diff options
| author | Sascha Hauer <s.hauer@pengutronix.de> | 2023-11-10 13:57:52 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2023-11-20 09:40:20 +0100 |
| commit | 0ba1e86d2ed63e292baab2605b2b54d2d8dbfc42 (patch) | |
| tree | 75e6b212eea5fcc00b466099e3f8367b20e262c9 | |
| parent | a75769c67dad5493a02c8ce7d60dbb64a0c9fd9f (diff) | |
| download | barebox-0ba1e86d2ed63e292baab2605b2b54d2d8dbfc42.tar.gz barebox-0ba1e86d2ed63e292baab2605b2b54d2d8dbfc42.tar.xz | |
ARM: i.MX93: Add DDR size read support
Link: https://lore.barebox.org/20231110125800.1901232-18-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| -rw-r--r-- | arch/arm/mach-imx/esdctl.c | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c index 2fca0a44a1..ac35a2de66 100644 --- a/arch/arm/mach-imx/esdctl.c +++ b/arch/arm/mach-imx/esdctl.c @@ -28,6 +28,7 @@ #include <mach/imx/vf610-ddrmc.h> #include <mach/imx/imx8m-regs.h> #include <mach/imx/imx7-regs.h> +#include <mach/imx/imx9-regs.h> struct imx_esdctl_data { unsigned long base0; @@ -555,6 +556,39 @@ static int imx8mn_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data) return _imx8m_ddrc_add_mem(mmdcbase, data, 16); } +#define IMX9_DDRC_CS_CONFIG(n) (0x80 + (n) * 4) +#define IMX9_DDRC_CS_ROW_BITS GENMASK(10, 8) +#define IMX9_DDRC_CS_COL_BITS GENMASK(2, 0) +#define IMX9_DDRC_CS_EN BIT(31) + +static int imx9_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data) +{ + int width = 2; + int banks = 8; + unsigned long mem = 0; + int i; + + for (i = 0; i < 2; i++) { + int rows, cols; + u32 cs, col_bits; + + cs = readl(mmdcbase + IMX9_DDRC_CS_CONFIG(i)); + if (!(cs & IMX9_DDRC_CS_EN)) + continue; + + rows = FIELD_GET(IMX9_DDRC_CS_ROW_BITS, cs) + 12; + col_bits = FIELD_GET(IMX9_DDRC_CS_COL_BITS, cs); + if (col_bits == 7) + cols = 7; + else + cols = col_bits + 8; + + mem += memory_sdram_size(cols, rows, banks, width); + } + + return arm_add_mem_device("ram0", data->base0, mem); +} + static resource_size_t imx7d_ddrc_sdram_size(void __iomem *ddrc) { const u32 addrmap[DDRC_ADDRMAP_LENGTH] = { @@ -695,6 +729,11 @@ static __maybe_unused struct imx_esdctl_data imx8mn_data = { .add_mem = imx8mn_ddrc_add_mem, }; +static __maybe_unused struct imx_esdctl_data imx9_data = { + .base0 = MX9_DDR_CSD1_BASE_ADDR, + .add_mem = imx9_ddrc_add_mem, +}; + static __maybe_unused struct imx_esdctl_data imx7d_data = { .base0 = MX7_DDR_BASE_ADDR, .add_mem = imx7d_ddrc_add_mem, @@ -771,6 +810,9 @@ static __maybe_unused struct of_device_id imx_esdctl_dt_ids[] = { .compatible = "fsl,imx8mn-ddrc", .data = &imx8mn_data }, { + .compatible = "fsl,imx93-ddrc", + .data = &imx9_data + }, { .compatible = "fsl,imx7d-ddrc", .data = &imx7d_data }, { |