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authorVyacheslav Yurkov <Vyacheslav.Yurkov@bruker.com>2022-11-01 11:33:26 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2022-11-02 09:07:08 +0100
commit28366ce804344b7055bfadf7970ea05cd7e52f56 (patch)
treedc1fc9cbab4afd332c9c98ec0a6ab8037ddcb108
parentb295e00bfab3ee1e2d157aea932803ad598ee878 (diff)
downloadbarebox-28366ce804344b7055bfadf7970ea05cd7e52f56.tar.gz
barebox-28366ce804344b7055bfadf7970ea05cd7e52f56.tar.xz
ARM: socfpga: Fix SDRAM firewall init
Incorrect enable bits were used in initialization sequence of SDRAM firewall. This enables the FPGA to access regions of SDRAM, which were previously inaccessible. Signed-off-by: Vyacheslav Yurkov <Vyacheslav.Yurkov@bruker.com> Link: https://lore.barebox.org/20221101103327.985435-1-uvv.mail@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r--arch/arm/mach-socfpga/arria10-sdram.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/mach-socfpga/arria10-sdram.c b/arch/arm/mach-socfpga/arria10-sdram.c
index 35c355df71..b7eade0b17 100644
--- a/arch/arm/mach-socfpga/arria10-sdram.c
+++ b/arch/arm/mach-socfpga/arria10-sdram.c
@@ -486,7 +486,7 @@ static int arria10_sdram_firewall_setup(void)
writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_MPUREGION3ADDR);
writel(0xffff0000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION0ADDR);
- mpu_en |= ARRIA10_NOC_FW_DDR_MPU_MPUREG1EN;
+ mpu_en |= ARRIA10_NOC_FW_DDR_MPU_F2SDR0REG0EN;
writel(mpu_en, ARRIA10_SDR_FW_MPU_FPGA_EN);
writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION1ADDR);
@@ -494,7 +494,7 @@ static int arria10_sdram_firewall_setup(void)
writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM0REGION3ADDR);
writel(0xffff0000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION0ADDR);
- mpu_en |= ARRIA10_NOC_FW_DDR_MPU_MPUREG2EN;
+ mpu_en |= ARRIA10_NOC_FW_DDR_MPU_F2SDR1REG0EN;
writel(mpu_en, ARRIA10_SDR_FW_MPU_FPGA_EN);
writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION1ADDR);
@@ -502,7 +502,7 @@ static int arria10_sdram_firewall_setup(void)
writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM1REGION3ADDR);
writel(0xffff0000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION0ADDR);
- mpu_en |= ARRIA10_NOC_FW_DDR_MPU_MPUREG3EN;
+ mpu_en |= ARRIA10_NOC_FW_DDR_MPU_F2SDR2REG0EN;
writel(mpu_en, ARRIA10_SDR_FW_MPU_FPGA_EN);
writel(0x00000000, ARRIA10_SDR_FW_MPU_FPGA_FPGA2SDRAM2REGION1ADDR);