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authorperachet7@gmail.com <perachet7@gmail.com>2018-11-08 15:34:29 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2018-11-09 08:13:18 +0100
commit459bf1fd31da2c091c6c1e3a7e0f6a1b1cbf588b (patch)
treeccaa36b630d91b36d71f97c21be5a862da5bf06b
parent20c12d090a1de80a3c58a232b4074067dcbb61a4 (diff)
downloadbarebox-459bf1fd31da2c091c6c1e3a7e0f6a1b1cbf588b.tar.gz
ARM: clk: rk3188: don't set same clk rate twice
We found setting a clock rate which has already been set, rk3188 (radxa rock pro) bails out. This is a quick fix only. Underlying situation not (yet) investigated: why it is even trying to set it to the same rate again. It remains to state that some but not all rrpro boards exhibit this behaviour, no other rk3188 boards have been tested. Signed-off-by: P. Rachet <perachet7@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r--drivers/clk/rockchip/clk-pll.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index f0dc120..87a3969 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -164,6 +164,9 @@ static int rockchip_rk3066_pll_set_rate(struct clk *hw, unsigned long drate,
int cur_parent;
int ret;
+ if (old_rate == drate)
+ return 0;
+
pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n",
__func__, __clk_get_name(hw), old_rate, drate, prate);