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authorSascha Hauer <sha@octopus.labnet.pengutronix.de>2007-09-21 14:18:25 +0200
committerSascha Hauer <sha@octopus.labnet.pengutronix.de>2007-09-21 14:18:25 +0200
commit9414ad39aff26db771d73db6e34eff1ba70fb90d (patch)
treebb311349ec22e75b2da1a76e698651ea5182ae0c
parentd323c2e1d2a0f6a5209a1fd7d5ebe3ab379e5637 (diff)
downloadbarebox-9414ad39aff26db771d73db6e34eff1ba70fb90d.tar.gz
barebox-9414ad39aff26db771d73db6e34eff1ba70fb90d.tar.xz
remove unported includes and drivers
Diffstat
-rw-r--r--include/74xx_7xx.h162
-rw-r--r--include/ata.h258
-rw-r--r--include/bedbug/bedbug.h42
-rw-r--r--include/bedbug/ppc.h413
-rw-r--r--include/bedbug/regs.h403
-rw-r--r--include/bedbug/tables.h601
-rw-r--r--include/commproc.h1818
-rw-r--r--include/dtt.h105
-rw-r--r--include/fdc.h37
-rw-r--r--include/i2c.h129
-rw-r--r--include/i8042.h76
-rw-r--r--include/ide.h55
-rw-r--r--include/jffs2/jffs2.h218
-rw-r--r--include/jffs2/load_kernel.h73
-rw-r--r--include/linux_logo.h1445
-rw-r--r--include/nand.h124
-rw-r--r--include/ns16550.h159
-rw-r--r--include/pc_keyb.h112
-rw-r--r--include/pci.h528
-rw-r--r--include/pci_ids.h2052
-rw-r--r--include/post.h97
-rw-r--r--include/scsi.h208
-rw-r--r--include/status_led.h369
-rw-r--r--include/systemace.h31
-rw-r--r--include/universe.h148
-rw-r--r--include/video.h19
-rw-r--r--include/video_ad7179.h36
-rw-r--r--include/video_easylogo.h23
-rw-r--r--include/video_logo.h1951
29 files changed, 0 insertions, 11692 deletions
diff --git a/include/74xx_7xx.h b/include/74xx_7xx.h
deleted file mode 100644
index 33e396a066..0000000000
--- a/include/74xx_7xx.h
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber, Mission Critical Linux, Inc. <huber@mclx.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * 74xx_7xx.h
- *
- * 74xx/7xx specific definitions
- */
-
-#ifndef __MPC74XX_H__
-#define __MPC74XX_H__
-
-/*----------------------------------------------------------------
- * Exception offsets (PowerPC standard)
- */
-#define EXC_OFF_SYS_RESET 0x0100 /* default system reset offset */
-
-/*----------------------------------------------------------------
- * l2cr values
- */
-#define l2cr 1017
-
-#define L2CR_L2E 0x80000000 /* bit 0 - enable */
-#define L2CR_L2PE 0x40000000 /* bit 1 - data parity */
-#define L2CR_L2SIZ_2M 0x00000000 /* bits 2-3 - 2MB, MPC7400 only! */
-#define L2CR_L2SIZ_1M 0x30000000 /* ... 1MB */
-#define L2CR_L2SIZ_HM 0x20000000 /* ... 512K */
-#define L2CR_L2SIZ_QM 0x10000000 /* ... 256k */
-#define L2CR_L2CLK_1 0x02000000 /* bits 4-6 clock ratio div 1 */
-#define L2CR_L2CLK_1_5 0x04000000 /* bits 4-6 clock ratio div 1.5 */
-#define L2CR_L2CLK_2 0x08000000 /* bits 4-6 clock ratio div 2 */
-#define L2CR_L2CLK_2_5 0x0a000000 /* bits 4-6 clock ratio div 2.5 */
-#define L2CR_L2CLK_3 0x0c000000 /* bits 4-6 clock ratio div 3 */
-#define L2CR_L2CLK_3_5 0x06000000 /* bits 4-6 clock ratio div 3.5 */
-#define L2CR_L2CLK_4 0x0e000000 /* bits 4-6 clock ratio div 4 */
-#define L2CR_L2RAM_BURST 0x01000000 /* bits 7-8 - burst SRAM */
-#define L2CR_DO 0x00400000 /* bit 9 - enable caching of instr. in L2 */
-#define L2CR_L2I 0x00200000 /* bit 10 - global invalidate bit */
-#define L2CR_L2CTL 0x00100000 /* bit 11 - l2 ram control */
-#define L2CR_L2WT 0x00080000 /* bit 12 - l2 write-through */
-#define L2CR_TS 0x00040000 /* bit 13 - test support on */
-#define L2CR_TS_OFF -L2CR_TS /* bit 13 - test support off */
-#define L2CR_L2OH_5 0x00000000 /* bits 14-15 - output hold time = short */
-#define L2CR_L2OH_1 0x00010000 /* bits 14-15 - output hold time = medium */
-#define L2CR_L2OH_INV 0x00020000 /* bits 14-15 - output hold time = long */
-#define L2CR_L2IP 0x00000001 /* global invalidate in progress */
-
-/*----------------------------------------------------------------
- * BAT settings. Look in config_<BOARD>.h for the actual setup
- */
-
-#define BATU_BL_128K 0x00000000
-#define BATU_BL_256K 0x00000004
-#define BATU_BL_512K 0x0000000c
-#define BATU_BL_1M 0x0000001c
-#define BATU_BL_2M 0x0000003c
-#define BATU_BL_4M 0x0000007c
-#define BATU_BL_8M 0x000000fc
-#define BATU_BL_16M 0x000001fc
-#define BATU_BL_32M 0x000003fc
-#define BATU_BL_64M 0x000007fc
-#define BATU_BL_128M 0x00000ffc
-#define BATU_BL_256M 0x00001ffc
-
-#define BATU_VS 0x00000002
-#define BATU_VP 0x00000001
-#define BATU_INVALID 0x00000000
-
-#define BATL_WRITETHROUGH 0x00000040
-#define BATL_CACHEINHIBIT 0x00000020
-#define BATL_MEMCOHERENCE 0x00000010
-#define BATL_GUARDEDSTORAGE 0x00000008
-#define BATL_NO_ACCESS 0x00000000
-
-#define BATL_PP_MSK 0x00000003
-#define BATL_PP_00 0x00000000 /* No access */
-#define BATL_PP_01 0x00000001 /* Read-only */
-#define BATL_PP_10 0x00000002 /* Read-write */
-#define BATL_PP_11 0x00000003
-
-#define BATL_PP_NO_ACCESS BATL_PP_00
-#define BATL_PP_RO BATL_PP_01
-#define BATL_PP_RW BATL_PP_10
-
-#ifndef __ASSEMBLY__
-/* cpu ids we detect */
-typedef enum __cpu_t {
- CPU_740, CPU_750,
- CPU_740P, CPU_750P,
- CPU_745, CPU_755,
- CPU_750CX, CPU_750FX, CPU_750GX,
- CPU_7400,
- CPU_7410,
- CPU_7448,
- CPU_7450, CPU_7455, CPU_7457,
- CPU_UNKNOWN} cpu_t;
-
-extern cpu_t get_cpu_type(void);
-
-#define l1icache_enable icache_enable
-
-void l2cache_enable(void);
-void l1dcache_enable(void);
-
-static __inline__ unsigned long get_msr (void)
-{
- unsigned long msr;
- asm volatile("mfmsr %0" : "=r" (msr) :);
- return msr;
-}
-
-static __inline__ void set_msr (unsigned long msr)
-{
- asm volatile("mtmsr %0" : : "r" (msr));
-}
-
-static __inline__ unsigned long get_hid0 (void)
-{
- unsigned long hid0;
- asm volatile("mfspr %0, 1008" : "=r" (hid0) :);
- return hid0;
-}
-
-static __inline__ unsigned long get_hid1 (void)
-{
- unsigned long hid1;
- asm volatile("mfspr %0, 1009" : "=r" (hid1) :);
- return hid1;
-}
-
-static __inline__ void set_hid0 (unsigned long hid0)
-{
- asm volatile("mtspr 1008, %0" : : "r" (hid0));
-}
-
-static __inline__ void set_hid1 (unsigned long hid1)
-{
- asm volatile("mtspr 1009, %0" : : "r" (hid1));
-}
-
-#endif /* __ASSEMBLY__ */
-#endif /* __MPC74XX_H__ */
diff --git a/include/ata.h b/include/ata.h
deleted file mode 100644
index 8584226eb0..0000000000
--- a/include/ata.h
+++ /dev/null
@@ -1,258 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Most of the following information was derived from the document
- * "Information Technology - AT Attachment-3 Interface (ATA-3)"
- * which can be found at:
- * http://www.dt.wdc.com/ata/ata-3/ata3r5v.zip
- * ftp://poctok.iae.nsk.su/pub/asm/Documents/IDE/ATA3R5V.ZIP
- * ftp://ftp.fee.vutbr.cz/pub/doc/io/ata/ata-3/ata3r5v.zip
- */
-
-#ifndef _ATA_H
-#define _ATA_H
-
-/* Register addressing depends on the hardware design; for instance,
- * 8-bit (register) and 16-bit (data) accesses might use different
- * address spaces. This is implemented by the following definitions.
- */
-#ifndef CFG_ATA_STRIDE
-#define CFG_ATA_STRIDE 1
-#endif
-
-#define ATA_IO_DATA(x) (CFG_ATA_DATA_OFFSET+((x) * CFG_ATA_STRIDE))
-#define ATA_IO_REG(x) (CFG_ATA_REG_OFFSET +((x) * CFG_ATA_STRIDE))
-#define ATA_IO_ALT(x) (CFG_ATA_ALT_OFFSET +((x) * CFG_ATA_STRIDE))
-
-/*
- * I/O Register Descriptions
- */
-#define ATA_DATA_REG ATA_IO_DATA(0)
-#define ATA_ERROR_REG ATA_IO_REG(1)
-#define ATA_SECT_CNT ATA_IO_REG(2)
-#define ATA_SECT_NUM ATA_IO_REG(3)
-#define ATA_CYL_LOW ATA_IO_REG(4)
-#define ATA_CYL_HIGH ATA_IO_REG(5)
-#define ATA_DEV_HD ATA_IO_REG(6)
-#define ATA_COMMAND ATA_IO_REG(7)
-#define ATA_DATA_EVEN ATA_IO_REG(8)
-#define ATA_DATA_ODD ATA_IO_REG(9)
-#define ATA_STATUS ATA_COMMAND
-#define ATA_DEV_CTL ATA_IO_ALT(6)
-#define ATA_LBA_LOW ATA_SECT_NUM
-#define ATA_LBA_MID ATA_CYL_LOW
-#define ATA_LBA_HIGH ATA_CYL_HIGH
-#define ATA_LBA_SEL ATA_DEV_CTL
-
-/*
- * Status register bits
- */
-#define ATA_STAT_BUSY 0x80 /* Device Busy */
-#define ATA_STAT_READY 0x40 /* Device Ready */
-#define ATA_STAT_FAULT 0x20 /* Device Fault */
-#define ATA_STAT_SEEK 0x10 /* Device Seek Complete */
-#define ATA_STAT_DRQ 0x08 /* Data Request (ready) */
-#define ATA_STAT_CORR 0x04 /* Corrected Data Error */
-#define ATA_STAT_INDEX 0x02 /* Vendor specific */
-#define ATA_STAT_ERR 0x01 /* Error */
-
-/*
- * Device / Head Register Bits
- */
-#define ATA_DEVICE(x) ((x & 1)<<4)
-#define ATA_LBA 0xE0
-
-/*
- * ATA Commands (only mandatory commands listed here)
- */
-#define ATA_CMD_READ 0x20 /* Read Sectors (with retries) */
-#define ATA_CMD_READN 0x21 /* Read Sectors ( no retries) */
-#define ATA_CMD_WRITE 0x30 /* Write Sectores (with retries)*/
-#define ATA_CMD_WRITEN 0x31 /* Write Sectors ( no retries)*/
-#define ATA_CMD_VRFY 0x40 /* Read Verify (with retries) */
-#define ATA_CMD_VRFYN 0x41 /* Read verify ( no retries) */
-#define ATA_CMD_SEEK 0x70 /* Seek */
-#define ATA_CMD_DIAG 0x90 /* Execute Device Diagnostic */
-#define ATA_CMD_INIT 0x91 /* Initialize Device Parameters */
-#define ATA_CMD_RD_MULT 0xC4 /* Read Multiple */
-#define ATA_CMD_WR_MULT 0xC5 /* Write Multiple */
-#define ATA_CMD_SETMULT 0xC6 /* Set Multiple Mode */
-#define ATA_CMD_RD_DMA 0xC8 /* Read DMA (with retries) */
-#define ATA_CMD_RD_DMAN 0xC9 /* Read DMS ( no retries) */
-#define ATA_CMD_WR_DMA 0xCA /* Write DMA (with retries) */
-#define ATA_CMD_WR_DMAN 0xCB /* Write DMA ( no retires) */
-#define ATA_CMD_IDENT 0xEC /* Identify Device */
-#define ATA_CMD_SETF 0xEF /* Set Features */
-#define ATA_CMD_CHK_PWR 0xE5 /* Check Power Mode */
-
-#define ATA_CMD_READ_EXT 0x24 /* Read Sectors (with retries) with 48bit addressing */
-#define ATA_CMD_WRITE_EXT 0x34 /* Write Sectores (with retries) with 48bit addressing */
-#define ATA_CMD_VRFY_EXT 0x42 /* Read Verify (with retries) with 48bit addressing */
-
-/*
- * ATAPI Commands
- */
-#define ATAPI_CMD_IDENT 0xA1 /* Identify AT Atachment Packed Interface Device */
-#define ATAPI_CMD_PACKET 0xA0 /* Packed Command */
-
-
-#define ATAPI_CMD_INQUIRY 0x12
-#define ATAPI_CMD_REQ_SENSE 0x03
-#define ATAPI_CMD_READ_CAP 0x25
-#define ATAPI_CMD_START_STOP 0x1B
-#define ATAPI_CMD_READ_12 0xA8
-
-
-#define ATA_GET_ERR() inb(ATA_STATUS)
-#define ATA_GET_STAT() inb(ATA_STATUS)
-#define ATA_OK_STAT(stat,good,bad) (((stat)&((good)|(bad)))==(good))
-#define ATA_BAD_R_STAT (ATA_STAT_BUSY | ATA_STAT_ERR)
-#define ATA_BAD_W_STAT (ATA_BAD_R_STAT | ATA_STAT_FAULT)
-#define ATA_BAD_STAT (ATA_BAD_R_STAT | ATA_STAT_DRQ)
-#define ATA_DRIVE_READY (ATA_READY_STAT | ATA_STAT_SEEK)
-#define ATA_DATA_READY (ATA_STAT_DRQ)
-
-#define ATA_BLOCKSIZE 512 /* bytes */
-#define ATA_BLOCKSHIFT 9 /* 2 ^ ATA_BLOCKSIZESHIFT = 512 */
-#define ATA_SECTORWORDS (512 / sizeof(unsigned long))
-
-#ifndef ATA_RESET_TIME
-#define ATA_RESET_TIME 60 /* spec allows up to 31 seconds */
-#endif
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * structure returned by ATA_CMD_IDENT, as per ANSI ATA2 rev.2f spec
- */
-typedef struct hd_driveid {
- unsigned short config; /* lots of obsolete bit flags */
- unsigned short cyls; /* "physical" cyls */
- unsigned short reserved2; /* reserved (word 2) */
- unsigned short heads; /* "physical" heads */
- unsigned short track_bytes; /* unformatted bytes per track */
- unsigned short sector_bytes; /* unformatted bytes per sector */
- unsigned short sectors; /* "physical" sectors per track */
- unsigned short vendor0; /* vendor unique */
- unsigned short vendor1; /* vendor unique */
- unsigned short vendor2; /* vendor unique */
- unsigned char serial_no[20]; /* 0 = not_specified */
- unsigned short buf_type;
- unsigned short buf_size; /* 512 byte increments; 0 = not_specified */
- unsigned short ecc_bytes; /* for r/w long cmds; 0 = not_specified */
- unsigned char fw_rev[8]; /* 0 = not_specified */
- unsigned char model[40]; /* 0 = not_specified */
- unsigned char max_multsect; /* 0=not_implemented */
- unsigned char vendor3; /* vendor unique */
- unsigned short dword_io; /* 0=not_implemented; 1=implemented */
- unsigned char vendor4; /* vendor unique */
- unsigned char capability; /* bits 0:DMA 1:LBA 2:IORDYsw 3:IORDYsup*/
- unsigned short reserved50; /* reserved (word 50) */
- unsigned char vendor5; /* vendor unique */
- unsigned char tPIO; /* 0=slow, 1=medium, 2=fast */
- unsigned char vendor6; /* vendor unique */
- unsigned char tDMA; /* 0=slow, 1=medium, 2=fast */
- unsigned short field_valid; /* bits 0:cur_ok 1:eide_ok */
- unsigned short cur_cyls; /* logical cylinders */
- unsigned short cur_heads; /* logical heads */
- unsigned short cur_sectors; /* logical sectors per track */
- unsigned short cur_capacity0; /* logical total sectors on drive */
- unsigned short cur_capacity1; /* (2 words, misaligned int) */
- unsigned char multsect; /* current multiple sector count */
- unsigned char multsect_valid; /* when (bit0==1) multsect is ok */
- unsigned int lba_capacity; /* total number of sectors */
- unsigned short dma_1word; /* single-word dma info */
- unsigned short dma_mword; /* multiple-word dma info */
- unsigned short eide_pio_modes; /* bits 0:mode3 1:mode4 */
- unsigned short eide_dma_min; /* min mword dma cycle time (ns) */
- unsigned short eide_dma_time; /* recommended mword dma cycle time (ns) */
- unsigned short eide_pio; /* min cycle time (ns), no IORDY */
- unsigned short eide_pio_iordy; /* min cycle time (ns), with IORDY */
- unsigned short words69_70[2]; /* reserved words 69-70 */
- unsigned short words71_74[4]; /* reserved words 71-74 */
- unsigned short queue_depth; /* */
- unsigned short words76_79[4]; /* reserved words 76-79 */
- unsigned short major_rev_num; /* */
- unsigned short minor_rev_num; /* */
- unsigned short command_set_1; /* bits 0:Smart 1:Security 2:Removable 3:PM */
- unsigned short command_set_2; /* bits 14:Smart Enabled 13:0 zero 10:lba48 support*/
- unsigned short cfsse; /* command set-feature supported extensions */
- unsigned short cfs_enable_1; /* command set-feature enabled */
- unsigned short cfs_enable_2; /* command set-feature enabled */
- unsigned short csf_default; /* command set-feature default */
- unsigned short dma_ultra; /* */
- unsigned short word89; /* reserved (word 89) */
- unsigned short word90; /* reserved (word 90) */
- unsigned short CurAPMvalues; /* current APM values */
- unsigned short word92; /* reserved (word 92) */
- unsigned short hw_config; /* hardware config */
- unsigned short words94_99[6];/* reserved words 94-99 */
- /*unsigned long long lba48_capacity; /--* 4 16bit values containing lba 48 total number of sectors */
- unsigned short lba48_capacity[4]; /* 4 16bit values containing lba 48 total number of sectors */
- unsigned short words104_125[22];/* reserved words 104-125 */
- unsigned short last_lun; /* reserved (word 126) */
- unsigned short word127; /* reserved (word 127) */
- unsigned short dlf; /* device lock function
- * 15:9 reserved
- * 8 security level 1:max 0:high
- * 7:6 reserved
- * 5 enhanced erase
- * 4 expire
- * 3 frozen
- * 2 locked
- * 1 en/disabled
- * 0 capability
- */
- unsigned short csfo; /* current set features options
- * 15:4 reserved
- * 3 auto reassign
- * 2 reverting
- * 1 read-look-ahead
- * 0 write cache
- */
- unsigned short words130_155[26];/* reserved vendor words 130-155 */
- unsigned short word156;
- unsigned short words157_159[3];/* reserved vendor words 157-159 */
- unsigned short words160_255[95];/* reserved words 160-255 */
-} hd_driveid_t;
-
-
-/*
- * PIO Mode Configuration
- *
- * See ATA-3 (AT Attachment-3 Interface) documentation, Figure 14 / Table 21
- */
-
-typedef struct {
- unsigned int t_setup; /* Setup Time in [ns] or clocks */
- unsigned int t_length; /* Length Time in [ns] or clocks */
- unsigned int t_hold; /* Hold Time in [ns] or clocks */
-}
-pio_config_t;
-
-#define IDE_MAX_PIO_MODE 4 /* max suppurted PIO mode */
-
-/* ------------------------------------------------------------------------- */
-
-#endif /* _ATA_H */
diff --git a/include/bedbug/bedbug.h b/include/bedbug/bedbug.h
deleted file mode 100644
index 471215ee02..0000000000
--- a/include/bedbug/bedbug.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* $Id$ */
-
-#ifndef _BEDBUG_H
-#define _BEDBUG_H
-
-#ifndef NULL
-#define NULL 0
-#endif
-
-#define _USE_PROTOTYPES
-
-#ifndef isblank
-#define isblank(c) isspace((int)(c))
-#endif
-
-#ifndef __P
-#if defined(_USE_PROTOTYPES) && (defined(__STDC__) || defined(__cplusplus))
-#define __P(protos) protos /* full-blown ANSI C */
-#else
-#define __P(protos) () /* traditional C preprocessor */
-#endif
-#endif
-
-#define assert( condition ) if( (condition) ) _exit(0)
-
-#endif /* _BEDBUG_H */
-
-
-/*
- * Copyright (c) 2001 William L. Pitts
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are freely
- * permitted provided that the above copyright notice and this
- * paragraph and the following disclaimer are duplicated in all
- * such forms.
- *
- * This software is provided "AS IS" and without any express or
- * implied warranties, including, without limitation, the implied
- * warranties of merchantability and fitness for a particular
- * purpose.
- */
diff --git a/include/bedbug/ppc.h b/include/bedbug/ppc.h
deleted file mode 100644
index 9cc8f9fa38..0000000000
--- a/include/bedbug/ppc.h
+++ /dev/null
@@ -1,413 +0,0 @@
-/* $Id$ */
-
-#ifndef _PPC_H
-#define _PPC_H
-
-/*======================================================================
- *
- * OPERANDS
- *
- *======================================================================*/
-
-enum OP_FIELD {
- O_AA = 1, O_BD, O_BI, O_BO, O_crbD, O_crbA, O_crbB, O_CRM, O_d, O_frC, O_frD,
- O_frS, O_IMM, O_LI, O_LK, O_MB, O_ME, O_NB, O_OE, O_rA, O_rB, O_Rc, O_rD,
- O_rS, O_SH, O_SIMM, O_SR, O_TO, O_UIMM, O_crfD, O_crfS, O_L, O_spr, O_tbr,
- O_cr2 };
-
-struct operand {
- enum OP_FIELD field; /* The operand identifier from the
- enum above */
-
- char * name; /* Symbolic name of this operand */
-
- unsigned int bits; /* The number of bits used by this
- operand */
-
- unsigned int shift; /* How far to the right the operand
- should be shifted so that it is
- aligned at the beginning of the
- word */
-
- unsigned int hint; /* A bitwise-inclusive-OR of the
- values shown below. These are used
- tell the disassembler how to print
- this operand */
-};
-
-/* Values for operand hint */
-#define OH_SILENT 0x01 /* dont print this operand */
-#define OH_ADDR 0x02 /* this operand is an address */
-#define OH_REG 0x04 /* this operand is a register */
-#define OH_SPR 0x08 /* this operand is an SPR */
-#define OH_TBR 0x10 /* this operand is a TBR */
-#define OH_OFFSET 0x20 /* this operand is an offset */
-#define OH_LITERAL 0x40 /* a literal string */
-
-
-/*======================================================================
- *
- * OPCODES
- *
- *======================================================================*/
-
-/* From the MPCxxx instruction set documentation, all instructions are
- * 32 bits long and word aligned. Bits 0-5 always specify the primary
- * opcode. Many instructions also have an extended opcode.
- */
-
-#define GET_OPCD(i) (((unsigned long)(i) >> 26) & 0x3f)
-#define MAKE_OPCODE(i) ((((unsigned long)(i)) & 0x3f) << 26)
-
-/* The MPC860 User's Manual, Appendix D.4 contains the definitions of the
- * instruction forms
- */
-
-
-/*-------------------------------------------------
- * I-Form Instructions:
- * bX
- *-------------------------------------------------
- * OPCD | LI |AA|LK
- *-------------------------------------------------*/
-
-#define I_OPCODE(i,aa,lk) (MAKE_OPCODE(i) | (((aa) & 0x1) << 1) | ((lk) & 0x1))
-#define I_MASK I_OPCODE(0x3f,0x1,0x1)
-
-
-/*-------------------------------------------------
- * B-Form Instructions:
- * bcX
- *-------------------------------------------------
- * OPCD | BO | BI | BD |AA|LK
- *-------------------------------------------------*/
-
-#define B_OPCODE(i,aa,lk) (MAKE_OPCODE(i) | (((aa) & 0x1) << 1) | ((lk) & 0x1))
-#define B_MASK B_OPCODE(0x3f,0x1,0x1)
-
-
-/*-------------------------------------------------
- * SC-Form Instructions:
- * sc
- *-------------------------------------------------
- * OPCD | 00000 | 00000 | 00000000000000 |1|0
- *-------------------------------------------------*/
-
-#define SC_OPCODE(i) (MAKE_OPCODE(i) | 0x2)
-#define SC_MASK SC_OPCODE(0x3f)
-
-
-/*-------------------------------------------------
- * D-Form Instructions:
- * addi addic addic. addis andi. andis. cmpi cmpli
- * lbz lbzu lha lhau lhz lhzu lmw lwz lwzu mulli
- * ori oris stb stbu sth sthu stmw stw stwu subfic
- * twi xori xoris
- *-------------------------------------------------
- * OPCD | D | A | d
- * OPCD | D | A | SIMM
- * OPCD | S | A | d
- * OPCD | S | A | UIMM
- * OPCD |crfD|0|L| A | SIMM
- * OPCD |crfD|0|L| A | UIMM
- * OPCD | TO | A | SIMM
- *-------------------------------------------------*/
-
-#define D_OPCODE(i) MAKE_OPCODE(i)
-#define D_MASK MAKE_OPCODE(0x3f)
-
-
-/*-------------------------------------------------
- * DS-Form Instructions:
- * (none supported by MPC860)
- *-------------------------------------------------
- * OPCD | D | A | ds |XO
- * OPCD | S | A | ds |XO
- *-------------------------------------------------*/
-
-#define DS_OPCODE(i,xo) (MAKE_OPCODE(i) | ((xo) & 0x3))
-#define DS_MASK DS_OPCODE(0x3f,0x1)
-
-
-/*---------------------------------------------------
- * X-Form Instructions:
- * andX andcX cmp cmpl cntlzwX dcbf dcbi dcbst dcbt
- * dcbtst dcbz eciwx ecowx eieio eqvX extsbX extshX
- * icbi lbzux lbxz lhaux lhax lhbrx lhzux lhxz lswi
- * lswx lwarx lwbrx lwzux lwxz mcrfs mcrxr mfcr
- * mfmsr mfsr mfsrin mtmsr mtsr mtsrin nandX norX
- * orX orcX slwX srawX srawiX srwX stbux stbx
- * sthbrx sthuxsthx stswi stswx stwbrx stwcx. stwux
- * stwx sync tlbie tlbld tlbli tlbsync tw xorX
- *---------------------------------------------------
- * OPCD | D | A | B | XO |0
- * OPCD | D | A | NB | XO |0
- * OPCD | D | 00000 | B | XO |0
- * OPCD | D | 00000 | 00000 | XO |0
- * OPCD | D |0| SR | 00000 | XO |0
- * OPCD | S | A | B | XO |Rc
- * OPCD | S | A | B | XO |1
- * OPCD | S | A | B | XO |0
- * OPCD | S | A | NB | XO |0
- * OPCD | S | A | 00000 | XO |Rc
- * OPCD | S | 00000 | B | XO |0
- * OPCD | S | 00000 | 00000 | XO |0
- * OPCD | S |0| SR | 00000 | XO |0
- * OPCD | S | A | SH | XO |Rc
- * OPCD |crfD|0|L| A | SH | XO |0
- * OPCD |crfD |00| A | B | XO |0
- * OPCD |crfD |00|crfS |00| 00000 | XO |0
- * OPCD |crfD |00| 00000 | 00000 | XO |0
- * OPCD |crfD |00| 00000 | IMM |0| XO |Rc
- * OPCD | TO | A | B | XO |0
- * OPCD | D | 00000 | B | XO |Rc
- * OPCD | D | 00000 | 00000 | XO |Rc
- * OPCD | crbD | 00000 | 00000 | XO |Rc
- * OPCD | 00000 | A | B | XO |0
- * OPCD | 00000 | 00000 | B | XO |0
- * OPCD | 00000 | 00000 | 00000 | XO |0
- *---------------------------------------------------*/
-
-#define X_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
- ((rc) & 0x1))
-#define X_MASK X_OPCODE(0x3f,0x3ff,0x1)
-
-
-/*---------------------------------------------------
- * XL-Form Instructions:
- * bcctrX bclrX crand crandc creqv crnand crnor cror
- * croc crxorisync mcrf rfi
- *---------------------------------------------------
- * OPCD | BO | BI | 00000 | XO |LK
- * OPCD | crbD | crbA | crbB | XO |0
- * OPCD |crfD |00|crfS |00| 00000 | XO |0
- * OPCD | 00000 | 00000 | 00000 | XO |0
- *---------------------------------------------------*/
-
-#define XL_OPCODE(i,xo,lk) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
- ((lk) & 0x1))
-#define XL_MASK XL_OPCODE(0x3f,0x3ff,0x1)
-
-
-/*---------------------------------------------------
- * XFX-Form Instructions:
- * mfspr mftb mtcrf mtspr
- *---------------------------------------------------
- * OPCD | D | spr | XO |0
- * OPCD | D |0| CRM |0| XO |0
- * OPCD | S | spr | XO |0
- * OPCD | D | tbr | XO |0
- *---------------------------------------------------*/
-
-#define XFX_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
- ((rc) & 0x1))
-#define XFX_MASK XFX_OPCODE(0x3f,0x3ff,0x1)
-
-
-/*---------------------------------------------------
- * XFL-Form Instructions:
- * (none supported by MPC860)
- *---------------------------------------------------
- * OPCD |0| FM |0| B | XO |0
- *---------------------------------------------------*/
-
-#define XFL_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
- ((rc) & 0x1))
-#define XFL_MASK XFL_OPCODE(0x3f,0x3ff,0x1)
-
-
-/*---------------------------------------------------
- * XS-Form Instructions:
- * (none supported by MPC860)
- *---------------------------------------------------
- * OPCD | S | A | sh | XO |sh|LK
- *---------------------------------------------------*/
-
-#define XS_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x1ff) << 2) | \
- ((rc) & 0x1))
-#define XS_MASK XS_OPCODE(0x3f,0x1ff,0x1)
-
-
-/*---------------------------------------------------
- * XO-Form Instructions:
- * addX addcXaddeX addmeX addzeX divwX divwuX mulhwX
- * mulhwuX mullwX negX subfX subfcX subfeX subfmeX
- * subfzeX
- *---------------------------------------------------
- * OPCD | D | A | B |OE| XO |Rc
- * OPCD | D | A | B |0 | XO |Rc
- * OPCD | D | A | 00000 |OE| XO |Rc
- *---------------------------------------------------*/
-
-#define XO_OPCODE(i,xo,oe,rc) (MAKE_OPCODE(i) | (((oe) & 0x1) << 10) | \
- (((xo) & 0x1ff) << 1) | ((rc) & 0x1))
-#define XO_MASK XO_OPCODE(0x3f,0x1ff,0x1,0x1)
-
-
-/*---------------------------------------------------
- * A-Form Instructions:
- * (none supported by MPC860)
- *---------------------------------------------------
- * OPCD | D | A | B |00000| XO |Rc
- * OPCD | D | A | B | C | XO |Rc
- * OPCD | D | A | 00000 | C | XO |Rc
- * OPCD | D | 00000 | B |00000| XO |Rc
- *---------------------------------------------------*/
-
-#define A_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x1f) << 1) | \
- ((rc) & 0x1))
-#define A_MASK A_OPCODE(0x3f,0x1f,0x1)
-
-
-/*---------------------------------------------------
- * M-Form Instructions:
- * rlwimiX rlwinmX rlwnmX
- *---------------------------------------------------
- * OPCD | S | A | SH | MB | ME |Rc
- * OPCD | S | A | B | MB | ME |Rc
- *---------------------------------------------------*/
-
-#define M_OPCODE(i,rc) (MAKE_OPCODE(i) | ((rc) & 0x1))
-#define M_MASK M_OPCODE(0x3f,0x1)
-
-
-/*---------------------------------------------------
- * MD-Form Instructions:
- * (none supported by MPC860)
- *---------------------------------------------------
- * OPCD | S | A | sh | mb | XO |sh|Rc
- * OPCD | S | A | sh | me | XO |sh|Rc
- *---------------------------------------------------*/
-
-#define MD_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x7) << 2) | \
- ((rc) & 0x1))
-#define MD_MASK MD_OPCODE(0x3f,0x7,0x1)
-
-
-/*---------------------------------------------------
- * MDS-Form Instructions:
- * (none supported by MPC860)
- *---------------------------------------------------
- * OPCD | S | A | B | mb | XO |Rc
- * OPCD | S | A | B | me | XO |Rc
- *---------------------------------------------------*/
-
-#define MDS_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0xf) << 1) | \
- ((rc) & 0x1))
-#define MDS_MASK MDS_OPCODE(0x3f,0xf,0x1)
-
-#ifndef FALSE
-#define FALSE 0
-#define TRUE (!FALSE)
-#endif
-
-#define INSTRUCTION( memaddr ) ntohl(*(unsigned long *)(memaddr))
-
-#define MAX_OPERANDS 8
-
-struct ppc_ctx;
-
-struct opcode {
- unsigned long opcode; /* The complete opcode as produced by
- one of the XXX_OPCODE macros above */
-
- unsigned long mask; /* The mask to use on an instruction
- before comparing with the opcode
- field to see if it matches */
-
- enum OP_FIELD fields[MAX_OPERANDS];
- /* An array defining the operands for
- this opcode. The values of the
- array are the operand identifiers */
-
- int (*hfunc)(struct ppc_ctx *);
- /* Address of a function to handle the given
- mnemonic */
-
- char * name; /* The symbolic name of this opcode */
-
- unsigned int hint; /* A bitwise-inclusive-OR of the
- values shown below. These are used
- tell the disassembler how to print
- some operands for this opcode */
-};
-
-/* values for opcode hints */
-#define H_RELATIVE 0x1 /* The address operand is relative */
-#define H_IMM_HIGH 0x2 /* [U|S]IMM field shifted high */
-#define H_RA0_IS_0 0x4 /* If rA = 0 then treat as literal 0 */
-
-struct ppc_ctx {
- struct opcode * op;
- unsigned long instr;
- unsigned int flags;
- int datalen;
- char data[ 256 ];
- char radix_fmt[ 8 ];
- unsigned char * virtual;
-};
-
-
-/*======================================================================
- *
- * FUNCTIONS
- *
- *======================================================================*/
-
-/* Values for flags as passed to various ppc routines */
-#define F_RADOCTAL 0x1 /* output radix = unsigned octal */
-#define F_RADUDECIMAL 0x2 /* output radix = unsigned decimal */
-#define F_RADSDECIMAL 0x4 /* output radix = signed decimal */
-#define F_RADHEX 0x8 /* output radix = unsigned hex */
-#define F_SIMPLE 0x10 /* use simplified mnemonics */
-#define F_SYMBOL 0x20 /* use symbol lookups for addresses */
-#define F_INSTR 0x40 /* output the raw instruction */
-#define F_LOCALMEM 0x80 /* retrieve opcodes from local memory
- rather than from the HMI */
-#define F_LINENO 0x100 /* show line number info if available */
-#define F_VALIDONLY 0x200 /* cache: valid entries only */
-
-/* Values for assembler error codes */
-#define E_ASM_BAD_OPCODE 1
-#define E_ASM_NUM_OPERANDS 2
-#define E_ASM_BAD_REGISTER 3
-#define E_ASM_BAD_SPR 4
-#define E_ASM_BAD_TBR 5
-
-extern int disppc __P((unsigned char *,unsigned char *,int,
- int (*)(const char *), unsigned long));
-extern int print_source_line __P((char *,char *,int,
- int (*pfunc)(const char *)));
-extern int find_next_address __P((unsigned char *,int,struct pt_regs *));
-extern int handle_bc __P((struct ppc_ctx *));
-extern unsigned long asmppc __P((unsigned long,char*,int*));
-extern char *asm_error_str __P((int));
-
-/*======================================================================
- *
- * GLOBAL VARIABLES
- *
- *======================================================================*/
-
-extern struct operand operands[];
-extern const unsigned int n_operands;
-extern struct opcode opcodes[];
-extern const unsigned int n_opcodes;
-
-#endif /* _PPC_H */
-
-
-/*
- * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are freely
- * permitted provided that the above copyright notice and this
- * paragraph and the following disclaimer are duplicated in all
- * such forms.
- *
- * This software is provided "AS IS" and without any express or
- * implied warranties, including, without limitation, the implied
- * warranties of merchantability and fitness for a particular
- * purpose.
- */
diff --git a/include/bedbug/regs.h b/include/bedbug/regs.h
deleted file mode 100644
index 938e435c55..0000000000
--- a/include/bedbug/regs.h
+++ /dev/null
@@ -1,403 +0,0 @@
-/* $Id$ */
-
-#ifndef _REGS_H
-#define _REGS_H
-
-/* Special Purpose Registers */
-
-#define SPR_CR -1
-#define SPR_MSR -2
-
-#define SPR_XER 1
-#define SPR_LR 8
-#define SPR_CTR 9
-#define SPR_DSISR 18
-#define SPR_DAR 19
-#define SPR_DEC 22
-#define SPR_SRR0 26
-#define SPR_SRR1 27
-#define SPR_EIE 80
-#define SPR_EID 81
-#define SPR_CMPA 144
-#define SPR_CMPB 145
-#define SPR_CMPC 146
-#define SPR_CMPD 147
-#define SPR_ICR 148
-#define SPR_DER 149
-#define SPR_COUNTA 150
-#define SPR_COUNTB 151
-#define SPR_CMPE 152
-#define SPR_CMPF 153
-#define SPR_CMPG 154
-#define SPR_CMPH 155
-#define SPR_LCTRL1 156
-#define SPR_LCTRL2 157
-#define SPR_ICTRL 158
-#define SPR_BAR 159
-#define SPR_USPRG0 256
-#define SPR_SPRG4_RO 260
-#define SPR_SPRG5_RO 261
-#define SPR_SPRG6_RO 262
-#define SPR_SPRG7_RO 263
-#define SPR_SPRG0 272
-#define SPR_SPRG1 273
-#define SPR_SPRG2 274
-#define SPR_SPRG3 275
-#define SPR_SPRG4 276
-#define SPR_SPRG5 277
-#define SPR_SPRG6 278
-#define SPR_SPRG7 279
-#define SPR_EAR 282 /* MPC603e core */
-#define SPR_TBL 284
-#define SPR_TBU 285
-#define SPR_PVR 287
-#define SPR_IC_CST 560
-#define SPR_IC_ADR 561
-#define SPR_IC_DAT 562
-#define SPR_DC_CST 568
-#define SPR_DC_ADR 569
-#define SPR_DC_DAT 570
-#define SPR_DPDR 630
-#define SPR_IMMR 638
-#define SPR_MI_CTR 784
-#define SPR_MI_AP 786
-#define SPR_MI_EPN 787
-#define SPR_MI_TWC 789
-#define SPR_MI_RPN 790
-#define SPR_MD_CTR 792
-#define SPR_M_CASID 793
-#define SPR_MD_AP 794
-#define SPR_MD_EPN 795
-#define SPR_M_TWB 796
-#define SPR_MD_TWC 797
-#define SPR_MD_RPN 798
-#define SPR_M_TW 799
-#define SPR_MI_DBCAM 816
-#define SPR_MI_DBRAM0 817
-#define SPR_MI_DBRAM1 818
-#define SPR_MD_DBCAM 824
-#define SPR_MD_DBRAM0 825
-#define SPR_MD_DBRAM1 826
-#define SPR_ZPR 944
-#define SPR_PID 945
-#define SPR_CCR0 947
-#define SPR_IAC3 948
-#define SPR_IAC4 949
-#define SPR_DVC1 950
-#define SPR_DVC2 951
-#define SPR_SGR 953
-#define SPR_DCWR 954
-#define SPR_SLER 955
-#define SPR_SU0R 956
-#define SPR_DBCR1 957
-#define SPR_ICDBDR 979
-#define SPR_ESR 980
-#define SPR_DEAR 981
-#define SPR_EVPR 982
-#define SPR_TSR 984
-#define SPR_TCR 986
-#define SPR_PIT 987
-#define SPR_SRR2 990
-#define SPR_SRR3 991
-#define SPR_DBSR 1008
-#define SPR_DBCR0 1010
-#define SPR_IABR 1010 /* MPC603e core */
-#define SPR_IAC1 1012
-#define SPR_IAC2 1013
-#define SPR_DAC1 1014
-#define SPR_DAC2 1015
-#define SPR_DCCR 1018
-#define SPR_ICCR 1019
-
-/* Bits for the DBCR0 register */
-#define DBCR0_EDM 0x80000000
-#define DBCR0_IDM 0x40000000
-#define DBCR0_RST 0x30000000
-#define DBCR0_IC 0x08000000
-#define DBCR0_BT 0x04000000
-#define DBCR0_EDE 0x02000000
-#define DBCR0_TDE 0x01000000
-#define DBCR0_IA1 0x00800000
-#define DBCR0_IA2 0x00400000
-#define DBCR0_IA12 0x00200000
-#define DBCR0_IA12X 0x00100000
-#define DBCR0_IA3 0x00080000
-#define DBCR0_IA4 0x00040000
-#define DBCR0_IA34 0x00020000
-#define DBCR0_IA34X 0x00010000
-#define DBCR0_IA12T 0x00008000
-#define DBCR0_IA34T 0x00004000
-#define DBCR0_FT 0x00000001
-
-/* Bits for the DBCR1 register */
-#define DBCR1_D1R 0x80000000
-#define DBCR1_D2R 0x40000000
-#define DBCR1_D1W 0x20000000
-#define DBCR1_D2W 0x10000000
-#define DBCR1_D1S 0x0C000000
-#define DBCR1_D2S 0x03000000
-#define DBCR1_DA12 0x00800000
-#define DBCR1_DA12X 0x00400000
-#define DBCR1_DV1M 0x000C0000
-#define DBCR1_DV2M 0x00030000
-#define DBCR1_DV1BE 0x0000F000
-#define DBCR1_DV2BE 0x00000F00
-
-/* Bits for the DBSR register */
-#define DBSR_IC 0x80000000
-#define DBSR_BT 0x40000000
-#define DBSR_EDE 0x20000000
-#define DBSR_TIE 0x10000000
-#define DBSR_UDE 0x08000000
-#define DBSR_IA1 0x04000000
-#define DBSR_IA2 0x02000000
-#define DBSR_DR1 0x01000000
-#define DBSR_DW1 0x00800000
-#define DBSR_DR2 0x00400000
-#define DBSR_DW2 0x00200000
-#define DBSR_IDE 0x00100000
-#define DBSR_IA3 0x00080000
-#define DBSR_IA4 0x00040000
-#define DBSR_MRR 0x00000300
-
-struct spr_info {
- int spr_val;
- char spr_name[ 10 ];
-};
-
-extern struct spr_info spr_map[];
-extern const unsigned int n_sprs;
-
-
-#define SET_REGISTER( str, val ) \
-({ unsigned long __value = (val); \
- asm volatile( str : : "r" (__value)); \
- __value; })
-
-#define GET_REGISTER( str ) \
-({ unsigned long __value; \
- asm volatile( str : "=r" (__value) : ); \
- __value; })
-
-#define GET_CR() GET_REGISTER( "mfcr %0" )
-#define SET_CR(val) SET_REGISTER( "mtcr %0", val )
-#define GET_MSR() GET_REGISTER( "mfmsr %0" )
-#define SET_MSR(val) SET_REGISTER( "mtmsr %0", val )
-#define GET_XER() GET_REGISTER( "mfspr %0,1" )
-#define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val )
-#define GET_LR() GET_REGISTER( "mfspr %0,8" )
-#define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val )
-#define GET_CTR() GET_REGISTER( "mfspr %0,9" )
-#define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val )
-#define GET_DSISR() GET_REGISTER( "mfspr %0,18" )
-#define SET_DSISR(val) SET_REGISTER( "mtspr 18,%0", val )
-#define GET_DAR() GET_REGISTER( "mfspr %0,19" )
-#define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val )
-#define GET_DEC() GET_REGISTER( "mfspr %0,22" )
-#define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val )
-#define GET_SRR0() GET_REGISTER( "mfspr %0,26" )
-#define SET_SRR0(val) SET_REGISTER( "mtspr 26,%0", val )
-#define GET_SRR1() GET_REGISTER( "mfspr %0,27" )
-#define SET_SRR1(val) SET_REGISTER( "mtspr 27,%0", val )
-#define GET_EIE() GET_REGISTER( "mfspr %0,80" )
-#define SET_EIE(val) SET_REGISTER( "mtspr 80,%0", val )
-#define GET_EID() GET_REGISTER( "mfspr %0,81" )
-#define SET_EID(val) SET_REGISTER( "mtspr 81,%0", val )
-#define GET_CMPA() GET_REGISTER( "mfspr %0,144" )
-#define SET_CMPA(val) SET_REGISTER( "mtspr 144,%0", val )
-#define GET_CMPB() GET_REGISTER( "mfspr %0,145" )
-#define SET_CMPB(val) SET_REGISTER( "mtspr 145,%0", val )
-#define GET_CMPC() GET_REGISTER( "mfspr %0,146" )
-#define SET_CMPC(val) SET_REGISTER( "mtspr 146,%0", val )
-#define GET_CMPD() GET_REGISTER( "mfspr %0,147" )
-#define SET_CMPD(val) SET_REGISTER( "mtspr 147,%0", val )
-#define GET_ICR() GET_REGISTER( "mfspr %0,148" )
-#define SET_ICR(val) SET_REGISTER( "mtspr 148,%0", val )
-#define GET_DER() GET_REGISTER( "mfspr %0,149" )
-#define SET_DER(val) SET_REGISTER( "mtspr 149,%0", val )
-#define GET_COUNTA() GET_REGISTER( "mfspr %0,150" )
-#define SET_COUNTA(val) SET_REGISTER( "mtspr 150,%0", val )
-#define GET_COUNTB() GET_REGISTER( "mfspr %0,151" )
-#define SET_COUNTB(val) SET_REGISTER( "mtspr 151,%0", val )
-#define GET_CMPE() GET_REGISTER( "mfspr %0,152" )
-#define SET_CMPE(val) SET_REGISTER( "mtspr 152,%0", val )
-#define GET_CMPF() GET_REGISTER( "mfspr %0,153" )
-#define SET_CMPF(val) SET_REGISTER( "mtspr 153,%0", val )
-#define GET_CMPG() GET_REGISTER( "mfspr %0,154" )
-#define SET_CMPG(val) SET_REGISTER( "mtspr 154,%0", val )
-#define GET_CMPH() GET_REGISTER( "mfspr %0,155" )
-#define SET_CMPH(val) SET_REGISTER( "mtspr 155,%0", val )
-#define GET_LCTRL1() GET_REGISTER( "mfspr %0,156" )
-#define SET_LCTRL1(val) SET_REGISTER( "mtspr 156,%0", val )
-#define GET_LCTRL2() GET_REGISTER( "mfspr %0,157" )
-#define SET_LCTRL2(val) SET_REGISTER( "mtspr 157,%0", val )
-#define GET_ICTRL() GET_REGISTER( "mfspr %0,158" )
-#define SET_ICTRL(val) SET_REGISTER( "mtspr 158,%0", val )
-#define GET_BAR() GET_REGISTER( "mfspr %0,159" )
-#define SET_BAR(val) SET_REGISTER( "mtspr 159,%0", val )
-#define GET_USPRG0() GET_REGISTER( "mfspr %0,256" )
-#define SET_USPRG0(val) SET_REGISTER( "mtspr 256,%0", val )
-#define GET_SPRG4_RO() GET_REGISTER( "mfspr %0,260" )
-#define SET_SPRG4_RO(val) SET_REGISTER( "mtspr 260,%0", val )
-#define GET_SPRG5_RO() GET_REGISTER( "mfspr %0,261" )
-#define SET_SPRG5_RO(val) SET_REGISTER( "mtspr 261,%0", val )
-#define GET_SPRG6_RO() GET_REGISTER( "mfspr %0,262" )
-#define SET_SPRG6_RO(val) SET_REGISTER( "mtspr 262,%0", val )
-#define GET_SPRG7_RO() GET_REGISTER( "mfspr %0,263" )
-#define SET_SPRG7_RO(val) SET_REGISTER( "mtspr 263,%0", val )
-#define GET_SPRG0() GET_REGISTER( "mfspr %0,272" )
-#define SET_SPRG0(val) SET_REGISTER( "mtspr 272,%0", val )
-#define GET_SPRG1() GET_REGISTER( "mfspr %0,273" )
-#define SET_SPRG1(val) SET_REGISTER( "mtspr 273,%0", val )
-#define GET_SPRG2() GET_REGISTER( "mfspr %0,274" )
-#define SET_SPRG2(val) SET_REGISTER( "mtspr 274,%0", val )
-#define GET_SPRG3() GET_REGISTER( "mfspr %0,275" )
-#define SET_SPRG3(val) SET_REGISTER( "mtspr 275,%0", val )
-#define GET_SPRG4() GET_REGISTER( "mfspr %0,276" )
-#define SET_SPRG4(val) SET_REGISTER( "mtspr 276,%0", val )
-#define GET_SPRG5() GET_REGISTER( "mfspr %0,277" )
-#define SET_SPRG5(val) SET_REGISTER( "mtspr 277,%0", val )
-#define GET_SPRG6() GET_REGISTER( "mfspr %0,278" )
-#define SET_SPRG6(val) SET_REGISTER( "mtspr 278,%0", val )
-#define GET_SPRG7() GET_REGISTER( "mfspr %0,279" )
-#define SET_SPRG7(val) SET_REGISTER( "mtspr 279,%0", val )
-#define GET_EAR() GET_REGISTER( "mfspr %0,282" )
-#define SET_EAR(val) SET_REGISTER( "mtspr 282,%0", val )
-#define GET_TBL() GET_REGISTER( "mfspr %0,284" )
-#define SET_TBL(val) SET_REGISTER( "mtspr 284,%0", val )
-#define GET_TBU() GET_REGISTER( "mfspr %0,285" )
-#define SET_TBU(val) SET_REGISTER( "mtspr 285,%0", val )
-#define GET_PVR() GET_REGISTER( "mfspr %0,287" )
-#define SET_PVR(val) SET_REGISTER( "mtspr 287,%0", val )
-#define GET_IC_CST() GET_REGISTER( "mfspr %0,560" )
-#define SET_IC_CST(val) SET_REGISTER( "mtspr 560,%0", val )
-#define GET_IC_ADR() GET_REGISTER( "mfspr %0,561" )
-#define SET_IC_ADR(val) SET_REGISTER( "mtspr 561,%0", val )
-#define GET_IC_DAT() GET_REGISTER( "mfspr %0,562" )
-#define SET_IC_DAT(val) SET_REGISTER( "mtspr 562,%0", val )
-#define GET_DC_CST() GET_REGISTER( "mfspr %0,568" )
-#define SET_DC_CST(val) SET_REGISTER( "mtspr 568,%0", val )
-#define GET_DC_ADR() GET_REGISTER( "mfspr %0,569" )
-#define SET_DC_ADR(val) SET_REGISTER( "mtspr 569,%0", val )
-#define GET_DC_DAT() GET_REGISTER( "mfspr %0,570" )
-#define SET_DC_DAT(val) SET_REGISTER( "mtspr 570,%0", val )
-#define GET_DPDR() GET_REGISTER( "mfspr %0,630" )
-#define SET_DPDR(val) SET_REGISTER( "mtspr 630,%0", val )
-#define GET_IMMR() GET_REGISTER( "mfspr %0,638" )
-#define SET_IMMR(val) SET_REGISTER( "mtspr 638,%0", val )
-#define GET_MI_CTR() GET_REGISTER( "mfspr %0,784" )
-#define SET_MI_CTR(val) SET_REGISTER( "mtspr 784,%0", val )
-#define GET_MI_AP() GET_REGISTER( "mfspr %0,786" )
-#define SET_MI_AP(val) SET_REGISTER( "mtspr 786,%0", val )
-#define GET_MI_EPN() GET_REGISTER( "mfspr %0,787" )
-#define SET_MI_EPN(val) SET_REGISTER( "mtspr 787,%0", val )
-#define GET_MI_TWC() GET_REGISTER( "mfspr %0,789" )
-#define SET_MI_TWC(val) SET_REGISTER( "mtspr 789,%0", val )
-#define GET_MI_RPN() GET_REGISTER( "mfspr %0,790" )
-#define SET_MI_RPN(val) SET_REGISTER( "mtspr 790,%0", val )
-#define GET_MD_CTR() GET_REGISTER( "mfspr %0,792" )
-#define SET_MD_CTR(val) SET_REGISTER( "mtspr 792,%0", val )
-#define GET_M_CASID() GET_REGISTER( "mfspr %0,793" )
-#define SET_M_CASID(val) SET_REGISTER( "mtspr 793,%0", val )
-#define GET_MD_AP() GET_REGISTER( "mfspr %0,794" )
-#define SET_MD_AP(val) SET_REGISTER( "mtspr ,794%0", val )
-#define GET_MD_EPN() GET_REGISTER( "mfspr %0,795" )
-#define SET_MD_EPN(val) SET_REGISTER( "mtspr 795,%0", val )
-#define GET_M_TWB() GET_REGISTER( "mfspr %0,796" )
-#define SET_M_TWB(val) SET_REGISTER( "mtspr 796,%0", val )
-#define GET_MD_TWC() GET_REGISTER( "mfspr %0,797" )
-#define SET_MD_TWC(val) SET_REGISTER( "mtspr 797,%0", val )
-#define GET_MD_RPN() GET_REGISTER( "mfspr %0,798" )
-#define SET_MD_RPN(val) SET_REGISTER( "mtspr 798,%0", val )
-#define GET_M_TW() GET_REGISTER( "mfspr %0,799" )
-#define SET_M_TW(val) SET_REGISTER( "mtspr 799,%0", val )
-#define GET_MI_DBCAM() GET_REGISTER( "mfspr %0,816" )
-#define SET_MI_DBCAM(val) SET_REGISTER( "mtspr 816,%0", val )
-#define GET_MI_DBRAM0() GET_REGISTER( "mfspr %0,817" )
-#define SET_MI_DBRAM0(val) SET_REGISTER( "mtspr 817,%0", val )
-#define GET_MI_DBRAM1() GET_REGISTER( "mfspr %0,818" )
-#define SET_MI_DBRAM1(val) SET_REGISTER( "mtspr 818,%0", val )
-#define GET_MD_DBCAM() GET_REGISTER( "mfspr %0,824" )
-#define SET_MD_DBCA(val) SET_REGISTER( "mtspr 824,%0", val )
-#define GET_MD_DBRAM0() GET_REGISTER( "mfspr %0,825" )
-#define SET_MD_DBRAM0(val) SET_REGISTER( "mtspr 825,%0", val )
-#define GET_MD_DBRAM1() GET_REGISTER( "mfspr %0,826" )
-#define SET_MD_DBRAM1(val) SET_REGISTER( "mtspr 826,%0", val )
-#define GET_ZPR() GET_REGISTER( "mfspr %0,944" )
-#define SET_ZPR(val) SET_REGISTER( "mtspr 944,%0", val )
-#define GET_PID() GET_REGISTER( "mfspr %0,945" )
-#define SET_PID(val) SET_REGISTER( "mtspr 945,%0", val )
-#define GET_CCR0() GET_REGISTER( "mfspr %0,947" )
-#define SET_CCR0(val) SET_REGISTER( "mtspr 947,%0", val )
-#define GET_IAC3() GET_REGISTER( "mfspr %0,948" )
-#define SET_IAC3(val) SET_REGISTER( "mtspr 948,%0", val )
-#define GET_IAC4() GET_REGISTER( "mfspr %0,949" )
-#define SET_IAC4(val) SET_REGISTER( "mtspr 949,%0", val )
-#define GET_DVC1() GET_REGISTER( "mfspr %0,950" )
-#define SET_DVC1(val) SET_REGISTER( "mtspr 950,%0", val )
-#define GET_DVC2() GET_REGISTER( "mfspr %0,951" )
-#define SET_DVC2(val) SET_REGISTER( "mtspr 951,%0", val )
-#define GET_SGR() GET_REGISTER( "mfspr %0,953" )
-#define SET_SGR(val) SET_REGISTER( "mtspr 953,%0", val )
-#define GET_DCWR() GET_REGISTER( "mfspr %0,954" )
-#define SET_DCWR(val) SET_REGISTER( "mtspr 954,%0", val )
-#define GET_SLER() GET_REGISTER( "mfspr %0,955" )
-#define SET_SLER(val) SET_REGISTER( "mtspr 955,%0", val )
-#define GET_SU0R() GET_REGISTER( "mfspr %0,956" )
-#define SET_SU0R(val) SET_REGISTER( "mtspr 956,%0", val )
-#define GET_DBCR1() GET_REGISTER( "mfspr %0,957" )
-#define SET_DBCR1(val) SET_REGISTER( "mtspr 957,%0", val )
-#define GET_ICDBDR() GET_REGISTER( "mfspr %0,979" )
-#define SET_ICDBDR(val) SET_REGISTER( "mtspr 979,%0", val )
-#define GET_ESR() GET_REGISTER( "mfspr %0,980" )
-#define SET_ESR(val) SET_REGISTER( "mtspr 980,%0", val )
-#define GET_DEAR() GET_REGISTER( "mfspr %0,981" )
-#define SET_DEAR(val) SET_REGISTER( "mtspr 981,%0", val )
-#define GET_EVPR() GET_REGISTER( "mfspr %0,982" )
-#define SET_EVPR(val) SET_REGISTER( "mtspr 982,%0", val )
-#define GET_TSR() GET_REGISTER( "mfspr %0,984" )
-#define SET_TSR(val) SET_REGISTER( "mtspr 984,%0", val )
-#define GET_TCR() GET_REGISTER( "mfspr %0,986" )
-#define SET_TCR(val) SET_REGISTER( "mtspr 986,%0", val )
-#define GET_PIT() GET_REGISTER( "mfspr %0,987" )
-#define SET_PIT(val) SET_REGISTER( "mtspr 987,%0", val )
-#define GET_SRR2() GET_REGISTER( "mfspr %0,990" )
-#define SET_SRR2(val) SET_REGISTER( "mtspr 990,%0", val )
-#define GET_SRR3() GET_REGISTER( "mfspr %0,991" )
-#define SET_SRR3(val) SET_REGISTER( "mtspr 991,%0", val )
-#define GET_DBSR() GET_REGISTER( "mfspr %0,1008" )
-#define SET_DBSR(val) SET_REGISTER( "mtspr 1008,%0", val )
-#define GET_DBCR0() GET_REGISTER( "mfspr %0,1010" )
-#define SET_DBCR0(val) SET_REGISTER( "mtspr 1010,%0", val )
-#define GET_IABR() GET_REGISTER( "mfspr %0,1010" )
-#define SET_IABR(val) SET_REGISTER( "mtspr 1010,%0", val )
-#define GET_IAC1() GET_REGISTER( "mfspr %0,1012" )
-#define SET_IAC1(val) SET_REGISTER( "mtspr 1012,%0", val )
-#define GET_IAC2() GET_REGISTER( "mfspr %0,1013" )
-#define SET_IAC2(val) SET_REGISTER( "mtspr 1013,%0", val )
-#define GET_DAC1() GET_REGISTER( "mfspr %0,1014" )
-#define SET_DAC1(val) SET_REGISTER( "mtspr 1014,%0", val )
-#define GET_DAC2() GET_REGISTER( "mfspr %0,1015" )
-#define SET_DAC2(val) SET_REGISTER( "mtspr 1015,%0", val )
-#define GET_DCCR() GET_REGISTER( "mfspr %0,1018" )
-#define SET_DCCR(val) SET_REGISTER( "mtspr 1018,%0", val )
-#define GET_ICCR() GET_REGISTER( "mfspr %0,1019" )
-#define SET_ICCR(val) SET_REGISTER( "mtspr 1019,%0", val )
-
-#endif /* _REGS_H */
-
-
-/*
- * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are freely
- * permitted provided that the above copyright notice and this
- * paragraph and the following disclaimer are duplicated in all
- * such forms.
- *
- * This software is provided "AS IS" and without any express or
- * implied warranties, including, without limitation, the implied
- * warranties of merchantability and fitness for a particular
- * purpose.
- */
diff --git a/include/bedbug/tables.h b/include/bedbug/tables.h
deleted file mode 100644
index 66cf8eaea3..0000000000
--- a/include/bedbug/tables.h
+++ /dev/null
@@ -1,601 +0,0 @@
-/* $Id$ */
-
-#ifndef TABLES_H
-#define TABLES_H
-
-/* This is only included by common/bedbug.c, and depends on the following
- * files to already be included
- * common.h
- * bedbug/bedbug.h
- * bedbug/ppc.h
- * bedbug/regs.h
- */
-
-struct operand operands[] = {
- /*Field Name Bits Shift Hint Position */
- /*----- ------ ----- ----- ---- ------------ */
- { O_AA, "O_AA", 1, 1, OH_SILENT }, /* 30 */
- { O_BD, "O_BD", 14, 2, OH_ADDR }, /* 16-29 */
- { O_BI, "O_BI", 5, 16, 0 }, /* 11-15 */
- { O_BO, "O_BO", 5, 21, 0 }, /* 6-10 */
- { O_crbD, "O_crbD", 5, 21, 0 }, /* 6-10 */
- { O_crbA, "O_crbA", 5, 16, 0 }, /* 11-15 */
- { O_crbB, "O_crbB", 5, 11, 0 }, /* 16-20 */
- { O_CRM, "O_CRM", 8, 12, 0 }, /* 12-19 */
- { O_d, "O_d", 15, 0, OH_OFFSET }, /* 16-31 */
- { O_frC, "O_frC", 5, 6, 0 }, /* 21-25 */
- { O_frD, "O_frD", 5, 21, 0 }, /* 6-10 */
- { O_frS, "O_frS", 5, 21, 0 }, /* 6-10 */
- { O_IMM, "O_IMM", 4, 12, 0 }, /* 16-19 */
- { O_LI, "O_LI", 24, 2, OH_ADDR }, /* 6-29 */
- { O_LK, "O_LK", 1, 0, OH_SILENT }, /* 31 */
- { O_MB, "O_MB", 5, 6, 0 }, /* 21-25 */
- { O_ME, "O_ME", 5, 1, 0 }, /* 26-30 */
- { O_NB, "O_NB", 5, 11, 0 }, /* 16-20 */
- { O_OE, "O_OE", 1, 10, OH_SILENT }, /* 21 */
- { O_rA, "O_rA", 5, 16, OH_REG }, /* 11-15 */
- { O_rB, "O_rB", 5, 11, OH_REG }, /* 16-20 */
- { O_Rc, "O_Rc", 1, 0, OH_SILENT }, /* 31 */
- { O_rD, "O_rD", 5, 21, OH_REG }, /* 6-10 */
- { O_rS, "O_rS", 5, 21, OH_REG }, /* 6-10 */
- { O_SH, "O_SH", 5, 11, 0 }, /* 16-20 */
- { O_SIMM, "O_SIMM", 16, 0, 0 }, /* 16-31 */
- { O_SR, "O_SR", 4, 16, 0 }, /* 12-15 */
- { O_TO, "O_TO", 5, 21, 0 }, /* 6-10 */
- { O_UIMM, "O_UIMM", 16, 0, 0 }, /* 16-31 */
- { O_crfD, "O_crfD", 3, 23, 0 }, /* 6- 8 */
- { O_crfS, "O_crfS", 3, 18, 0 }, /* 11-13 */
- { O_L, "O_L", 1, 21, 0 }, /* 10 */
- { O_spr, "O_spr", 10, 11, OH_SPR }, /* 11-20 */
- { O_tbr, "O_tbr", 10, 11, OH_TBR }, /* 11-20 */
- { O_cr2, "O_cr2", 0, 0, OH_LITERAL }, /* "cr2" */
-};
-
-const unsigned int n_operands = sizeof(operands) / sizeof(operands[0]);
-
-/* A note about the fields array in the opcodes structure:
- The operands are listed in the order they appear in the output.
-
- This table is arranged in numeric order of the opcode. Note that some
- opcodes have defined bits in odd places so not all forms of a command
- will be in the same place. This is done so that a binary search can be
- done to find the opcodes. Note that table D.2 in the MPC860 User's
- Manual "Instructions Sorted by Opcode" does not account for these
- bit locations */
-
-struct opcode opcodes[] = {
- { D_OPCODE(3), D_MASK, {O_TO, O_rA, O_SIMM, 0},
- 0, "twi", 0 },
- { D_OPCODE(7), D_MASK, {O_rD, O_rA, O_SIMM, 0},
- 0, "mulli", 0 },
- { D_OPCODE(8), D_MASK, {O_rD, O_rA, O_SIMM, 0},
- 0, "subfic", 0 },
- { D_OPCODE(10), D_MASK, {O_crfD, O_L, O_rA, O_UIMM, 0},
- 0, "cmpli", 0 },
- { D_OPCODE(11), D_MASK, {O_crfD, O_L, O_rA, O_SIMM, 0},
- 0, "cmpi", 0 },
- { D_OPCODE(12), D_MASK, {O_rD, O_rA, O_SIMM, 0},
- 0, "addic", 0 },
- { D_OPCODE(13), D_MASK, {O_rD, O_rA, O_SIMM, 0},
- 0, "addic.", 0 },
- { D_OPCODE(14), D_MASK, {O_rD, O_rA, O_SIMM, 0},
- 0, "addi", H_RA0_IS_0 },
- { D_OPCODE(15), D_MASK, {O_rD, O_rA, O_SIMM, 0},
- 0, "addis", H_RA0_IS_0|H_IMM_HIGH },
- { B_OPCODE(16,0,0), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
- handle_bc, "bc", H_RELATIVE },
- { B_OPCODE(16,0,1), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
- 0, "bcl", H_RELATIVE },
- { B_OPCODE(16,1,0), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
- 0, "bca", 0 },
- { B_OPCODE(16,1,1), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
- 0, "bcla", 0 },
- { SC_OPCODE(17), SC_MASK, {0},
- 0, "sc", 0 },
- { I_OPCODE(18,0,0), I_MASK, {O_LI, O_AA, O_LK, 0},
- 0, "b", H_RELATIVE },
- { I_OPCODE(18,0,1), I_MASK, {O_LI, O_AA, O_LK, 0},
- 0, "bl", H_RELATIVE },
- { I_OPCODE(18,1,0), I_MASK, {O_LI, O_AA, O_LK, 0},
- 0, "ba", 0 },
- { I_OPCODE(18,1,1), I_MASK, {O_LI, O_AA, O_LK, 0},
- 0, "bla", 0 },
- { XL_OPCODE(19,0,0), XL_MASK, {O_crfD, O_crfS},
- 0, "mcrf", 0 },
- { XL_OPCODE(19,16,0), XL_MASK, {O_BO, O_BI, O_LK, 0},
- 0, "bclr", 0 },
- { XL_OPCODE(19,16,1), XL_MASK, {O_BO, O_BI, O_LK, 0},
- 0, "bclrl", 0 },
- { XL_OPCODE(19,33,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
- 0, "crnor", 0 },
- { XL_OPCODE(19,50,0), XL_MASK, {0},
- 0, "rfi", 0 },
- { XL_OPCODE(19,129,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
- 0, "crandc", 0 },
- { XL_OPCODE(19,150,0), XL_MASK, {0},
- 0, "isync", 0 },
- { XL_OPCODE(19,193,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
- 0, "crxor", 0 },
- { XL_OPCODE(19,225,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
- 0, "crnand", 0 },
- { XL_OPCODE(19,257,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
- 0, "crand", 0 },
- { XL_OPCODE(19,289,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
- 0, "creqv", 0 },
- { XL_OPCODE(19,417,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
- 0, "crorc", 0 },
- { XL_OPCODE(19,449,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
- 0, "cror", 0 },
- { XL_OPCODE(19,528,0), XL_MASK, {O_BO, O_BI, O_LK, 0},
- 0, "bcctr", 0 },
- { XL_OPCODE(19,528,1), XL_MASK, {O_BO, O_BI, O_LK, 0},
- 0, "bcctrl", 0 },
- { M_OPCODE(20,0), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
- 0, "rlwimi", 0 },
- { M_OPCODE(20,1), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
- 0, "rlwimi.", 0 },
- { M_OPCODE(21,0), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
- 0, "rlwinm", 0 },
- { M_OPCODE(21,1), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
- 0, "rlwinm.", 0 },
- { M_OPCODE(23,0), M_MASK, {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0},
- 0, "rlwnm", 0 },
- { M_OPCODE(23,1), M_MASK, {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0},
- 0, "rlwnm.", 0 },
- { D_OPCODE(24), D_MASK, {O_rA, O_rS, O_UIMM, 0},
- 0, "ori", 0 },
- { D_OPCODE(25), D_MASK, {O_rA, O_rS, O_UIMM, 0},
- 0, "oris", H_IMM_HIGH },
- { D_OPCODE(26), D_MASK, {O_rA, O_rS, O_UIMM, 0},
- 0, "xori", 0 },
- { D_OPCODE(27), D_MASK, {O_rA, O_rS, O_UIMM, 0},
- 0, "xoris", H_IMM_HIGH },
- { D_OPCODE(28), D_MASK, {O_rA, O_rS, O_UIMM, 0},
- 0, "andi.", 0 },
- { D_OPCODE(29), D_MASK, {O_rA, O_rS, O_UIMM, 0},
- 0, "andis.", H_IMM_HIGH },
- { X_OPCODE(31,0,0), X_MASK, {O_crfD, O_L, O_rA, O_rB, 0},
- 0, "cmp", 0 },
- { X_OPCODE(31,4,0), X_MASK, {O_TO, O_rA, O_rB, 0},
- 0, "tw", 0 },
- { XO_OPCODE(31,8,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "subfc", 0 },
- { XO_OPCODE(31,8,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "subfc.", 0 },
- { XO_OPCODE(31,10,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "addc", 0 },
- { XO_OPCODE(31,10,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "addc.", 0 },
- { XO_OPCODE(31,11,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0},
- 0, "mulhwu", 0 },
- { XO_OPCODE(31,11,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0},
- 0, "mulhwu.", 0 },
- { X_OPCODE(31,19,0), X_MASK, {O_rD, 0},
- 0, "mfcr", 0 },
- { X_OPCODE(31,20,0), X_MASK, {O_rD, O_rA, O_rB, 0},
- 0, "lwarx", H_RA0_IS_0 },
- { X_OPCODE(31,23,0), X_MASK, {O_rD, O_rA, O_rB, 0},
- 0, "lwzx", H_RA0_IS_0 },
- { X_OPCODE(31,24,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "slw", 0 },
- { X_OPCODE(31,24,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "slw.", 0 },
- { X_OPCODE(31,26,0), X_MASK, {O_rA, O_rS, O_Rc, 0 },
- 0, "cntlzw", 0 },
- { X_OPCODE(31,26,1), X_MASK, {O_rA, O_rS, O_Rc, 0},
- 0, "cntlzw.", 0 },
- { X_OPCODE(31,28,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "and", 0 },
- { X_OPCODE(31,28,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "and.", 0 },
- { X_OPCODE(31,32,0), X_MASK, {O_crfD, O_L, O_rA, O_rB, 0},
- 0, "cmpl", 0 },
- { XO_OPCODE(31,40,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "subf", 0 },
- { XO_OPCODE(31,40,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "subf.", 0 },
- { X_OPCODE(31,54,0), X_MASK, {O_rA, O_rB, 0},
- 0, "dcbst", H_RA0_IS_0 },
- { X_OPCODE(31,55,0), X_MASK, {O_rD, O_rA, O_rB, 0},
- 0, "lwzux", 0 },
- { X_OPCODE(31,60,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "andc", 0 },
- { X_OPCODE(31,60,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "andc.", 0 },
- { XO_OPCODE(31,75,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0},
- 0, "mulhw", 0 },
- { XO_OPCODE(31,75,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0},
- 0, "mulhw.", 0 },
- { X_OPCODE(31,83,0), X_MASK, {O_rD, 0},
- 0, "mfmsr", 0 },
- { X_OPCODE(31,86,0), X_MASK, {O_rA, O_rB, 0},
- 0, "dcbf", H_RA0_IS_0 },
- { X_OPCODE(31,87,0), X_MASK, {O_rD, O_rA, O_rB, 0},
- 0, "lbzx", H_RA0_IS_0 },
- { XO_OPCODE(31,104,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "neg", 0 },
- { XO_OPCODE(31,104,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "neg.", 0 },
- { X_OPCODE(31,119,0), X_MASK, {O_rD, O_rA, O_rB, 0},
- 0, "lbzux", 0 },
- { X_OPCODE(31,124,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "nor", 0 },
- { X_OPCODE(31,124,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "nor.", 0 },
- { XO_OPCODE(31,136,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "subfe", 0 },
- { XO_OPCODE(31,136,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "subfe.", 0 },
- { XO_OPCODE(31,138,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "adde", 0 },
- { XO_OPCODE(31,138,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "adde.", 0 },
- { XFX_OPCODE(31,144,0), XFX_MASK, {O_CRM, O_rS, 0},
- 0, "mtcrf", 0 },
- { X_OPCODE(31,146,0), X_MASK, {O_rS, 0},
- 0, "mtmsr", 0 },
- { X_OPCODE(31,150,1), X_MASK, {O_rS, O_rA, O_rB, 0},
- 0, "stwcx.", 0 },
- { X_OPCODE(31,151,0), X_MASK, {O_rS, O_rA, O_rB, 0},
- 0, "stwx", 0 },
- { X_OPCODE(31,183,0), X_MASK, {O_rS, O_rA, O_rB, 0},
- 0, "stwux", 0 },
- { XO_OPCODE(31,200,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "subfze", 0 },
- { XO_OPCODE(31,200,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "subfze.", 0 },
- { XO_OPCODE(31,202,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "addze", 0 },
- { XO_OPCODE(31,202,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "addze.", 0 },
- { X_OPCODE(31,210,0), X_MASK, {O_SR, O_rS, 0},
- 0, "mtsr", 0 },
- { X_OPCODE(31,215,0), X_MASK, {O_rS, O_rA, O_rB, 0},
- 0, "stbx", H_RA0_IS_0 },
- { XO_OPCODE(31,232,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "subfme", 0 },
- { XO_OPCODE(31,232,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "subfme.", 0 },
- { XO_OPCODE(31,234,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "addme", 0 },
- { XO_OPCODE(31,234,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "addme.", 0 },
- { XO_OPCODE(31,235,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "mullw", 0 },
- { XO_OPCODE(31,235,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "mullw.", 0 },
- { X_OPCODE(31,242,0), X_MASK, {O_rS, O_rB, 0},
- 0, "mtsrin", 0 },
- { X_OPCODE(31,246,0), X_MASK, {O_rA, O_rB, 0},
- 0, "dcbtst", H_RA0_IS_0 },
- { X_OPCODE(31,247,0), X_MASK, {O_rS, O_rA, O_rB, 0},
- 0, "stbux", 0 },
- { XO_OPCODE(31,266,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "add", 0 },
- { XO_OPCODE(31,266,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "add.", 0 },
- { X_OPCODE(31,278,0), X_MASK, {O_rA, O_rB, 0},
- 0, "dcbt", H_RA0_IS_0 },
- { X_OPCODE(31,279,0), X_MASK, {O_rD, O_rA, O_rB, 0},
- 0, "lhzx", H_RA0_IS_0 },
- { X_OPCODE(31,284,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "eqv", 0 },
- { X_OPCODE(31,284,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "eqv.", 0 },
- { X_OPCODE(31,306,0), X_MASK, {O_rB, 0},
- 0, "tlbie", 0 },
- { X_OPCODE(31,310,0), X_MASK, {O_rD, O_rA, O_rB, 0},
- 0, "eciwx", H_RA0_IS_0 },
- { X_OPCODE(31,311,0), X_MASK, {O_rD, O_rA, O_rB, 0},
- 0, "lhzux", 0 },
- { X_OPCODE(31,316,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "xor", 0 },
- { X_OPCODE(31,316,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "xor.", 0 },
- { XFX_OPCODE(31,339,0), XFX_MASK, {O_rD, O_spr, 0},
- 0, "mfspr", 0 },
- { X_OPCODE(31,343,0), X_MASK, {O_rD, O_rA, O_rB, 0},
- 0, "lhax", H_RA0_IS_0 },
- { X_OPCODE(31,370,0), X_MASK, {0},
- 0, "tlbia", 0 },
- { XFX_OPCODE(31,371,0), XFX_MASK, {O_rD, O_tbr, 0},
- 0, "mftb", 0 },
- { X_OPCODE(31,375,0), X_MASK, {O_rD, O_rA, O_rB, 0},
- 0, "lhaux", 0 },
- { X_OPCODE(31,407,0), X_MASK, {O_rS, O_rA, O_rB, 0},
- 0, "sthx", H_RA0_IS_0 },
- { X_OPCODE(31,412,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "orc", 0 },
- { X_OPCODE(31,412,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "orc.", 0 },
- { X_OPCODE(31,438,0), X_MASK, {O_rS, O_rA, O_rB, 0},
- 0, "ecowx", H_RA0_IS_0 },
- { X_OPCODE(31,439,0), X_MASK, {O_rS, O_rA, O_rB, 0},
- 0, "sthux", 0 },
- { X_OPCODE(31,444,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "or", 0 },
- { X_OPCODE(31,444,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "or.", 0 },
- { XO_OPCODE(31,459,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "divwu", 0 },
- { XO_OPCODE(31,459,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "divwu.", 0 },
- { XFX_OPCODE(31,467,0), XFX_MASK, {O_spr, O_rS, 0},
- 0, "mtspr", 0 },
- { X_OPCODE(31,470,0), X_MASK, {O_rA, O_rB, 0},
- 0, "dcbi", H_RA0_IS_0 },
- { X_OPCODE(31,476,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "nand", 0 },
- { X_OPCODE(31,476,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc,0},
- 0, "nand.", 0 },
- { XO_OPCODE(31,491,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "divw", 0 },
- { XO_OPCODE(31,491,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "divw.", 0 },
- { X_OPCODE(31,512,0), X_MASK, {O_crfD, 0},
- 0, "mcrxr", 0 },
- { XO_OPCODE(31,8,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "subfco", 0 },
- { XO_OPCODE(31,8,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "subfco.", 0 },
- { XO_OPCODE(31,10,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "addco", 0 },
- { XO_OPCODE(31,10,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "addco.", 0 },
- { X_OPCODE(31,533,0), X_MASK, {O_rD, O_rA, O_rB, 0},
- 0, "lswx", H_RA0_IS_0 },
- { X_OPCODE(31,534,0), X_MASK, {O_rD, O_rA, O_rB, 0},
- 0, "lwbrx", H_RA0_IS_0 },
- { X_OPCODE(31,536,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "srw", 0 },
- { X_OPCODE(31,536,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "srw.", 0 },
- { XO_OPCODE(31,40,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "subfo", 0 },
- { XO_OPCODE(31,40,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "subfo.", 0 },
- { X_OPCODE(31,566,0), X_MASK, {0},
- 0, "tlbsync", 0 },
- { X_OPCODE(31,595,0), X_MASK, {O_rD, O_SR, 0},
- 0, "mfsr", 0 },
- { X_OPCODE(31,597,0), X_MASK, {O_rD, O_rA, O_NB, 0},
- 0, "lswi", H_RA0_IS_0 },
- { X_OPCODE(31,598,0), X_MASK, {0},
- 0, "sync", 0 },
- { XO_OPCODE(31,104,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "nego", 0 },
- { XO_OPCODE(31,104,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "nego.", 0 },
- { XO_OPCODE(31,136,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "subfeo", 0 },
- { XO_OPCODE(31,136,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "subfeo.", 0 },
- { XO_OPCODE(31,138,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "addeo", 0 },
- { XO_OPCODE(31,138,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "addeo.", 0 },
- { X_OPCODE(31,659,0), X_MASK, {O_rD, O_rB, 0},
- 0, "mfsrin", 0 },
- { X_OPCODE(31,661,0), X_MASK, {O_rS, O_rA, O_rB, 0},
- 0, "stswx", H_RA0_IS_0 },
- { X_OPCODE(31,662,0), X_MASK, {O_rS, O_rA, O_rB, 0},
- 0, "stwbrx", H_RA0_IS_0 },
- { XO_OPCODE(31,200,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "subfzeo", 0 },
- { XO_OPCODE(31,200,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "subfzeo.", 0 },
- { XO_OPCODE(31,202,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "addzeo", 0 },
- { XO_OPCODE(31,202,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "addzeo.", 0 },
- { X_OPCODE(31,725,0), X_MASK, {O_rS, O_rA, O_NB, 0},
- 0, "stswi", H_RA0_IS_0 },
- { XO_OPCODE(31,232,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "subfmeo", 0 },
- { XO_OPCODE(31,232,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "subfmeo.", 0 },
- { XO_OPCODE(31,234,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "addmeo", 0 },
- { XO_OPCODE(31,234,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
- 0, "addmeo.", 0 },
- { XO_OPCODE(31,235,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "mullwo", 0 },
- { XO_OPCODE(31,235,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "mullwo.", 0 },
- { XO_OPCODE(31,266,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "addo", 0 },
- { XO_OPCODE(31,266,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "addo.", 0 },
- { X_OPCODE(31,790,0), X_MASK, {O_rD, O_rA, O_rB, 0},
- 0, "lhbrx", H_RA0_IS_0 },
- { X_OPCODE(31,792,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "sraw", 0 },
- { X_OPCODE(31,792,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
- 0, "sraw.", 0 },
- { X_OPCODE(31,824,0), X_MASK, {O_rA, O_rS, O_SH, O_Rc, 0},
- 0, "srawi", 0 },
- { X_OPCODE(31,824,1), X_MASK, {O_rA, O_rS, O_SH, O_Rc, 0},
- 0, "srawi.", 0 },
- { X_OPCODE(31,854,0), X_MASK, {0},
- 0, "eieio", 0 },
- { X_OPCODE(31,918,0), X_MASK, {O_rS, O_rA, O_rB, 0},
- 0, "sthbrx", H_RA0_IS_0 },
- { X_OPCODE(31,922,0), X_MASK, {O_rA, O_rS, O_Rc, 0},
- 0, "extsh", 0 },
- { X_OPCODE(31,922,1), X_MASK, {O_rA, O_rS, O_Rc, 0},
- 0, "extsh.", 0 },
- { X_OPCODE(31,954,0), X_MASK, {O_rA, O_rS, O_Rc, 0},
- 0, "extsb", 0 },
- { X_OPCODE(31,954,1), X_MASK, {O_rA, O_rS, O_Rc, 0},
- 0, "extsb.", 0 },
- { XO_OPCODE(31,459,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "divwuo", 0 },
- { XO_OPCODE(31,459,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "divwuo.", 0 },
- { X_OPCODE(31,978,0), X_MASK, {O_rB, 0},
- 0, "tlbld", 0 },
- { X_OPCODE(31,982,0), X_MASK, {O_rA, O_rB, 0},
- 0, "icbi", H_RA0_IS_0 },
- { XO_OPCODE(31,491,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "divwo", 0 },
- { XO_OPCODE(31,491,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
- 0, "divwo.", 0 },
- { X_OPCODE(31,1010,0), X_MASK, {O_rB, 0},
- 0, "tlbli", 0 },
- { X_OPCODE(31,1014,0), X_MASK, {O_rA, O_rB, 0},
- 0, "dcbz", H_RA0_IS_0 },
- { D_OPCODE(32), D_MASK, {O_rD, O_d, O_rA, 0},
- 0, "lwz", H_RA0_IS_0 },
- { D_OPCODE(33), D_MASK, {O_rD, O_d, O_rA, 0},
- 0, "lwzu", 0 },
- { D_OPCODE(34), D_MASK, {O_rD, O_d, O_rA, 0},
- 0, "lbz", H_RA0_IS_0 },
- { D_OPCODE(35), D_MASK, {O_rD, O_d, O_rA, 0},
- 0, "lbzu", 0 },
- { D_OPCODE(36), D_MASK, {O_rS, O_d, O_rA, 0},
- 0, "stw", H_RA0_IS_0 },
- { D_OPCODE(37), D_MASK, {O_rS, O_d, O_rA, 0},
- 0, "stwu", 0 },
- { D_OPCODE(38), D_MASK, {O_rS, O_d, O_rA, 0},
- 0, "stb", H_RA0_IS_0 },
- { D_OPCODE(39), D_MASK, {O_rS, O_d, O_rA, 0},
- 0, "stbu", 0 },
- { D_OPCODE(40), D_MASK, {O_rD, O_d, O_rA, 0},
- 0, "lhz", H_RA0_IS_0 },
- { D_OPCODE(41), D_MASK, {O_rD, O_d, O_rA, 0},
- 0, "lhzu", 0 },
- { D_OPCODE(42), D_MASK, {O_rD, O_d, O_rA, 0},
- 0, "lha", H_RA0_IS_0 },
- { D_OPCODE(43), D_MASK, {O_rD, O_d, O_rA, 0},
- 0, "lhau", 0 },
- { D_OPCODE(44), D_MASK, {O_rS, O_d, O_rA, 0},
- 0, "sth", H_RA0_IS_0 },
- { D_OPCODE(45), D_MASK, {O_rS, O_d, O_rA, 0},
- 0, "sthu", 0 },
- { D_OPCODE(46), D_MASK, {O_rD, O_d, O_rA, 0},
- 0, "lmw", H_RA0_IS_0 },
- { D_OPCODE(47), D_MASK, {O_rS, O_d, O_rA, 0},
- 0, "stmw", H_RA0_IS_0 },
-};
-
-const unsigned int n_opcodes = sizeof(opcodes) / sizeof(opcodes[0]);
-
-struct spr_info spr_map[] = {
- { SPR_XER, "XER" },
- { SPR_LR, "LR" },
- { SPR_CTR, "CTR" },
- { SPR_DSISR, "DSISR" },
- { SPR_DAR, "DAR" },
- { SPR_DEC, "DEC" },
- { SPR_SRR0, "SRR0" },
- { SPR_SRR1, "SRR1" },
- { SPR_EIE, "EIE" },
- { SPR_EID, "EID" },
- { SPR_CMPA, "CMPA" },
- { SPR_CMPB, "CMPB" },
- { SPR_CMPC, "CMPC" },
- { SPR_CMPD, "CMPD" },
- { SPR_ICR, "ICR" },
- { SPR_DER, "DER" },
- { SPR_COUNTA, "COUNTA" },
- { SPR_COUNTB, "COUNTB" },
- { SPR_CMPE, "CMPE" },
- { SPR_CMPF, "CMPF" },
- { SPR_CMPG, "CMPG" },
- { SPR_CMPH, "CMPH" },
- { SPR_LCTRL1, "LCTRL1" },
- { SPR_LCTRL2, "LCTRL2" },
- { SPR_ICTRL, "ICTRL" },
- { SPR_BAR, "BAR" },
- { SPR_USPRG0, "USPRG0" },
- { SPR_SPRG4_RO, "SPRG4_RO" },
- { SPR_SPRG5_RO, "SPRG5_RO" },
- { SPR_SPRG6_RO, "SPRG6_RO" },
- { SPR_SPRG7_RO, "SPRG7_RO" },
- { SPR_SPRG0, "SPRG0" },
- { SPR_SPRG1, "SPRG1" },
- { SPR_SPRG2, "SPRG2" },
- { SPR_SPRG3, "SPRG3" },
- { SPR_SPRG4, "SPRG4" },
- { SPR_SPRG5, "SPRG5" },
- { SPR_SPRG6, "SPRG6" },
- { SPR_SPRG7, "SPRG7" },
- { SPR_EAR, "EAR" },
- { SPR_TBL, "TBL" },
- { SPR_TBU, "TBU" },
- { SPR_IC_CST, "IC_CST" },
- { SPR_IC_ADR, "IC_ADR" },
- { SPR_IC_DAT, "IC_DAT" },
- { SPR_DC_CST, "DC_CST" },
- { SPR_DC_ADR, "DC_ADR" },
- { SPR_DC_DAT, "DC_DAT" },
- { SPR_DPDR, "DPDR" },
- { SPR_IMMR, "IMMR" },
- { SPR_MI_CTR, "MI_CTR" },
- { SPR_MI_AP, "MI_AP" },
- { SPR_MI_EPN, "MI_EPN" },
- { SPR_MI_TWC, "MI_TWC" },
- { SPR_MI_RPN, "MI_RPN" },
- { SPR_MD_CTR, "MD_CTR" },
- { SPR_M_CASID, "M_CASID" },
- { SPR_MD_AP, "MD_AP" },
- { SPR_MD_EPN, "MD_EPN" },
- { SPR_M_TWB, "M_TWB" },
- { SPR_MD_TWC, "MD_TWC" },
- { SPR_MD_RPN, "MD_RPN" },
- { SPR_M_TW, "M_TW" },
- { SPR_MI_DBCAM, "MI_DBCAM" },
- { SPR_MI_DBRAM0, "MI_DBRAM0" },
- { SPR_MI_DBRAM1, "MI_DBRAM1" },
- { SPR_MD_DBCAM, "MD_DBCAM" },
- { SPR_MD_DBRAM0, "MD_DBRAM0" },
- { SPR_MD_DBRAM1, "MD_DBRAM1" },
- { SPR_ZPR, "ZPR" },
- { SPR_PID, "PID" },
- { SPR_CCR0, "CCR0" },
- { SPR_IAC3, "IAC3" },
- { SPR_IAC4, "IAC4" },
- { SPR_DVC1, "DVC1" },
- { SPR_DVC2, "DVC2" },
- { SPR_SGR, "SGR" },
- { SPR_DCWR, "DCWR" },
- { SPR_SLER, "SLER" },
- { SPR_SU0R, "SU0R" },
- { SPR_DBCR1, "DBCR1" },
- { SPR_ICDBDR, "ICDBDR" },
- { SPR_ESR, "ESR" },
- { SPR_DEAR, "DEAR" },
- { SPR_EVPR, "EVPR" },
- { SPR_TSR, "TSR" },
- { SPR_TCR, "TCR" },
- { SPR_PIT, "PIT" },
- { SPR_SRR2, "SRR2" },
- { SPR_SRR3, "SRR3" },
- { SPR_DBSR, "DBSR" },
- { SPR_DBCR0, "DBCR0" },
- { SPR_IAC1, "IAC1" },
- { SPR_IAC2, "IAC2" },
- { SPR_DAC1, "DAC1" },
- { SPR_DAC2, "DAC2" },
- { SPR_DCCR, "DCCR" },
- { SPR_ICCR, "ICCR" },
-};
-
-const unsigned int n_sprs = sizeof(spr_map) / sizeof(spr_map[0]);
-
-#endif
-
-/*
- * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are freely
- * permitted provided that the above copyright notice and this
- * paragraph and the following disclaimer are duplicated in all
- * such forms.
- *
- * This software is provided "AS IS" and without any express or
- * implied warranties, including, without limitation, the implied
- * warranties of merchantability and fitness for a particular
- * purpose.
- */
diff --git a/include/commproc.h b/include/commproc.h
deleted file mode 100644
index 12400e3edd..0000000000
--- a/include/commproc.h
+++ /dev/null
@@ -1,1818 +0,0 @@
-/*
- * MPC8xx Communication Processor Module.
- * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
- *
- * (C) Copyright 2000-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * This file contains structures and information for the communication
- * processor channels. Some CPM control and status is available
- * throught the MPC8xx internal memory map. See immap.h for details.
- * This file only contains what I need for the moment, not the total
- * CPM capabilities. I (or someone else) will add definitions as they
- * are needed. -- Dan
- *
- * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
- * bytes of the DP RAM and relocates the I2C parameter area to the
- * IDMA1 space. The remaining DP RAM is available for buffer descriptors
- * or other use.
- */
-#ifndef __CPM_8XX__
-#define __CPM_8XX__
-
-#include <linux/config.h>
-#include <asm/8xx_immap.h>
-
-/* CPM Command register.
-*/
-#define CPM_CR_RST ((ushort)0x8000)
-#define CPM_CR_OPCODE ((ushort)0x0f00)
-#define CPM_CR_CHAN ((ushort)0x00f0)
-#define CPM_CR_FLG ((ushort)0x0001)
-
-/* Some commands (there are more...later)
-*/
-#define CPM_CR_INIT_TRX ((ushort)0x0000)
-#define CPM_CR_INIT_RX ((ushort)0x0001)
-#define CPM_CR_INIT_TX ((ushort)0x0002)
-#define CPM_CR_HUNT_MODE ((ushort)0x0003)
-#define CPM_CR_STOP_TX ((ushort)0x0004)
-#define CPM_CR_RESTART_TX ((ushort)0x0006)
-#define CPM_CR_SET_GADDR ((ushort)0x0008)
-
-/* Channel numbers.
-*/
-#define CPM_CR_CH_SCC1 ((ushort)0x0000)
-#define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */
-#define CPM_CR_CH_SCC2 ((ushort)0x0004)
-#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI/IDMA2/Timers */
-#define CPM_CR_CH_SCC3 ((ushort)0x0008)
-#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */
-#define CPM_CR_CH_SCC4 ((ushort)0x000c)
-#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */
-
-#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4))
-
-/*
- * DPRAM defines and allocation functions
- */
-
-/* The dual ported RAM is multi-functional. Some areas can be (and are
- * being) used for microcode. There is an area that can only be used
- * as data ram for buffer descriptors, which is all we use right now.
- * Currently the first 512 and last 256 bytes are used for microcode.
- */
-#ifdef CFG_ALLOC_DPRAM
-
-#define CPM_DATAONLY_BASE ((uint)0x0800)
-#define CPM_DATAONLY_SIZE ((uint)0x0700)
-#define CPM_DP_NOSPACE ((uint)0x7fffffff)
-
-#else
-
-#define CPM_SERIAL_BASE 0x0800
-#define CPM_I2C_BASE 0x0820
-#define CPM_SPI_BASE 0x0840
-#define CPM_FEC_BASE 0x0860
-#define CPM_SERIAL2_BASE 0x08E0
-#define CPM_SCC_BASE 0x0900
-#define CPM_POST_BASE 0x0980
-#define CPM_WLKBD_BASE 0x0a00
-
-#endif
-
-#ifndef CFG_CPM_POST_WORD_ADDR
-#define CPM_POST_WORD_ADDR 0x07FC
-#else
-#define CPM_POST_WORD_ADDR CFG_CPM_POST_WORD_ADDR
-#endif
-
-#ifndef CFG_CPM_BOOTCOUNT_ADDR
-#define CPM_BOOTCOUNT_ADDR (CPM_POST_WORD_ADDR - 2*sizeof(ulong))
-#else
-#define CPM_BOOTCOUNT_ADDR CFG_CPM_BOOTCOUNT_ADDR
-#endif
-
-#define BD_IIC_START ((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */
-
-/* Export the base address of the communication processor registers
- * and dual port ram.
- */
-extern cpm8xx_t *cpmp; /* Pointer to comm processor */
-
-/* Buffer descriptors used by many of the CPM protocols.
-*/
-typedef struct cpm_buf_desc {
- ushort cbd_sc; /* Status and Control */
- ushort cbd_datlen; /* Data length in buffer */
- uint cbd_bufaddr; /* Buffer address in host memory */
-} cbd_t;
-
-#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
-#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
-#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
-#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
-#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
-#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
-#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
-#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
-#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
-#define BD_SC_BR ((ushort)0x0020) /* Break received */
-#define BD_SC_FR ((ushort)0x0010) /* Framing error */
-#define BD_SC_PR ((ushort)0x0008) /* Parity error */
-#define BD_SC_OV ((ushort)0x0002) /* Overrun */
-#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */
-
-/* Parameter RAM offsets.
-*/
-#define PROFF_SCC1 ((uint)0x0000)
-#define PROFF_IIC ((uint)0x0080)
-#define PROFF_SCC2 ((uint)0x0100)
-#define PROFF_SPI ((uint)0x0180)
-#define PROFF_SCC3 ((uint)0x0200)
-#define PROFF_SMC1 ((uint)0x0280)
-#define PROFF_SCC4 ((uint)0x0300)
-#define PROFF_SMC2 ((uint)0x0380)
-
-/* Define enough so I can at least use the serial port as a UART.
- * The MBX uses SMC1 as the host serial port.
- */
-typedef struct smc_uart {
- ushort smc_rbase; /* Rx Buffer descriptor base address */
- ushort smc_tbase; /* Tx Buffer descriptor base address */
- u_char smc_rfcr; /* Rx function code */
- u_char smc_tfcr; /* Tx function code */
- ushort smc_mrblr; /* Max receive buffer length */
- uint smc_rstate; /* Internal */
- uint smc_idp; /* Internal */
- ushort smc_rbptr; /* Internal */
- ushort smc_ibc; /* Internal */
- uint smc_rxtmp; /* Internal */
- uint smc_tstate; /* Internal */
- uint smc_tdp; /* Internal */
- ushort smc_tbptr; /* Internal */
- ushort smc_tbc; /* Internal */
- uint smc_txtmp; /* Internal */
- ushort smc_maxidl; /* Maximum idle characters */
- ushort smc_tmpidl; /* Temporary idle counter */
- ushort smc_brklen; /* Last received break length */
- ushort smc_brkec; /* rcv'd break condition counter */
- ushort smc_brkcr; /* xmt break count register */
- ushort smc_rmask; /* Temporary bit mask */
-} smc_uart_t;
-
-/* Function code bits.
-*/
-#define SMC_EB ((u_char)0x10) /* Set big endian byte order */
-
-/* SMC uart mode register.
-*/
-#define SMCMR_REN ((ushort)0x0001)
-#define SMCMR_TEN ((ushort)0x0002)
-#define SMCMR_DM ((ushort)0x000c)
-#define SMCMR_SM_GCI ((ushort)0x0000)
-#define SMCMR_SM_UART ((ushort)0x0020)
-#define SMCMR_SM_TRANS ((ushort)0x0030)
-#define SMCMR_SM_MASK ((ushort)0x0030)
-#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
-#define SMCMR_REVD SMCMR_PM_EVEN
-#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
-#define SMCMR_BS SMCMR_PEN
-#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
-#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
-#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
-
-/* SMC2 as Centronics parallel printer. It is half duplex, in that
- * it can only receive or transmit. The parameter ram values for
- * each direction are either unique or properly overlap, so we can
- * include them in one structure.
- */
-typedef struct smc_centronics {
- ushort scent_rbase;
- ushort scent_tbase;
- u_char scent_cfcr;
- u_char scent_smask;
- ushort scent_mrblr;
- uint scent_rstate;
- uint scent_r_ptr;
- ushort scent_rbptr;
- ushort scent_r_cnt;
- uint scent_rtemp;
- uint scent_tstate;
- uint scent_t_ptr;
- ushort scent_tbptr;
- ushort scent_t_cnt;
- uint scent_ttemp;
- ushort scent_max_sl;
- ushort scent_sl_cnt;
- ushort scent_character1;
- ushort scent_character2;
- ushort scent_character3;
- ushort scent_character4;
- ushort scent_character5;
- ushort scent_character6;
- ushort scent_character7;
- ushort scent_character8;
- ushort scent_rccm;
- ushort scent_rccr;
-} smc_cent_t;
-
-/* Centronics Status Mask Register.
-*/
-#define SMC_CENT_F ((u_char)0x08)
-#define SMC_CENT_PE ((u_char)0x04)
-#define SMC_CENT_S ((u_char)0x02)
-
-/* SMC Event and Mask register.
-*/
-#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
-#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
-#define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */
-#define SMCM_BSY ((unsigned char)0x04)
-#define SMCM_TX ((unsigned char)0x02)
-#define SMCM_RX ((unsigned char)0x01)
-
-/* Baud rate generators.
-*/
-#define CPM_BRG_RST ((uint)0x00020000)
-#define CPM_BRG_EN ((uint)0x00010000)
-#define CPM_BRG_EXTC_INT ((uint)0x00000000)
-#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000)
-#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000)
-#define CPM_BRG_ATB ((uint)0x00002000)
-#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
-#define CPM_BRG_DIV16 ((uint)0x00000001)
-
-/* SI Clock Route Register
-*/
-#define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000)
-#define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000)
-#define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800)
-#define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100)
-#define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000)
-#define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000)
-#define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000)
-#define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000)
-
-/* SCCs.
-*/
-#define SCC_GSMRH_IRP ((uint)0x00040000)
-#define SCC_GSMRH_GDE ((uint)0x00010000)
-#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
-#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
-#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
-#define SCC_GSMRH_REVD ((uint)0x00002000)
-#define SCC_GSMRH_TRX ((uint)0x00001000)
-#define SCC_GSMRH_TTX ((uint)0x00000800)
-#define SCC_GSMRH_CDP ((uint)0x00000400)
-#define SCC_GSMRH_CTSP ((uint)0x00000200)
-#define SCC_GSMRH_CDS ((uint)0x00000100)
-#define SCC_GSMRH_CTSS ((uint)0x00000080)
-#define SCC_GSMRH_TFL ((uint)0x00000040)
-#define SCC_GSMRH_RFW ((uint)0x00000020)
-#define SCC_GSMRH_TXSY ((uint)0x00000010)
-#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
-#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
-#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
-#define SCC_GSMRH_RTSM ((uint)0x00000002)
-#define SCC_GSMRH_RSYN ((uint)0x00000001)
-
-#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
-#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
-#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
-#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
-#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
-#define SCC_GSMRL_TCI ((uint)0x10000000)
-#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
-#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
-#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
-#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
-#define SCC_GSMRL_RINV ((uint)0x02000000)
-#define SCC_GSMRL_TINV ((uint)0x01000000)
-#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
-#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
-#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
-#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
-#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
-#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
-#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
-#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
-#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
-#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
-#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
-#define SCC_GSMRL_TEND ((uint)0x00040000)
-#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
-#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
-#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
-#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
-#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
-#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
-#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
-#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
-#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
-#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
-#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
-#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
-#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
-#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
-#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
-#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
-#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
-#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
-#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
-#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
-#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
-#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
-#define SCC_GSMRL_ENR ((uint)0x00000020)
-#define SCC_GSMRL_ENT ((uint)0x00000010)
-#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
-#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
-#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
-#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
-#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
-#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
-#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
-#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
-#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
-#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
-
-#define SCC_TODR_TOD ((ushort)0x8000)
-
-/* SCC Event and Mask register.
-*/
-#define SCCM_TXE ((unsigned char)0x10)
-#define SCCM_BSY ((unsigned char)0x04)
-#define SCCM_TX ((unsigned char)0x02)
-#define SCCM_RX ((unsigned char)0x01)
-
-typedef struct scc_param {
- ushort scc_rbase; /* Rx Buffer descriptor base address */
- ushort scc_tbase; /* Tx Buffer descriptor base address */
- u_char scc_rfcr; /* Rx function code */
- u_char scc_tfcr; /* Tx function code */
- ushort scc_mrblr; /* Max receive buffer length */
- uint scc_rstate; /* Internal */
- uint scc_idp; /* Internal */
- ushort scc_rbptr; /* Internal */
- ushort scc_ibc; /* Internal */
- uint scc_rxtmp; /* Internal */
- uint scc_tstate; /* Internal */
- uint scc_tdp; /* Internal */
- ushort scc_tbptr; /* Internal */
- ushort scc_tbc; /* Internal */
- uint scc_txtmp; /* Internal */
- uint scc_rcrc; /* Internal */
- uint scc_tcrc; /* Internal */
-} sccp_t;
-
-/* Function code bits.
-*/
-#define SCC_EB ((u_char)0x10) /* Set big endian byte order */
-
-/* CPM Ethernet through SCCx.
- */
-typedef struct scc_enet {
- sccp_t sen_genscc;
- uint sen_cpres; /* Preset CRC */
- uint sen_cmask; /* Constant mask for CRC */
- uint sen_crcec; /* CRC Error counter */
- uint sen_alec; /* alignment error counter */
- uint sen_disfc; /* discard frame counter */
- ushort sen_pads; /* Tx short frame pad character */
- ushort sen_retlim; /* Retry limit threshold */
- ushort sen_retcnt; /* Retry limit counter */
- ushort sen_maxflr; /* maximum frame length register */
- ushort sen_minflr; /* minimum frame length register */
- ushort sen_maxd1; /* maximum DMA1 length */
- ushort sen_maxd2; /* maximum DMA2 length */
- ushort sen_maxd; /* Rx max DMA */
- ushort sen_dmacnt; /* Rx DMA counter */
- ushort sen_maxb; /* Max BD byte count */
- ushort sen_gaddr1; /* Group address filter */
- ushort sen_gaddr2;
- ushort sen_gaddr3;
- ushort sen_gaddr4;
- uint sen_tbuf0data0; /* Save area 0 - current frame */
- uint sen_tbuf0data1; /* Save area 1 - current frame */
- uint sen_tbuf0rba; /* Internal */
- uint sen_tbuf0crc; /* Internal */
- ushort sen_tbuf0bcnt; /* Internal */
- ushort sen_paddrh; /* physical address (MSB) */
- ushort sen_paddrm;
- ushort sen_paddrl; /* physical address (LSB) */
- ushort sen_pper; /* persistence */
- ushort sen_rfbdptr; /* Rx first BD pointer */
- ushort sen_tfbdptr; /* Tx first BD pointer */
- ushort sen_tlbdptr; /* Tx last BD pointer */
- uint sen_tbuf1data0; /* Save area 0 - current frame */
- uint sen_tbuf1data1; /* Save area 1 - current frame */
- uint sen_tbuf1rba; /* Internal */
- uint sen_tbuf1crc; /* Internal */
- ushort sen_tbuf1bcnt; /* Internal */
- ushort sen_txlen; /* Tx Frame length counter */
- ushort sen_iaddr1; /* Individual address filter */
- ushort sen_iaddr2;
- ushort sen_iaddr3;
- ushort sen_iaddr4;
- ushort sen_boffcnt; /* Backoff counter */
-
- /* NOTE: Some versions of the manual have the following items
- * incorrectly documented. Below is the proper order.
- */
- ushort sen_taddrh; /* temp address (MSB) */
- ushort sen_taddrm;
- ushort sen_taddrl; /* temp address (LSB) */
-} scc_enet_t;
-
-/**********************************************************************
- *
- * Board specific configuration settings.
- *
- * Please note that we use the presence of a #define SCC_ENET and/or
- * #define FEC_ENET to enable the SCC resp. FEC ethernet drivers.
- **********************************************************************/
-
-
-/*** ADS *************************************************************/
-
-#if defined(CONFIG_MPC860) && defined(CONFIG_ADS)
-/* This ENET stuff is for the MPC860ADS with ethernet on SCC1.
- */
-
-#define PROFF_ENET PROFF_SCC1
-#define CPM_CR_ENET CPM_CR_CH_SCC1
-#define SCC_ENET 0
-
-#define PA_ENET_RXD ((ushort)0x0001)
-#define PA_ENET_TXD ((ushort)0x0002)
-#define PA_ENET_TCLK ((ushort)0x0100)
-#define PA_ENET_RCLK ((ushort)0x0200)
-
-#define PB_ENET_TENA ((uint)0x00001000)
-
-#define PC_ENET_CLSN ((ushort)0x0010)
-#define PC_ENET_RENA ((ushort)0x0020)
-
-#define SICR_ENET_MASK ((uint)0x000000ff)
-#define SICR_ENET_CLKRT ((uint)0x0000002c)
-
-/* 68160 PHY control */
-
-#define PC_ENET_ETHLOOP ((ushort)0x0800)
-#define PC_ENET_TPFLDL ((ushort)0x0400)
-#define PC_ENET_TPSQEL ((ushort)0x0200)
-
-#endif /* MPC860ADS */
-
-/*** AMX860 **********************************************/
-
-#if defined(CONFIG_AMX860)
-
-/* This ENET stuff is for the AMX860 with ethernet on SCC1.
- */
-
-#define PROFF_ENET PROFF_SCC1
-#define CPM_CR_ENET CPM_CR_CH_SCC1
-#define SCC_ENET 0
-
-#define PA_ENET_RXD ((ushort)0x0001)
-#define PA_ENET_TXD ((ushort)0x0002)
-#define PA_ENET_TCLK ((ushort)0x0400)
-#define PA_ENET_RCLK ((ushort)0x0800)
-
-#define PB_ENET_TENA ((uint)0x00001000)
-
-#define PC_ENET_CLSN ((ushort)0x0010)
-#define PC_ENET_RENA ((ushort)0x0020)
-
-#define SICR_ENET_MASK ((uint)0x000000ff)
-#define SICR_ENET_CLKRT ((uint)0x0000003e)
-
-/* 68160 PHY control */
-
-#define PB_ENET_ETHLOOP ((uint)0x00020000)
-#define PB_ENET_TPFLDL ((uint)0x00010000)
-#define PB_ENET_TPSQEL ((uint)0x00008000)
-#define PD_ENET_ETH_EN ((ushort)0x0004)
-
-#endif /* CONFIG_AMX860 */
-
-/*** BSEIP **********************************************************/
-
-#ifdef CONFIG_BSEIP
-/* This ENET stuff is for the MPC823 with ethernet on SCC2.
- * This is unique to the BSE ip-Engine board.
- */
-#define PROFF_ENET PROFF_SCC2
-#define CPM_CR_ENET CPM_CR_CH_SCC2
-#define SCC_ENET 1
-#define PA_ENET_RXD ((ushort)0x0004)
-#define PA_ENET_TXD ((ushort)0x0008)
-#define PA_ENET_TCLK ((ushort)0x0100)
-#define PA_ENET_RCLK ((ushort)0x0200)
-#define PB_ENET_TENA ((uint)0x00002000)
-#define PC_ENET_CLSN ((ushort)0x0040)
-#define PC_ENET_RENA ((ushort)0x0080)
-
-/* BSE uses port B and C bits for PHY control also.
-*/
-#define PB_BSE_POWERUP ((uint)0x00000004)
-#define PB_BSE_FDXDIS ((uint)0x00008000)
-#define PC_BSE_LOOPBACK ((ushort)0x0800)
-
-#define SICR_ENET_MASK ((uint)0x0000ff00)
-#define SICR_ENET_CLKRT ((uint)0x00002c00)
-#endif /* CONFIG_BSEIP */
-
-/*** BSEIP **********************************************************/
-
-#ifdef CONFIG_FLAGADM
-/* Enet configuration for the FLAGADM */
-/* Enet on SCC2 */
-
-#define PROFF_ENET PROFF_SCC2
-#define CPM_CR_ENET CPM_CR_CH_SCC2
-#define SCC_ENET 1
-#define PA_ENET_RXD ((ushort)0x0004)
-#define PA_ENET_TXD ((ushort)0x0008)
-#define PA_ENET_TCLK ((ushort)0x0100)
-#define PA_ENET_RCLK ((ushort)0x0400)
-#define PB_ENET_TENA ((uint)0x00002000)
-#define PC_ENET_CLSN ((ushort)0x0040)
-#define PC_ENET_RENA ((ushort)0x0080)
-
-#define SICR_ENET_MASK ((uint)0x0000ff00)
-#define SICR_ENET_CLKRT ((uint)0x00003400)
-#endif /* CONFIG_FLAGADM */
-
-/*** C2MON **********************************************************/
-
-#ifdef CONFIG_C2MON
-
-# ifndef CONFIG_FEC_ENET /* use SCC for 10Mbps Ethernet */
-# error "Ethernet on SCC not supported on C2MON Board!"
-# else /* Use FEC for Fast Ethernet */
-
-#undef SCC_ENET
-#define FEC_ENET
-
-#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
-#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
-#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
-#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
-#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
-#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
-#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
-#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
-#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
-#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
-#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
-#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
-#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
-
-#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
-
-# endif /* CONFIG_FEC_ENET */
-#endif /* CONFIG_C2MON */
-
-/*********************************************************************/
-
-
-/*** CCM and PCU E ***********************************************/
-
-/* The PCU E and CCM use the FEC on a MPC860T for Ethernet */
-
-#if defined (CONFIG_PCU_E) || defined(CONFIG_CCM)
-
-#define FEC_ENET /* use FEC for EThernet */
-#undef SCC_ENET
-
-#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
-#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
-#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
-#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
-#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
-#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
-#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
-#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
-#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
-#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
-#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
-#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
-#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
-
-#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
-
-#endif /* CONFIG_PCU_E, CONFIG_CCM */
-
-/*** ELPT860 *********************************************************/
-
-#ifdef CONFIG_ELPT860
-/* Bits in parallel I/O port registers that have to be set/cleared
- * to configure the pins for SCC1 use.
- */
-# define PROFF_ENET PROFF_SCC1
-# define CPM_CR_ENET CPM_CR_CH_SCC1
-# define SCC_ENET 0
-
-# define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
-# define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
-# define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
-# define PA_ENET_TCLK ((ushort)0x0200) /* PA 6 */
-
-# define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
-# define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
-# define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
-
-/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK1) to
- * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
- */
-# define SICR_ENET_MASK ((uint)0x000000FF)
-# define SICR_ENET_CLKRT ((uint)0x00000025)
-#endif /* CONFIG_ELPT860 */
-
-/*** ESTEEM 192E **************************************************/
-#ifdef CONFIG_ESTEEM192E
-/* ESTEEM192E
- * This ENET stuff is for the MPC850 with ethernet on SCC2. This
- * is very similar to the RPX-Lite configuration.
- * Note TENA , LOOPBACK , FDPLEX_DIS on Port B.
- */
-
-#define PROFF_ENET PROFF_SCC2
-#define CPM_CR_ENET CPM_CR_CH_SCC2
-#define SCC_ENET 1
-
-#define PA_ENET_RXD ((ushort)0x0004)
-#define PA_ENET_TXD ((ushort)0x0008)
-#define PA_ENET_TCLK ((ushort)0x0200)
-#define PA_ENET_RCLK ((ushort)0x0800)
-#define PB_ENET_TENA ((uint)0x00002000)
-#define PC_ENET_CLSN ((ushort)0x0040)
-#define PC_ENET_RENA ((ushort)0x0080)
-
-#define SICR_ENET_MASK ((uint)0x0000ff00)
-#define SICR_ENET_CLKRT ((uint)0x00003d00)
-
-#define PB_ENET_LOOPBACK ((uint)0x00004000)
-#define PB_ENET_FDPLEX_DIS ((uint)0x00008000)
-
-#endif
-
-/*** FADS823 ********************************************************/
-
-#if defined(CONFIG_MPC823FADS) && defined(CONFIG_FADS)
-/* This ENET stuff is for the MPC823FADS with ethernet on SCC2.
- */
-#ifdef CONFIG_SCC2_ENET
-#define PROFF_ENET PROFF_SCC2
-#define CPM_CR_ENET CPM_CR_CH_SCC2
-#define SCC_ENET 1
-#define CPMVEC_ENET CPMVEC_SCC2
-#endif
-
-#ifdef CONFIG_SCC1_ENET
-#define PROFF_ENET PROFF_SCC1
-#define CPM_CR_ENET CPM_CR_CH_SCC1
-#define SCC_ENET 0
-#define CPMVEC_ENET CPMVEC_SCC1
-#endif
-
-#define PA_ENET_RXD ((ushort)0x0004)
-#define PA_ENET_TXD ((ushort)0x0008)
-#define PA_ENET_TCLK ((ushort)0x0400)
-#define PA_ENET_RCLK ((ushort)0x0200)
-
-#define PB_ENET_TENA ((uint)0x00002000)
-
-#define PC_ENET_CLSN ((ushort)0x0040)
-#define PC_ENET_RENA ((ushort)0x0080)
-
-#define SICR_ENET_MASK ((uint)0x0000ff00)
-#define SICR_ENET_CLKRT ((uint)0x00002e00)
-
-#endif /* CONFIG_FADS823FADS */
-
-/*** FADS850SAR ********************************************************/
-
-#if defined(CONFIG_MPC850SAR) && defined(CONFIG_FADS)
-/* This ENET stuff is for the MPC850SAR with ethernet on SCC2. Some of
- * this may be unique to the FADS850SAR configuration.
- * Note TENA is on Port B.
- */
-#define PROFF_ENET PROFF_SCC2
-#define CPM_CR_ENET CPM_CR_CH_SCC2
-#define SCC_ENET 1
-#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
-#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
-#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
-#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
-#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
-#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
-#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
-
-#define SICR_ENET_MASK ((uint)0x0000ff00)
-#define SICR_ENET_CLKRT ((uint)0x00002f00) /* RCLK-CLK2, TCLK-CLK4 */
-#endif /* CONFIG_FADS850SAR */
-
-/*** FADS860T********************************************************/
-
-#if defined(CONFIG_FADS) && defined(CONFIG_MPC86x)
-/*
- * This ENET stuff is for the MPC86xFADS/MPC8xxADS with ethernet on SCC1.
- */
-#ifdef CONFIG_SCC1_ENET
-
-#define SCC_ENET 0
-
-#define PROFF_ENET PROFF_SCC1
-#define CPM_CR_ENET CPM_CR_CH_SCC1
-
-#define PA_ENET_RXD ((ushort)0x0001)
-#define PA_ENET_TXD ((ushort)0x0002)
-#define PA_ENET_TCLK ((ushort)0x0100)
-#define PA_ENET_RCLK ((ushort)0x0200)
-
-#define PB_ENET_TENA ((uint)0x00001000)
-
-#define PC_ENET_CLSN ((ushort)0x0010)
-#define PC_ENET_RENA ((ushort)0x0020)
-
-#define SICR_ENET_MASK ((uint)0x000000ff)
-#define SICR_ENET_CLKRT ((uint)0x0000002c)
-
-#endif /* CONFIG_SCC1_ETHERNET */
-
-/*
- * This ENET stuff is for the MPC860TFADS/MPC86xADS/MPC885ADS
- * with ethernet on FEC.
- */
-
-#ifdef CONFIG_FEC_ENET
-#define FEC_ENET /* Use FEC for Ethernet */
-#endif /* CONFIG_FEC_ENET */
-
-#endif /* CONFIG_FADS && CONFIG_MPC86x */
-
-/*** FPS850L, FPS860L ************************************************/
-
-#if defined(CONFIG_FPS850L) || defined(CONFIG_FPS860L)
-/* Bits in parallel I/O port registers that have to be set/cleared
- * to configure the pins for SCC2 use.
- */
-#define PROFF_ENET PROFF_SCC2
-#define CPM_CR_ENET CPM_CR_CH_SCC2
-#define SCC_ENET 1
-#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
-#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
-#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
-#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
-
-#define PC_ENET_TENA ((ushort)0x0002) /* PC 14 */
-#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
-#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
-
-/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
- * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
- */
-#define SICR_ENET_MASK ((uint)0x0000ff00)
-#define SICR_ENET_CLKRT ((uint)0x00002600)
-#endif /* CONFIG_FPS850L, CONFIG_FPS860L */
-
-/*** GEN860T **********************************************************/
-#if defined(CONFIG_GEN860T)
-#undef SCC_ENET
-#define FEC_ENET
-
-#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
-#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
-#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
-#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
-#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
-#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
-#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
-#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
-#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
-#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
-#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
-#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
-#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
-#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3-15 */
-#endif /* CONFIG_GEN860T */
-
-/*** GENIETV ********************************************************/
-
-#if defined(CONFIG_GENIETV)
-/* Ethernet is only on SCC2 */
-
-#define CONFIG_SCC2_ENET
-#define PROFF_ENET PROFF_SCC2
-#define CPM_CR_ENET CPM_CR_CH_SCC2
-#define SCC_ENET 1
-#define CPMVEC_ENET CPMVEC_SCC2
-
-#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
-#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
-#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
-#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
-
-#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
-
-#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
-#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
-
-#define SICR_ENET_MASK ((uint)0x0000ff00)
-#define SICR_ENET_CLKRT ((uint)0x00002e00)
-
-#endif /* CONFIG_GENIETV */
-
-/*** GTH ******************************************************/
-
-#ifdef CONFIG_GTH
-#ifdef CONFIG_FEC_ENET
-#define FEC_ENET /* use FEC for EThernet */
-#endif /* CONFIG_FEC_ETHERNET */
-
-/* This ENET stuff is for GTH 10 Mbit ( SCC ) */
-#define PROFF_ENET PROFF_SCC1
-#define CPM_CR_ENET CPM_CR_CH_SCC1
-#define SCC_ENET 0
-
-#define PA_ENET_RXD ((ushort)0x0001) /* PA15 */
-#define PA_ENET_TXD ((ushort)0x0002) /* PA14 */
-#define PA_ENET_TCLK ((ushort)0x0800) /* PA4 */
-#define PA_ENET_RCLK ((ushort)0x0400) /* PA5 */
-
-#define PB_ENET_TENA ((uint)0x00001000) /* PB19 */
-
-#define PC_ENET_CLSN ((ushort)0x0010) /* PC11 */
-#define PC_ENET_RENA ((ushort)0x0020) /* PC10 */
-
-/* NOTE. This is reset for 10Mbit port only */
-#define PC_ENET_RESET ((ushort)0x0100) /* PC 7 */
-
-#define SICR_ENET_MASK ((uint)0x000000ff)
-
-/* TCLK PA4 -->CLK4, RCLK PA5 -->CLK3 */
-#define SICR_ENET_CLKRT ((uint)0x00000037)
-
-#endif /* CONFIG_GTH */
-
-/*** HERMES-PRO ******************************************************/
-
-/* The HERMES-PRO uses the FEC on a MPC860T for Ethernet */
-
-#ifdef CONFIG_HERMES
-
-#define FEC_ENET /* use FEC for EThernet */
-#undef SCC_ENET
-
-
-#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
-#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
-#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
-#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
-#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
-#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
-#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
-#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
-#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
-#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
-#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
-#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
-#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
-
-#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
-
-#endif /* CONFIG_HERMES */
-
-/*** IAD210 **********************************************************/
-
-/* The IAD210 uses the FEC on a MPC860P for Ethernet */
-
-#if defined(CONFIG_IAD210)
-
-# define FEC_ENET /* use FEC for Ethernet */
-# undef SCC_ENET
-
-# define PD_MII_TXD1 ((ushort) 0x1000 ) /* PD 3 */
-# define PD_MII_TXD2 ((ushort) 0x0800 ) /* PD 4 */
-# define PD_MII_TXD3 ((ushort) 0x0400 ) /* PD 5 */
-# define PD_MII_RX_DV ((ushort) 0x0200 ) /* PD 6 */
-# define PD_MII_RX_ERR ((ushort) 0x0100 ) /* PD 7 */
-# define PD_MII_RX_CLK ((ushort) 0x0080 ) /* PD 8 */
-# define PD_MII_TXD0 ((ushort) 0x0040 ) /* PD 9 */
-# define PD_MII_RXD0 ((ushort) 0x0020 ) /* PD 10 */
-# define PD_MII_TX_ERR ((ushort) 0x0010 ) /* PD 11 */
-# define PD_MII_MDC ((ushort) 0x0008 ) /* PD 12 */
-# define PD_MII_RXD1 ((ushort) 0x0004 ) /* PD 13 */
-# define PD_MII_RXD2 ((ushort) 0x0002 ) /* PD 14 */
-# define PD_MII_RXD3 ((ushort) 0x0001 ) /* PD 15 */
-
-# define PD_MII_MASK ((ushort) 0x1FFF ) /* PD 3...15 */
-
-#endif /* CONFIG_IAD210 */
-
-/*** ICU862 **********************************************************/
-
-#if defined(CONFIG_ICU862)
-
-#ifdef CONFIG_FEC_ENET
-#define FEC_ENET /* use FEC for EThernet */
-#endif /* CONFIG_FEC_ETHERNET */
-
-#endif /* CONFIG_ICU862 */
-
-/*** IP860 **********************************************************/
-
-#if defined(CONFIG_IP860)
-/* Bits in parallel I/O port registers that have to be set/cleared
- * to configure the pins for SCC1 use.
- */
-#define PROFF_ENET PROFF_SCC1
-#define CPM_CR_ENET CPM_CR_CH_SCC1
-#define SCC_ENET 0
-#define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
-#define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
-#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
-#define PA_ENET_TCLK ((ushort)0x0100) /* PA 7 */
-
-#define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
-#define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
-#define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
-
-#define PB_ENET_RESET (uint)0x00000008 /* PB 28 */
-#define PB_ENET_JABD (uint)0x00000004 /* PB 29 */
-
-/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
- * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
- */
-#define SICR_ENET_MASK ((uint)0x000000ff)
-#define SICR_ENET_CLKRT ((uint)0x0000002C)
-#endif /* CONFIG_IP860 */
-
-/*** IVMS8 **********************************************************/
-
-/* The IVMS8 uses the FEC on a MPC860T for Ethernet */
-
-#if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)
-
-#define FEC_ENET /* use FEC for EThernet */
-#undef SCC_ENET
-
-#define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */
-
-#define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */
-
-#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
-#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
-#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
-#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
-#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
-#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
-#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
-#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
-#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
-#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
-#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
-#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
-#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
-
-#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
-
-#endif /* CONFIG_IVMS8, CONFIG_IVML24 */
-
-/*** KUP4K, KUP4X ****************************************************/
-/* The KUP4 boards uses the FEC on a MPC8xx for Ethernet */
-
-#if defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
-
-#define FEC_ENET /* use FEC for EThernet */
-#undef SCC_ENET
-
-#define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */
-
-#define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */
-
-#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
-#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
-#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
-#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
-#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
-#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
-#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
-#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
-#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
-#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
-#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
-#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
-#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
-
-#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
-
-#endif /* CONFIG_KUP4K */
-
-
-/*** LANTEC *********************************************************/
-
-#if defined(CONFIG_LANTEC) && CONFIG_LANTEC >= 2
-/* Bits in parallel I/O port registers that have to be set/cleared
- * to configure the pins for SCC2 use.
- */
-#define PROFF_ENET PROFF_SCC2
-#define CPM_CR_ENET CPM_CR_CH_SCC2
-#define SCC_ENET 1
-#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
-#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
-#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
-#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
-
-#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
-
-#define PC_ENET_LBK ((ushort)0x0010) /* PC 11 */
-#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
-#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
-
-/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
- * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
- */
-#define SICR_ENET_MASK ((uint)0x0000FF00)
-#define SICR_ENET_CLKRT ((uint)0x00002E00)
-#endif /* CONFIG_LANTEC v2 */
-
-/*** LWMON **********************************************************/
-
-#if defined(CONFIG_LWMON)
-/* Bits in parallel I/O port registers that have to be set/cleared
- * to configure the pins for SCC2 use.
- */
-#define PROFF_ENET PROFF_SCC2
-#define CPM_CR_ENET CPM_CR_CH_SCC2
-#define SCC_ENET 1
-#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
-#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
-#define PA_ENET_RCLK ((ushort)0x0800) /* PA 4 */
-#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
-
-#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
-
-#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
-#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
-
-/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK4) to
- * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
- */
-#define SICR_ENET_MASK ((uint)0x0000ff00)
-#define SICR_ENET_CLKRT ((uint)0x00003E00)
-#endif /* CONFIG_LWMON */
-
-/*** NX823 ***********************************************/
-
-#if defined(CONFIG_NX823)
-/* Bits in parallel I/O port registers that have to be set/cleared
- * to configure the pins for SCC1 use.
- */
-#define PROFF_ENET PROFF_SCC2
-#define CPM_CR_ENET CPM_CR_CH_SCC2
-#define SCC_ENET 1
-#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
-#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
-#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
-#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
-
-#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
-
-#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
-#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
-
-/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
- * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
- */
-#define SICR_ENET_MASK ((uint)0x0000ff00)
-#define SICR_ENET_CLKRT ((uint)0x00002f00)
-
-#endif /* CONFIG_NX823 */
-
-/*** MBX ************************************************************/
-
-#ifdef CONFIG_MBX
-/* Bits in parallel I/O port registers that have to be set/cleared
- * to configure the pins for SCC1 use. The TCLK and RCLK seem unique
- * to the MBX860 board. Any two of the four available clocks could be
- * used, and the MPC860 cookbook manual has an example using different
- * clock pins.
- */
-#define PROFF_ENET PROFF_SCC1
-#define CPM_CR_ENET CPM_CR_CH_SCC1
-#define SCC_ENET 0
-#define PA_ENET_RXD ((ushort)0x0001)
-#define PA_ENET_TXD ((ushort)0x0002)
-#define PA_ENET_TCLK ((ushort)0x0200)
-#define PA_ENET_RCLK ((ushort)0x0800)
-#define PC_ENET_TENA ((ushort)0x0001)
-#define PC_ENET_CLSN ((ushort)0x0010)
-#define PC_ENET_RENA ((ushort)0x0020)
-
-/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
- * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
- */
-#define SICR_ENET_MASK ((uint)0x000000ff)
-#define SICR_ENET_CLKRT ((uint)0x0000003d)
-#endif /* CONFIG_MBX */
-
-/*** MHPC ********************************************************/
-
-#if defined(CONFIG_MHPC)
-/* This ENET stuff is for the MHPC with ethernet on SCC2.
- * Note TENA is on Port B.
- */
-#define PROFF_ENET PROFF_SCC2
-#define CPM_CR_ENET CPM_CR_CH_SCC2
-#define SCC_ENET 1
-#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
-#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
-#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
-#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
-#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
-#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
-#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
-
-#define SICR_ENET_MASK ((uint)0x0000ff00)
-#define SICR_ENET_CLKRT ((uint)0x00002e00) /* RCLK-CLK2, TCLK-CLK3 */
-#endif /* CONFIG_MHPC */
-
-/*** NETVIA *******************************************************/
-
-/* SinoVee Microsystems SC8xx series FEL8xx-AT,SC823,SC850,SC855T,SC860T */
-#if ( defined CONFIG_SVM_SC8xx )
-# ifndef CONFIG_FEC_ENET
-
-#define PROFF_ENET PROFF_SCC2
-#define CPM_CR_ENET CPM_CR_CH_SCC2
-#define SCC_ENET 1
-
- /* Bits in parallel I/O port registers that have to be set/cleared
- * * * * to configure the pins for SCC2 use.
- * * * */
-#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
-#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
-#define PA_ENET_RCLK ((ushort)0x0400) /* PA 5 */
-#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
-
-#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
-
-#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
-#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
-/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
- * * * * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
- * * * */
-#define SICR_ENET_MASK ((uint)0x0000ff00)
-#define SICR_ENET_CLKRT ((uint)0x00003700)
-
-# else /* Use FEC for Fast Ethernet */
-
-#undef SCC_ENET
-#define FEC_ENET
-
-#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
-#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
-#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
-#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
-#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
-#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
-#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
-#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
-#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
-#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
-#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
-#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
-#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
-
-#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
-
-# endif /* CONFIG_FEC_ENET */
-#endif /* CONFIG_SVM_SC8xx */
-
-
-#if defined(CONFIG_NETVIA)
-/* Bits in parallel I/O port registers that have to be set/cleared
- * to configure the pins for SCC2 use.
- */
-#define PROFF_ENET PROFF_SCC2
-#define CPM_CR_ENET CPM_CR_CH_SCC2
-#define SCC_ENET 1
-#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
-#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
-#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
-#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
-
-#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
-# define PB_ENET_PDN ((ushort)0x4000) /* PB 17 */
-#elif CONFIG_NETVIA_VERSION >= 2
-# define PC_ENET_PDN ((ushort)0x0008) /* PC 12 */
-#endif
-
-#define PB_ENET_TENA ((ushort)0x2000) /* PB 18 */
-
-#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
-#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
-
-/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
- * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
- */
-#define SICR_ENET_MASK ((uint)0x0000ff00)
-#define SICR_ENET_CLKRT ((uint)0x00002f00)
-
-#endif /* CONFIG_NETVIA */
-
-/*** QS850/QS823 ***************************************************/
-
-#if defined(CONFIG_QS850) || defined(CONFIG_QS823)
-#undef FEC_ENET /* Don't use FEC for EThernet */
-
-#define PROFF_ENET PROFF_SCC2
-#define CPM_CR_ENET CPM_CR_CH_SCC2
-#define SCC_ENET 1
-
-#define PA_ENET_RXD ((ushort)0x0004) /* RXD on PA13 (Pin D9) */
-#define PA_ENET_TXD ((ushort)0x0008) /* TXD on PA12 (Pin D7) */
-#define PC_ENET_RENA ((ushort)0x0080) /* RENA on PC8 (Pin D12) */
-#define PC_ENET_CLSN ((ushort)0x0040) /* CLSN on PC9 (Pin C12) */
-#define PA_ENET_TCLK ((ushort)0x0200) /* TCLK on PA6 (Pin D8) */
-#define PA_ENET_RCLK ((ushort)0x0800) /* RCLK on PA4 (Pin D10) */
-#define PB_ENET_TENA ((uint)0x00002000) /* TENA on PB18 (Pin D11) */
-#define PC_ENET_LBK ((ushort)0x0010) /* Loopback control on PC11 (Pin B14) */
-#define PC_ENET_LI ((ushort)0x0020) /* Link Integrity control PC10 (A15) */
-#define PC_ENET_SQE ((ushort)0x0100) /* SQE Disable control PC7 (B15) */
-
-/* SCC2 TXCLK from CLK2
- * SCC2 RXCLK from CLK4
- * SCC2 Connected to NMSI */
-#define SICR_ENET_MASK ((uint)0x00007F00)
-#define SICR_ENET_CLKRT ((uint)0x00003D00)
-
-#endif /* CONFIG_QS850/QS823 */
-
-/*** QS860T ***************************************************/
-
-#ifdef CONFIG_QS860T
-#ifdef CONFIG_FEC_ENET
-#define FEC_ENET /* use FEC for EThernet */
-#endif /* CONFIG_FEC_ETHERNET */
-
-/* This ENET stuff is for GTH 10 Mbit ( SCC ) */
-#define PROFF_ENET PROFF_SCC1
-#define CPM_CR_ENET CPM_CR_CH_SCC1
-#define SCC_ENET 0
-
-#define PA_ENET_RXD ((ushort)0x0001) /* PA15 */
-#define PA_ENET_TXD ((ushort)0x0002) /* PA14 */
-#define PA_ENET_TCLK ((ushort)0x0800) /* PA4 */
-#define PA_ENET_RCLK ((ushort)0x0200) /* PA6 */
-#define PB_ENET_TENA ((uint)0x00001000) /* PB19 */
-#define PC_ENET_CLSN ((ushort)0x0010) /* PC11 */
-#define PC_ENET_RENA ((ushort)0x0020) /* PC10 */
-
-#define SICR_ENET_MASK ((uint)0x000000ff)
-/* RCLK PA4 -->CLK4, TCLK PA6 -->CLK2 */
-#define SICR_ENET_CLKRT ((uint)0x0000003D)
-
-#endif /* CONFIG_QS860T */
-
-/*** RPXCLASSIC *****************************************************/
-
-#ifdef CONFIG_RPXCLASSIC
-
-#ifdef CONFIG_FEC_ENET
-
-# define FEC_ENET /* use FEC for EThernet */
-# undef SCC_ENET
-
-#else /* ! CONFIG_FEC_ENET */
-
-/* Bits in parallel I/O port registers that have to be set/cleared
- * to configure the pins for SCC1 use.
- */
-#define PROFF_ENET PROFF_SCC1
-#define CPM_CR_ENET CPM_CR_CH_SCC1
-#define SCC_ENET 0
-#define PA_ENET_RXD ((ushort)0x0001)
-#define PA_ENET_TXD ((ushort)0x0002)
-#define PA_ENET_TCLK ((ushort)0x0200)
-#define PA_ENET_RCLK ((ushort)0x0800)
-#define PB_ENET_TENA ((uint)0x00001000)
-#define PC_ENET_CLSN ((ushort)0x0010)
-#define PC_ENET_RENA ((ushort)0x0020)
-
-/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
- * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
- */
-#define SICR_ENET_MASK ((uint)0x000000ff)
-#define SICR_ENET_CLKRT ((uint)0x0000003d)
-
-#endif /* CONFIG_FEC_ENET */
-
-#endif /* CONFIG_RPXCLASSIC */
-
-/*** RPXLITE ********************************************************/
-
-#ifdef CONFIG_RPXLITE
-/* This ENET stuff is for the MPC850 with ethernet on SCC2. Some of
- * this may be unique to the RPX-Lite configuration.
- * Note TENA is on Port B.
- */
-#define PROFF_ENET PROFF_SCC2
-#define CPM_CR_ENET CPM_CR_CH_SCC2
-#define SCC_ENET 1
-#define PA_ENET_RXD ((ushort)0x0004)
-#define PA_ENET_TXD ((ushort)0x0008)
-#define PA_ENET_TCLK ((ushort)0x0200)
-#define PA_ENET_RCLK ((ushort)0x0800)
-#if defined(CONFIG_RMU)
-#define PC_ENET_TENA ((uint)0x00000002) /* PC14 */
-#else
-#define PB_ENET_TENA ((uint)0x00002000)
-#endif
-#define PC_ENET_CLSN ((ushort)0x0040)
-#define PC_ENET_RENA ((ushort)0x0080)
-
-#define SICR_ENET_MASK ((uint)0x0000ff00)
-#define SICR_ENET_CLKRT ((uint)0x00003d00)
-#endif /* CONFIG_RPXLITE */
-
-/*** SM850 *********************************************************/
-
-/* The SM850 Service Module uses SCC2 for IrDA and SCC3 for Ethernet */
-
-#ifdef CONFIG_SM850
-#define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */
-#define CPM_CR_ENET CPM_CR_CH_SCC3
-#define SCC_ENET 2
-#define PB_ENET_RXD ((uint)0x00000004) /* PB 29 */
-#define PB_ENET_TXD ((uint)0x00000002) /* PB 30 */
-#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
-#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
-
-#define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */
-#define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */
-
-#define PC_ENET_RENA ((ushort)0x0800) /* PC 4 */
-#define PC_ENET_CLSN ((ushort)0x0400) /* PC 5 */
-
-/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
- * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero.
- */
-#define SICR_ENET_MASK ((uint)0x00FF0000)
-#define SICR_ENET_CLKRT ((uint)0x00260000)
-#endif /* CONFIG_SM850 */
-
-/*** SPD823TS ******************************************************/
-
-#ifdef CONFIG_SPD823TS
-/* Bits in parallel I/O port registers that have to be set/cleared
- * to configure the pins for SCC2 use.
- */
-#define PROFF_ENET PROFF_SCC2 /* Ethernet on SCC2 */
-#define CPM_CR_ENET CPM_CR_CH_SCC2
-#define SCC_ENET 1
-#define PA_ENET_MDC ((ushort)0x0001) /* PA 15 !!! */
-#define PA_ENET_MDIO ((ushort)0x0002) /* PA 14 !!! */
-#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
-#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
-#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
-#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
-
-#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
-
-#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
-#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
-#define PC_ENET_RESET ((ushort)0x0100) /* PC 7 !!! */
-
-/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
- * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
- */
-#define SICR_ENET_MASK ((uint)0x0000ff00)
-#define SICR_ENET_CLKRT ((uint)0x00002E00)
-#endif /* CONFIG_SPD823TS */
-
-/*** SXNI855T ******************************************************/
-
-#if defined(CONFIG_SXNI855T)
-
-#ifdef CONFIG_FEC_ENET
-#define FEC_ENET /* use FEC for Ethernet */
-#endif /* CONFIG_FEC_ETHERNET */
-
-#endif /* CONFIG_SXNI855T */
-
-/*** MVS1, TQM823L/M, TQM850L/M, TQM885D, ETX094, R360MPI **********/
-
-#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
- defined(CONFIG_R360MPI) || defined(CONFIG_RBC823) || \
- defined(CONFIG_TQM823L) || defined(CONFIG_TQM823M) || \
- defined(CONFIG_TQM850L) || defined(CONFIG_TQM850M) || \
- defined(CONFIG_TQM885D) || defined(CONFIG_ETX094) || \
- defined(CONFIG_RRVISION)|| defined(CONFIG_VIRTLAB2)|| \
- (defined(CONFIG_LANTEC) && CONFIG_LANTEC < 2)
-
-/* Bits in parallel I/O port registers that have to be set/cleared
- * to configure the pins for SCC2 use.
- */
-#define PROFF_ENET PROFF_SCC2
-#define CPM_CR_ENET CPM_CR_CH_SCC2
-#define SCC_ENET 1
-#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
-#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
-#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
-#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
-
-#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
-
-#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
-#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
-#if defined(CONFIG_R360MPI)
-#define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */
-#endif /* CONFIG_R360MPI */
-
-/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
- * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
- */
-#define SICR_ENET_MASK ((uint)0x0000ff00)
-#define SICR_ENET_CLKRT ((uint)0x00002600)
-
-# ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */
-#define FEC_ENET
-# endif /* CONFIG_FEC_ENET */
-
-#endif /* CONFIG_MVS v1, CONFIG_TQM823L/M, CONFIG_TQM850L/M, etc. */
-
-/*** TQM855L/M, TQM860L/M, TQM862L/M, TQM866L/M *********************/
-
-#if defined(CONFIG_TQM855L) || defined(CONFIG_TQM855M) || \
- defined(CONFIG_TQM860L) || defined(CONFIG_TQM860M) || \
- defined(CONFIG_TQM862L) || defined(CONFIG_TQM862M) || \
- defined(CONFIG_TQM866L) || defined(CONFIG_TQM866M)
-
-# ifdef CONFIG_SCC1_ENET /* use SCC for 10Mbps Ethernet */
-
-/* Bits in parallel I/O port registers that have to be set/cleared
- * to configure the pins for SCC1 use.
- */
-#define PROFF_ENET PROFF_SCC1
-#define CPM_CR_ENET CPM_CR_CH_SCC1
-#define SCC_ENET 0
-#define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
-#define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
-#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
-#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
-
-#define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
-#define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
-#define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
-
-/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
- * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
- */
-#define SICR_ENET_MASK ((uint)0x000000ff)
-#define SICR_ENET_CLKRT ((uint)0x00000026)
-
-# endif /* CONFIG_SCC1_ENET */
-
-# ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */
-
-#define FEC_ENET
-
-#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
-#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
-#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
-#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
-#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
-#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
-#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
-#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
-#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
-#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
-#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
-#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
-#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
-
-#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
-
-# endif /* CONFIG_FEC_ENET */
-#endif /* CONFIG_TQM855L/M, TQM860L/M, TQM862L/M */
-
-/*** V37 **********************************************************/
-
-#ifdef CONFIG_V37
-/* This ENET stuff is for the MPC823 with ethernet on SCC2. Some of
- * this may be unique to the Marel V37 configuration.
- * Note TENA is on Port B.
- */
-#define PROFF_ENET PROFF_SCC2
-#define CPM_CR_ENET CPM_CR_CH_SCC2
-#define SCC_ENET 1
-#define PA_ENET_RXD ((ushort)0x0004)
-#define PA_ENET_TXD ((ushort)0x0008)
-#define PA_ENET_TCLK ((ushort)0x0400)
-#define PA_ENET_RCLK ((ushort)0x0200)
-#define PB_ENET_TENA ((uint)0x00002000)
-#define PC_ENET_CLSN ((ushort)0x0040)
-#define PC_ENET_RENA ((ushort)0x0080)
-
-#define SICR_ENET_MASK ((uint)0x0000ff00)
-#define SICR_ENET_CLKRT ((uint)0x00002e00)
-#endif /* CONFIG_V37 */
-
-
-/*********************************************************************/
-
-/* SCC Event register as used by Ethernet.
-*/
-#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
-#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
-#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
-#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
-#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
-#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
-
-/* SCC Mode Register (PSMR) as used by Ethernet.
-*/
-#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
-#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
-#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
-#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
-#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
-#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
-#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
-#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
-#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
-#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
-#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
-#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
-#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
-
-/* Buffer descriptor control/status used by Ethernet receive.
-*/
-#define BD_ENET_RX_EMPTY ((ushort)0x8000)
-#define BD_ENET_RX_WRAP ((ushort)0x2000)
-#define BD_ENET_RX_INTR ((ushort)0x1000)
-#define BD_ENET_RX_LAST ((ushort)0x0800)
-#define BD_ENET_RX_FIRST ((ushort)0x0400)
-#define BD_ENET_RX_MISS ((ushort)0x0100)
-#define BD_ENET_RX_LG ((ushort)0x0020)
-#define BD_ENET_RX_NO ((ushort)0x0010)
-#define BD_ENET_RX_SH ((ushort)0x0008)
-#define BD_ENET_RX_CR ((ushort)0x0004)
-#define BD_ENET_RX_OV ((ushort)0x0002)
-#define BD_ENET_RX_CL ((ushort)0x0001)
-#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
-
-/* Buffer descriptor control/status used by Ethernet transmit.
-*/
-#define BD_ENET_TX_READY ((ushort)0x8000)
-#define BD_ENET_TX_PAD ((ushort)0x4000)
-#define BD_ENET_TX_WRAP ((ushort)0x2000)
-#define BD_ENET_TX_INTR ((ushort)0x1000)
-#define BD_ENET_TX_LAST ((ushort)0x0800)
-#define BD_ENET_TX_TC ((ushort)0x0400)
-#define BD_ENET_TX_DEF ((ushort)0x0200)
-#define BD_ENET_TX_HB ((ushort)0x0100)
-#define BD_ENET_TX_LC ((ushort)0x0080)
-#define BD_ENET_TX_RL ((ushort)0x0040)
-#define BD_ENET_TX_RCMASK ((ushort)0x003c)
-#define BD_ENET_TX_UN ((ushort)0x0002)
-#define BD_ENET_TX_CSL ((ushort)0x0001)
-#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
-
-/* SCC as UART
-*/
-typedef struct scc_uart {
- sccp_t scc_genscc;
- uint scc_res1; /* Reserved */
- uint scc_res2; /* Reserved */
- ushort scc_maxidl; /* Maximum idle chars */
- ushort scc_idlc; /* temp idle counter */
- ushort scc_brkcr; /* Break count register */
- ushort scc_parec; /* receive parity error counter */
- ushort scc_frmec; /* receive framing error counter */
- ushort scc_nosec; /* receive noise counter */
- ushort scc_brkec; /* receive break condition counter */
- ushort scc_brkln; /* last received break length */
- ushort scc_uaddr1; /* UART address character 1 */
- ushort scc_uaddr2; /* UART address character 2 */
- ushort scc_rtemp; /* Temp storage */
- ushort scc_toseq; /* Transmit out of sequence char */
- ushort scc_char1; /* control character 1 */
- ushort scc_char2; /* control character 2 */
- ushort scc_char3; /* control character 3 */
- ushort scc_char4; /* control character 4 */
- ushort scc_char5; /* control character 5 */
- ushort scc_char6; /* control character 6 */
- ushort scc_char7; /* control character 7 */
- ushort scc_char8; /* control character 8 */
- ushort scc_rccm; /* receive control character mask */
- ushort scc_rccr; /* receive control character register */
- ushort scc_rlbc; /* receive last break character */
-} scc_uart_t;
-
-/* SCC Event and Mask registers when it is used as a UART.
-*/
-#define UART_SCCM_GLR ((ushort)0x1000)
-#define UART_SCCM_GLT ((ushort)0x0800)
-#define UART_SCCM_AB ((ushort)0x0200)
-#define UART_SCCM_IDL ((ushort)0x0100)
-#define UART_SCCM_GRA ((ushort)0x0080)
-#define UART_SCCM_BRKE ((ushort)0x0040)
-#define UART_SCCM_BRKS ((ushort)0x0020)
-#define UART_SCCM_CCR ((ushort)0x0008)
-#define UART_SCCM_BSY ((ushort)0x0004)
-#define UART_SCCM_TX ((ushort)0x0002)
-#define UART_SCCM_RX ((ushort)0x0001)
-
-/* The SCC PSMR when used as a UART.
-*/
-#define SCU_PSMR_FLC ((ushort)0x8000)
-#define SCU_PSMR_SL ((ushort)0x4000)
-#define SCU_PSMR_CL ((ushort)0x3000)
-#define SCU_PSMR_UM ((ushort)0x0c00)
-#define SCU_PSMR_FRZ ((ushort)0x0200)
-#define SCU_PSMR_RZS ((ushort)0x0100)
-#define SCU_PSMR_SYN ((ushort)0x0080)
-#define SCU_PSMR_DRT ((ushort)0x0040)
-#define SCU_PSMR_PEN ((ushort)0x0010)
-#define SCU_PSMR_RPM ((ushort)0x000c)
-#define SCU_PSMR_REVP ((ushort)0x0008)
-#define SCU_PSMR_TPM ((ushort)0x0003)
-#define SCU_PSMR_TEVP ((ushort)0x0003)
-
-/* CPM Transparent mode SCC.
- */
-typedef struct scc_trans {
- sccp_t st_genscc;
- uint st_cpres; /* Preset CRC */
- uint st_cmask; /* Constant mask for CRC */
-} scc_trans_t;
-
-#define BD_SCC_TX_LAST ((ushort)0x0800)
-
-/* IIC parameter RAM.
-*/
-typedef struct iic {
- ushort iic_rbase; /* Rx Buffer descriptor base address */
- ushort iic_tbase; /* Tx Buffer descriptor base address */
- u_char iic_rfcr; /* Rx function code */
- u_char iic_tfcr; /* Tx function code */
- ushort iic_mrblr; /* Max receive buffer length */
- uint iic_rstate; /* Internal */
- uint iic_rdp; /* Internal */
- ushort iic_rbptr; /* Internal */
- ushort iic_rbc; /* Internal */
- uint iic_rxtmp; /* Internal */
- uint iic_tstate; /* Internal */
- uint iic_tdp; /* Internal */
- ushort iic_tbptr; /* Internal */
- ushort iic_tbc; /* Internal */
- uint iic_txtmp; /* Internal */
- uint iic_res; /* reserved */
- ushort iic_rpbase; /* Relocation pointer */
- ushort iic_res2; /* reserved */
-} iic_t;
-
-/* SPI parameter RAM.
-*/
-typedef struct spi {
- ushort spi_rbase; /* Rx Buffer descriptor base address */
- ushort spi_tbase; /* Tx Buffer descriptor base address */
- u_char spi_rfcr; /* Rx function code */
- u_char spi_tfcr; /* Tx function code */
- ushort spi_mrblr; /* Max receive buffer length */
- uint spi_rstate; /* Internal */
- uint spi_rdp; /* Internal */
- ushort spi_rbptr; /* Internal */
- ushort spi_rbc; /* Internal */
- uint spi_rxtmp; /* Internal */
- uint spi_tstate; /* Internal */
- uint spi_tdp; /* Internal */
- ushort spi_tbptr; /* Internal */
- ushort spi_tbc; /* Internal */
- uint spi_txtmp; /* Internal */
- uint spi_res;
- ushort spi_rpbase; /* Relocation pointer */
- ushort spi_res2;
-} spi_t;
-
-/* SPI Mode register.
-*/
-#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
-#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
-#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
-#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
-#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
-#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
-#define SPMODE_EN ((ushort)0x0100) /* Enable */
-#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
-#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
-
-#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4)
-#define SPMODE_PM(x) ((x) &0xF)
-
-/* HDLC parameter RAM.
-*/
-
-typedef struct hdlc_pram_s {
- /*
- * SCC parameter RAM
- */
- ushort rbase; /* Rx Buffer descriptor base address */
- ushort tbase; /* Tx Buffer descriptor base address */
- uchar rfcr; /* Rx function code */
- uchar tfcr; /* Tx function code */
- ushort mrblr; /* Rx buffer length */
- ulong rstate; /* Rx internal state */
- ulong rptr; /* Rx internal data pointer */
- ushort rbptr; /* rb BD Pointer */
- ushort rcount; /* Rx internal byte count */
- ulong rtemp; /* Rx temp */
- ulong tstate; /* Tx internal state */
- ulong tptr; /* Tx internal data pointer */
- ushort tbptr; /* Tx BD pointer */
- ushort tcount; /* Tx byte count */
- ulong ttemp; /* Tx temp */
- ulong rcrc; /* temp receive CRC */
- ulong tcrc; /* temp transmit CRC */
- /*
- * HDLC specific parameter RAM
- */
- uchar res[4]; /* reserved */
- ulong c_mask; /* CRC constant */
- ulong c_pres; /* CRC preset */
- ushort disfc; /* discarded frame counter */
- ushort crcec; /* CRC error counter */
- ushort abtsc; /* abort sequence counter */
- ushort nmarc; /* nonmatching address rx cnt */
- ushort retrc; /* frame retransmission cnt */
- ushort mflr; /* maximum frame length reg */
- ushort max_cnt; /* maximum length counter */
- ushort rfthr; /* received frames threshold */
- ushort rfcnt; /* received frames count */
- ushort hmask; /* user defined frm addr mask */
- ushort haddr1; /* user defined frm address 1 */
- ushort haddr2; /* user defined frm address 2 */
- ushort haddr3; /* user defined frm address 3 */
- ushort haddr4; /* user defined frm address 4 */
- ushort tmp; /* temp */
- ushort tmp_mb; /* temp */
-} hdlc_pram_t;
-
-/* CPM interrupts. There are nearly 32 interrupts generated by CPM
- * channels or devices. All of these are presented to the PPC core
- * as a single interrupt. The CPM interrupt handler dispatches its
- * own handlers, in a similar fashion to the PPC core handler. We
- * use the table as defined in the manuals (i.e. no special high
- * priority and SCC1 == SCCa, etc...).
- */
-#define CPMVEC_NR 32
-#define CPMVEC_OFFSET 0x00010000
-#define CPMVEC_PIO_PC15 ((ushort)0x1f | CPMVEC_OFFSET)
-#define CPMVEC_SCC1 ((ushort)0x1e | CPMVEC_OFFSET)
-#define CPMVEC_SCC2 ((ushort)0x1d | CPMVEC_OFFSET)
-#define CPMVEC_SCC3 ((ushort)0x1c | CPMVEC_OFFSET)
-#define CPMVEC_SCC4 ((ushort)0x1b | CPMVEC_OFFSET)
-#define CPMVEC_PIO_PC14 ((ushort)0x1a | CPMVEC_OFFSET)
-#define CPMVEC_TIMER1 ((ushort)0x19 | CPMVEC_OFFSET)
-#define CPMVEC_PIO_PC13 ((ushort)0x18 | CPMVEC_OFFSET)
-#define CPMVEC_PIO_PC12 ((ushort)0x17 | CPMVEC_OFFSET)
-#define CPMVEC_SDMA_CB_ERR ((ushort)0x16 | CPMVEC_OFFSET)
-#define CPMVEC_IDMA1 ((ushort)0x15 | CPMVEC_OFFSET)
-#define CPMVEC_IDMA2 ((ushort)0x14 | CPMVEC_OFFSET)
-#define CPMVEC_TIMER2 ((ushort)0x12 | CPMVEC_OFFSET)
-#define CPMVEC_RISCTIMER ((ushort)0x11 | CPMVEC_OFFSET)
-#define CPMVEC_I2C ((ushort)0x10 | CPMVEC_OFFSET)
-#define CPMVEC_PIO_PC11 ((ushort)0x0f | CPMVEC_OFFSET)
-#define CPMVEC_PIO_PC10 ((ushort)0x0e | CPMVEC_OFFSET)
-#define CPMVEC_TIMER3 ((ushort)0x0c | CPMVEC_OFFSET)
-#define CPMVEC_PIO_PC9 ((ushort)0x0b | CPMVEC_OFFSET)
-#define CPMVEC_PIO_PC8 ((ushort)0x0a | CPMVEC_OFFSET)
-#define CPMVEC_PIO_PC7 ((ushort)0x09 | CPMVEC_OFFSET)
-#define CPMVEC_TIMER4 ((ushort)0x07 | CPMVEC_OFFSET)
-#define CPMVEC_PIO_PC6 ((ushort)0x06 | CPMVEC_OFFSET)
-#define CPMVEC_SPI ((ushort)0x05 | CPMVEC_OFFSET)
-#define CPMVEC_SMC1 ((ushort)0x04 | CPMVEC_OFFSET)
-#define CPMVEC_SMC2 ((ushort)0x03 | CPMVEC_OFFSET)
-#define CPMVEC_PIO_PC5 ((ushort)0x02 | CPMVEC_OFFSET)
-#define CPMVEC_PIO_PC4 ((ushort)0x01 | CPMVEC_OFFSET)
-#define CPMVEC_ERROR ((ushort)0x00 | CPMVEC_OFFSET)
-
-extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
-
-/* CPM interrupt configuration vector.
-*/
-#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
-#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
-#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
-#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
-#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */
-#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
-#define CICR_IEN ((uint)0x00000080) /* Int. enable */
-#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
-#endif /* __CPM_8XX__ */
diff --git a/include/dtt.h b/include/dtt.h
deleted file mode 100644
index a17aa67703..0000000000
--- a/include/dtt.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * (C) Copyright 2001
- * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Digital Thermometers and Thermostats.
- */
-#ifndef _DTT_H_
-#define _DTT_H_
-
-#if defined(CONFIG_DTT_LM75) || \
- defined(CONFIG_DTT_DS1621) || \
- defined(CONFIG_DTT_ADM1021)
-
-#define CONFIG_DTT /* We have a DTT */
-
-#ifndef CONFIG_DTT_ADM1021
-#define DTT_COMMERCIAL_MAX_TEMP 70 /* 0 - +70 C */
-#define DTT_INDUSTRIAL_MAX_TEMP 85 /* -40 - +85 C */
-#define DTT_AUTOMOTIVE_MAX_TEMP 105 /* -40 - +105 C */
-#ifndef CFG_DTT_MAX_TEMP
-#define CFG_DTT_MAX_TEMP DTT_COMMERCIAL_MAX_TEMP
-#endif
-#ifndef CFG_DTT_HYSTERESIS
-#define CFG_DTT_HYSTERESIS 5 /* 5 C */
-#endif
-#endif /* CONFIG_DTT_ADM1021 */
-
-extern int dtt_init (void);
-extern int dtt_read(int sensor, int reg);
-extern int dtt_write(int sensor, int reg, int val);
-extern int dtt_get_temp(int sensor);
-#endif
-
-#if defined(CONFIG_DTT_LM75)
-#define DTT_READ_TEMP 0x0
-#define DTT_CONFIG 0x1
-#define DTT_TEMP_HYST 0x2
-#define DTT_TEMP_SET 0x3
-#endif
-
-#if defined(CONFIG_DTT_DS1621)
-#define DTT_READ_TEMP 0xAA
-#define DTT_READ_COUNTER 0xA8
-#define DTT_READ_SLOPE 0xA9
-#define DTT_WRITE_START_CONV 0xEE
-#define DTT_WRITE_STOP_CONV 0x22
-#define DTT_TEMP_HIGH 0xA1
-#define DTT_TEMP_LOW 0xA2
-#define DTT_CONFIG 0xAC
-#endif
-
-#if defined(CONFIG_DTT_ADM1021)
-#define DTT_READ_LOC_VALUE 0x00
-#define DTT_READ_REM_VALUE 0x01
-#define DTT_READ_STATUS 0x02
-#define DTT_READ_CONFIG 0x03
-#define DTT_READ_CONVRATE 0x04
-#define DTT_READ_LOC_HIGHLIM 0x05
-#define DTT_READ_LOC_LOWLIM 0x06
-#define DTT_READ_REM_HIGHLIM 0x07
-#define DTT_READ_REM_LOWLIM 0x08
-#define DTT_READ_DEVID 0xfe
-
-#define DTT_WRITE_CONFIG 0x09
-#define DTT_WRITE_CONVRATE 0x0a
-#define DTT_WRITE_LOC_HIGHLIM 0x0b
-#define DTT_WRITE_LOC_LOWLIM 0x0c
-#define DTT_WRITE_REM_HIGHLIM 0x0d
-#define DTT_WRITE_REM_LOWLIM 0x0e
-#define DTT_WRITE_ONESHOT 0x0f
-
-#define DTT_STATUS_BUSY 0x80 /* 1=ADC Converting */
-#define DTT_STATUS_LHIGH 0x40 /* 1=Local High Temp Limit Tripped */
-#define DTT_STATUS_LLOW 0x20 /* 1=Local Low Temp Limit Tripped */
-#define DTT_STATUS_RHIGH 0x10 /* 1=Remote High Temp Limit Tripped */
-#define DTT_STATUS_RLOW 0x08 /* 1=Remote Low Temp Limit Tripped */
-#define DTT_STATUS_OPEN 0x04 /* 1=Remote Sensor Open-Circuit */
-
-#define DTT_CONFIG_ALERT_MASKED 0x80 /* 0=ALERT Enabled, 1=ALERT Masked */
-#define DTT_CONFIG_STANDBY 0x40 /* 0=Run, 1=Standby */
-
-#define DTT_ADM1021_DEVID 0x41
-#endif
-
-#endif /* _DTT_H_ */
diff --git a/include/fdc.h b/include/fdc.h
deleted file mode 100644
index b66f20212b..0000000000
--- a/include/fdc.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * (C) Copyright 2002
- * Stäubli Faverges - <www.staubli.com>
- * Pierre AUBERT p.aubert@staubli.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _FDC_H_
-#define _FDC_H_
-
-/* Functions prototype */
-int fdc_fdos_init (int drive);
-int fdc_fdos_seek (int where);
-int fdc_fdos_read (void *buffer, int len);
-
-int dos_open(char *name);
-int dos_read (ulong addr);
-int dos_dir (void);
-
-#endif
diff --git a/include/i2c.h b/include/i2c.h
deleted file mode 100644
index 9f4c582230..0000000000
--- a/include/i2c.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * (C) Copyright 2001
- * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * The original I2C interface was
- * (C) 2000 by Paolo Scaffardi (arsenio@tin.it)
- * AIRVENT SAM s.p.a - RIMINI(ITALY)
- * but has been changed substantially.
- */
-
-#ifndef _I2C_H_
-#define _I2C_H_
-
-/*
- * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING
- *
- * The implementation MUST NOT use static or global variables if the
- * I2C routines are used to read SDRAM configuration information
- * because this is done before the memories are initialized. Limited
- * use of stack-based variables are OK (the initial stack size is
- * limited).
- *
- * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING
- */
-
-/*
- * Configuration items.
- */
-#define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */
-
-/*
- * Initialization, must be called once on start up, may be called
- * repeatedly to change the speed and slave addresses.
- */
-#ifdef CFG_I2C_INIT_BOARD
-void i2c_init_board(void);
-#endif
-
-/*
- * Probe the given I2C chip address. Returns 0 if a chip responded,
- * not 0 on failure.
- */
-int i2c_probe(uchar chip);
-
-/*
- * Read/Write interface:
- * chip: I2C chip address, range 0..127
- * addr: Memory (register) address within the chip
- * alen: Number of bytes to use for addr (typically 1, 2 for larger
- * memories, 0 for register type devices with only one
- * register)
- * buffer: Where to read/write the data
- * len: How many bytes to read/write
- *
- * Returns: 0 on success, not 0 on failure
- */
-int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len);
-int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len);
-
-/*
- * Utility routines to read/write registers.
- */
-uchar i2c_reg_read (uchar chip, uchar reg);
-void i2c_reg_write(uchar chip, uchar reg, uchar val);
-
-/*
- * Functions for setting the current I2C bus and its speed
- */
-
-/*
- * i2c_set_bus_num:
- *
- * Change the active I2C bus. Subsequent read/write calls will
- * go to this one.
- *
- * bus - bus index, zero based
- *
- * Returns: 0 on success, not 0 on failure
- *
- */
-int i2c_set_bus_num(unsigned int bus);
-
-/*
- * i2c_get_bus_num:
- *
- * Returns index of currently active I2C bus. Zero-based.
- */
-
-unsigned int i2c_get_bus_num(void);
-
-/*
- * i2c_set_bus_speed:
- *
- * Change the speed of the active I2C bus
- *
- * speed - bus speed in Hz
- *
- * Returns: 0 on success, not 0 on failure
- *
- */
-int i2c_set_bus_speed(unsigned int);
-
-/*
- * i2c_get_bus_speed:
- *
- * Returns speed of currently active I2C bus in Hz
- */
-
-unsigned int i2c_get_bus_speed(void);
-
-#endif /* _I2C_H_ */
diff --git a/include/i8042.h b/include/i8042.h
deleted file mode 100644
index f77239fdde..0000000000
--- a/include/i8042.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * (C) Copyright 2002 ELTEC Elektronik AG
- * Frank Gottschling <fgottschling@eltec.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* i8042.h - Intel 8042 keyboard driver header */
-
-#ifndef _I8042_H_
-#define _I8042_H_
-
-#ifdef __I386__
-#include <common.h>
-#include <asm/io.h>
-#define in8(p) inb(p)
-#define out8(p,v) outb(v,p)
-#endif
-
-/* defines */
-
-#define I8042_DATA_REG (CFG_ISA_IO + 0x0060) /* keyboard i/o buffer */
-#define I8042_STATUS_REG (CFG_ISA_IO + 0x0064) /* keyboard status read */
-#define I8042_COMMAND_REG (CFG_ISA_IO + 0x0064) /* keyboard ctrl write */
-
-#define KBD_US 0 /* default US layout */
-#define KBD_GER 1 /* german layout */
-
-#define KBD_TIMEOUT 1000 /* 1 sec */
-#define KBD_RESET_TRIES 3
-
-#define AS 0 /* normal character index */
-#define SH 1 /* shift index */
-#define CN 2 /* control index */
-#define NM 3 /* numeric lock index */
-#define AK 4 /* right alt key */
-#define CP 5 /* capslock index */
-#define ST 6 /* stop output index */
-#define EX 7 /* extended code index */
-#define ES 8 /* escape and extended code index */
-
-#define NORMAL 0x0000 /* normal key */
-#define STP 0x0001 /* scroll lock stop output*/
-#define NUM 0x0002 /* numeric lock */
-#define CAPS 0x0004 /* capslock */
-#define SHIFT 0x0008 /* shift */
-#define CTRL 0x0010 /* control*/
-#define EXT 0x0020 /* extended scan code 0xe0 */
-#define ESC 0x0040 /* escape key press */
-#define E1 0x0080 /* extended scan code 0xe1 */
-#define BRK 0x0100 /* make break flag for keyboard */
-#define ALT 0x0200 /* right alt */
-
-/* exports */
-
-int i8042_kbd_init(void);
-int i8042_tstc(void);
-int i8042_getc(void);
-
-#endif /* _I8042_H_ */
diff --git a/include/ide.h b/include/ide.h
deleted file mode 100644
index dfef32f267..0000000000
--- a/include/ide.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _IDE_H
-#define _IDE_H
-
-#define IDE_BUS(dev) (dev >> 1)
-
-#ifdef CONFIG_IDE_LED
-
-/*
- * LED Port
- */
-#define LED_PORT ((uchar *)(PER8_BASE + 0x3000))
-#define LED_IDE1 0x01
-#define LED_IDE2 0x02
-#define DEVICE_LED(d) ((d & 2) | ((d & 2) == 0)) /* depends on bit positions! */
-
-#endif /* CONFIG_IDE_LED */
-
-#ifdef CFG_64BIT_LBA
-typedef uint64_t lbaint_t;
-#else
-typedef ulong lbaint_t;
-#endif
-
-/*
- * Function Prototypes
- */
-
-void ide_init (void);
-ulong ide_read (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer);
-ulong ide_write (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer);
-
-#endif /* _IDE_H */
diff --git a/include/jffs2/jffs2.h b/include/jffs2/jffs2.h
deleted file mode 100644
index d142cd1bce..0000000000
--- a/include/jffs2/jffs2.h
+++ /dev/null
@@ -1,218 +0,0 @@
-/*
- * JFFS2 -- Journalling Flash File System, Version 2.
- *
- * Copyright (C) 2001 Red Hat, Inc.
- *
- * Created by David Woodhouse <dwmw2@cambridge.redhat.com>
- *
- * The original JFFS, from which the design for JFFS2 was derived,
- * was designed and implemented by Axis Communications AB.
- *
- * The contents of this file are subject to the Red Hat eCos Public
- * License Version 1.1 (the "Licence"); you may not use this file
- * except in compliance with the Licence. You may obtain a copy of
- * the Licence at http://www.redhat.com/
- *
- * Software distributed under the Licence is distributed on an "AS IS"
- * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.
- * See the Licence for the specific language governing rights and
- * limitations under the Licence.
- *
- * The Original Code is JFFS2 - Journalling Flash File System, version 2
- *
- * Alternatively, the contents of this file may be used under the
- * terms of the GNU General Public License version 2 (the "GPL"), in
- * which case the provisions of the GPL are applicable instead of the
- * above. If you wish to allow the use of your version of this file
- * only under the terms of the GPL and not to allow others to use your
- * version of this file under the RHEPL, indicate your decision by
- * deleting the provisions above and replace them with the notice and
- * other provisions required by the GPL. If you do not delete the
- * provisions above, a recipient may use your version of this file
- * under either the RHEPL or the GPL.
- *
- * $Id: jffs2.h,v 1.2 2002/01/17 00:53:20 nyet Exp $
- *
- */
-
-#ifndef __LINUX_JFFS2_H__
-#define __LINUX_JFFS2_H__
-
-#include <asm/types.h>
-#include <jffs2/load_kernel.h>
-
-#define JFFS2_SUPER_MAGIC 0x72b6
-
-/* Values we may expect to find in the 'magic' field */
-#define JFFS2_OLD_MAGIC_BITMASK 0x1984
-#define JFFS2_MAGIC_BITMASK 0x1985
-#define KSAMTIB_CIGAM_2SFFJ 0x5981 /* For detecting wrong-endian fs */
-#define JFFS2_EMPTY_BITMASK 0xffff
-#define JFFS2_DIRTY_BITMASK 0x0000
-
-/* We only allow a single char for length, and 0xFF is empty flash so
- we don't want it confused with a real length. Hence max 254.
-*/
-#define JFFS2_MAX_NAME_LEN 254
-
-/* How small can we sensibly write nodes? */
-#define JFFS2_MIN_DATA_LEN 128
-
-#define JFFS2_COMPR_NONE 0x00
-#define JFFS2_COMPR_ZERO 0x01
-#define JFFS2_COMPR_RTIME 0x02
-#define JFFS2_COMPR_RUBINMIPS 0x03
-#define JFFS2_COMPR_COPY 0x04
-#define JFFS2_COMPR_DYNRUBIN 0x05
-#define JFFS2_COMPR_ZLIB 0x06
-#if defined(CONFIG_JFFS2_LZO_LZARI)
-#define JFFS2_COMPR_LZO 0x07
-#define JFFS2_COMPR_LZARI 0x08
-#define JFFS2_NUM_COMPR 9
-#else
-#define JFFS2_NUM_COMPR 7
-#endif
-
-/* Compatibility flags. */
-#define JFFS2_COMPAT_MASK 0xc000 /* What do to if an unknown nodetype is found */
-#define JFFS2_NODE_ACCURATE 0x2000
-/* INCOMPAT: Fail to mount the filesystem */
-#define JFFS2_FEATURE_INCOMPAT 0xc000
-/* ROCOMPAT: Mount read-only */
-#define JFFS2_FEATURE_ROCOMPAT 0x8000
-/* RWCOMPAT_COPY: Mount read/write, and copy the node when it's GC'd */
-#define JFFS2_FEATURE_RWCOMPAT_COPY 0x4000
-/* RWCOMPAT_DELETE: Mount read/write, and delete the node when it's GC'd */
-#define JFFS2_FEATURE_RWCOMPAT_DELETE 0x0000
-
-#define JFFS2_NODETYPE_DIRENT (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 1)
-#define JFFS2_NODETYPE_INODE (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 2)
-#define JFFS2_NODETYPE_CLEANMARKER (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 3)
-#define JFFS2_NODETYPE_PADDING (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 4)
-
-/* Maybe later... */
-/*#define JFFS2_NODETYPE_CHECKPOINT (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 3) */
-/*#define JFFS2_NODETYPE_OPTIONS (JFFS2_FEATURE_RWCOMPAT_COPY | JFFS2_NODE_ACCURATE | 4) */
-
-/* Same as the non_ECC versions, but with extra space for real
- * ECC instead of just the checksum. For use on NAND flash
- */
-/*#define JFFS2_NODETYPE_DIRENT_ECC (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 5) */
-/*#define JFFS2_NODETYPE_INODE_ECC (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 6) */
-
-#define JFFS2_INO_FLAG_PREREAD 1 /* Do read_inode() for this one at
- mount time, don't wait for it to
- happen later */
-#define JFFS2_INO_FLAG_USERCOMPR 2 /* User has requested a specific
- compression type */
-
-
-struct jffs2_unknown_node
-{
- /* All start like this */
- __u16 magic;
- __u16 nodetype;
- __u32 totlen; /* So we can skip over nodes we don't grok */
- __u32 hdr_crc;
-} __attribute__((packed));
-
-struct jffs2_raw_dirent
-{
- __u16 magic;
- __u16 nodetype; /* == JFFS_NODETYPE_DIRENT */
- __u32 totlen;
- __u32 hdr_crc;
- __u32 pino;
- __u32 version;
- __u32 ino; /* == zero for unlink */
- __u32 mctime;
- __u8 nsize;
- __u8 type;
- __u8 unused[2];
- __u32 node_crc;
- __u32 name_crc;
- __u8 name[0];
-} __attribute__((packed));
-
-/* The JFFS2 raw inode structure: Used for storage on physical media. */
-/* The uid, gid, atime, mtime and ctime members could be longer, but
- are left like this for space efficiency. If and when people decide
- they really need them extended, it's simple enough to add support for
- a new type of raw node.
-*/
-struct jffs2_raw_inode
-{
- __u16 magic; /* A constant magic number. */
- __u16 nodetype; /* == JFFS_NODETYPE_INODE */
- __u32 totlen; /* Total length of this node (inc data, etc.) */
- __u32 hdr_crc;
- __u32 ino; /* Inode number. */
- __u32 version; /* Version number. */
- __u32 mode; /* The file's type or mode. */
- __u16 uid; /* The file's owner. */
- __u16 gid; /* The file's group. */
- __u32 isize; /* Total resultant size of this inode (used for truncations) */
- __u32 atime; /* Last access time. */
- __u32 mtime; /* Last modification time. */
- __u32 ctime; /* Change time. */
- __u32 offset; /* Where to begin to write. */
- __u32 csize; /* (Compressed) data size */
- __u32 dsize; /* Size of the node's data. (after decompression) */
- __u8 compr; /* Compression algorithm used */
- __u8 usercompr; /* Compression algorithm requested by the user */
- __u16 flags; /* See JFFS2_INO_FLAG_* */
- __u32 data_crc; /* CRC for the (compressed) data. */
- __u32 node_crc; /* CRC for the raw inode (excluding data) */
-/* __u8 data[dsize]; */
-} __attribute__((packed));
-
-union jffs2_node_union {
- struct jffs2_raw_inode i;
- struct jffs2_raw_dirent d;
- struct jffs2_unknown_node u;
-} __attribute__((packed));
-
-enum
- {
- DT_UNKNOWN = 0,
-# define DT_UNKNOWN DT_UNKNOWN
- DT_FIFO = 1,
-# define DT_FIFO DT_FIFO
- DT_CHR = 2,
-# define DT_CHR DT_CHR
- DT_DIR = 4,
-# define DT_DIR DT_DIR
- DT_BLK = 6,
-# define DT_BLK DT_BLK
- DT_REG = 8,
-# define DT_REG DT_REG
- DT_LNK = 10,
-# define DT_LNK DT_LNK
- DT_SOCK = 12,
-# define DT_SOCK DT_SOCK
- DT_WHT = 14
-# define DT_WHT DT_WHT
- };
-
-
-u32 jffs2_1pass_ls(struct part_info *part,const char *fname);
-u32 jffs2_1pass_load(char *dest, struct part_info *part,const char *fname);
-u32 jffs2_1pass_info(struct part_info *part);
-
-void rtime_decompress(unsigned char *data_in, unsigned char *cpage_out,
- u32 srclen, u32 destlen);
-void rubin_do_decompress(unsigned char *bits, unsigned char *in,
- unsigned char *page_out, __u32 destlen);
-void dynrubin_decompress(unsigned char *data_in, unsigned char *cpage_out,
- unsigned long sourcelen, unsigned long dstlen);
-long zlib_decompress(unsigned char *data_in, unsigned char *cpage_out,
- __u32 srclen, __u32 destlen);
-#if defined(CONFIG_JFFS2_LZO_LZARI)
-int lzo_decompress(unsigned char *data_in, unsigned char *cpage_out,
- u32 srclen, u32 destlen);
-int lzari_decompress(unsigned char *data_in, unsigned char *cpage_out,
- u32 srclen, u32 destlen);
-#endif
-
-char *mkmodestr(unsigned long mode, char *str);
-#endif /* __LINUX_JFFS2_H__ */
diff --git a/include/jffs2/load_kernel.h b/include/jffs2/load_kernel.h
deleted file mode 100644
index 882a80ea3a..0000000000
--- a/include/jffs2/load_kernel.h
+++ /dev/null
@@ -1,73 +0,0 @@
-#ifndef load_kernel_h
-#define load_kernel_h
-/*-------------------------------------------------------------------------
- * Filename: load_kernel.h
- * Version: $Id: load_kernel.h,v 1.3 2002/01/25 01:34:11 nyet Exp $
- * Copyright: Copyright (C) 2001, Russ Dill
- * Author: Russ Dill <Russ.Dill@asu.edu>
- * Description: header for load kernel modules
- *-----------------------------------------------------------------------*/
-/*
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-
-#include <linux/list.h>
-
-/* mtd device types */
-#define MTD_DEV_TYPE_NOR 0x0001
-#define MTD_DEV_TYPE_NAND 0x0002
-#define MTD_DEV_TYPE(type) ((type == MTD_DEV_TYPE_NAND) ? "nand" : "nor")
-
-struct mtd_device {
- struct list_head link;
- struct mtdids *id; /* parent mtd id entry */
- u16 num_parts; /* number of partitions on this device */
- struct list_head parts; /* partitions */
-};
-
-struct part_info {
- struct list_head link;
- char *name; /* partition name */
- u8 auto_name; /* set to 1 for generated name */
- u32 size; /* total size of the partition */
- u32 offset; /* offset within device */
- void *jffs2_priv; /* used internaly by jffs2 */
- u32 mask_flags; /* kernel MTD mask flags */
- struct mtd_device *dev; /* parent device */
-};
-
-struct mtdids {
- struct list_head link;
- u8 type; /* device type */
- u8 num; /* device number */
- u32 size; /* device size */
- char *mtd_id; /* linux kernel device id */
-};
-
-#define ldr_strlen strlen
-#define ldr_strncmp strncmp
-#define ldr_memcpy memcpy
-#define putstr(x) printf("%s", x)
-#define mmalloc malloc
-#define UDEBUG printf
-
-#define putnstr(str, size) printf("%*.*s", size, size, str)
-#define ldr_output_string(x) puts(x)
-#define putLabeledWord(x, y) printf("%s %08x\n", x, (unsigned int)y)
-#define led_blink(x, y, z, a)
-
-#endif /* load_kernel_h */
diff --git a/include/linux_logo.h b/include/linux_logo.h
deleted file mode 100644
index 9aa712eb4e..0000000000
--- a/include/linux_logo.h
+++ /dev/null
@@ -1,1445 +0,0 @@
-/* $Id: linux_logo.h,v 1.5 1998/07/30 16:30:58 jj Exp $
- * include/linux/linux_logo.h: This is a linux logo
- * to be displayed on boot.
- *
- * Copyright (C) 1996 Larry Ewing (lewing@isc.tamu.edu)
- * Copyright (C) 1996,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
- *
- * You can put anything here, but:
- * LINUX_LOGO_COLORS has to be less than 224
- * image size has to be 80x80
- * values have to start from 0x20
- * (i.e. RGB(linux_logo_red[0],
- * linux_logo_green[0],
- * linux_logo_blue[0]) is color 0x20)
- * BW image has to be 80x80 as well, with MS bit
- * on the left
- * Serial_console ascii image can be any size,
- * but should contain %s to display the version
- */
-
-#if LINUX_LOGO_COLORS == 214
-
-unsigned char linux_logo_red[] __initdata = {
- 0x02, 0x9E, 0xE9, 0xC4, 0x50, 0xC9, 0xC4, 0xE9,
- 0x65, 0xE3, 0xC2, 0x25, 0xA4, 0xEC, 0x90, 0xA6,
- 0xC4, 0x6A, 0xD1, 0xF3, 0x12, 0xED, 0xA0, 0xC2,
- 0xB8, 0xD5, 0xDB, 0xD2, 0x3E, 0x16, 0xEB, 0x54,
- 0xA9, 0xCD, 0xF5, 0x0A, 0xBA, 0xB3, 0xDC, 0x74,
- 0xCE, 0xF6, 0xD3, 0xC5, 0xEA, 0xB8, 0xED, 0x5E,
- 0xE5, 0x26, 0xF4, 0xA9, 0x82, 0x94, 0xE6, 0x38,
- 0xF2, 0x0F, 0x7F, 0x49, 0xE5, 0xF4, 0xD3, 0xC3,
- 0xC2, 0x1E, 0xD5, 0xC6, 0xA4, 0xFA, 0x0A, 0xBA,
- 0xD4, 0xEB, 0xEA, 0xEC, 0xA8, 0xBC, 0xB4, 0xDC,
- 0x84, 0xE4, 0xCE, 0xEC, 0x92, 0xCD, 0xDC, 0x8B,
- 0xCC, 0x1E, 0xF6, 0xB2, 0x60, 0x2A, 0x96, 0x52,
- 0x0F, 0xBD, 0xFA, 0xCC, 0xB8, 0x7A, 0x4C, 0xD2,
- 0x06, 0xEF, 0x44, 0x64, 0xF4, 0xBA, 0xCE, 0xE6,
- 0x8A, 0x6F, 0x3C, 0x70, 0x7C, 0x9C, 0xBA, 0xDF,
- 0x2C, 0x4D, 0x3B, 0xCA, 0xDE, 0xCE, 0xEE, 0x46,
- 0x6A, 0xAC, 0x96, 0xE5, 0x96, 0x7A, 0xBA, 0xB6,
- 0xE2, 0x7E, 0xAA, 0xC5, 0x96, 0x9E, 0xC2, 0xAA,
- 0xDA, 0x35, 0xB6, 0x82, 0x88, 0xBE, 0xC2, 0x9E,
- 0xB4, 0xD5, 0xDA, 0x9C, 0xA0, 0xD0, 0xA8, 0xC7,
- 0x72, 0xF2, 0xDB, 0x76, 0xDC, 0xBE, 0xAA, 0xF4,
- 0x87, 0x2F, 0x53, 0x8E, 0x36, 0xCE, 0xE6, 0xCA,
- 0xCB, 0xE4, 0xD6, 0xAA, 0x42, 0x5D, 0xB4, 0x59,
- 0x1C, 0xC8, 0x96, 0x6C, 0xDA, 0xCE, 0xE6, 0xCB,
- 0x96, 0x16, 0xFA, 0xBE, 0xAE, 0xFE, 0x6E, 0xD6,
- 0xCE, 0xB6, 0xE5, 0xED, 0xDB, 0xDC, 0xF4, 0x72,
- 0x1F, 0xAE, 0xE6, 0xC2, 0xCA, 0xC4
-};
-
-unsigned char linux_logo_green[] __initdata = {
- 0x02, 0x88, 0xC4, 0x85, 0x44, 0xA2, 0xA8, 0xE5,
- 0x65, 0xA6, 0xC2, 0x24, 0xA4, 0xB4, 0x62, 0x86,
- 0x94, 0x44, 0xD2, 0xB6, 0x12, 0xD4, 0x73, 0x96,
- 0x92, 0x95, 0xB2, 0xC2, 0x36, 0x0E, 0xBC, 0x54,
- 0x75, 0xA5, 0xF5, 0x0A, 0xB2, 0x83, 0xC2, 0x74,
- 0x9B, 0xBD, 0xA2, 0xCA, 0xDA, 0x8C, 0xCB, 0x42,
- 0xAC, 0x12, 0xDA, 0x7B, 0x54, 0x94, 0xD2, 0x24,
- 0xBE, 0x06, 0x65, 0x33, 0xBB, 0xBC, 0xAB, 0x8C,
- 0x92, 0x1E, 0x9B, 0xB6, 0x6E, 0xFB, 0x04, 0xA2,
- 0xC8, 0xBD, 0xAD, 0xEC, 0x92, 0xBC, 0x7B, 0x9D,
- 0x84, 0xC4, 0xC4, 0xB4, 0x6C, 0x93, 0xA3, 0x5E,
- 0x8D, 0x13, 0xD6, 0x82, 0x4C, 0x2A, 0x7A, 0x5A,
- 0x0D, 0x82, 0xBB, 0xCC, 0x8B, 0x6A, 0x3C, 0xBE,
- 0x06, 0xC4, 0x44, 0x45, 0xDB, 0x96, 0xB6, 0xDE,
- 0x8A, 0x4D, 0x3C, 0x5A, 0x7C, 0x9C, 0xAA, 0xCB,
- 0x1C, 0x4D, 0x2E, 0xB2, 0xBE, 0xAA, 0xDE, 0x3E,
- 0x6A, 0xAC, 0x82, 0xE5, 0x72, 0x62, 0x92, 0x9E,
- 0xCA, 0x4A, 0x8E, 0xBE, 0x86, 0x6B, 0xAA, 0x9A,
- 0xBE, 0x34, 0xAB, 0x76, 0x6E, 0x9A, 0x9E, 0x62,
- 0x76, 0xCE, 0xD3, 0x92, 0x7C, 0xB8, 0x7E, 0xC6,
- 0x5E, 0xE2, 0xC3, 0x54, 0xAA, 0x9E, 0x8A, 0xCA,
- 0x63, 0x2D, 0x3B, 0x8E, 0x1A, 0x9E, 0xC2, 0xA6,
- 0xCB, 0xDC, 0xD6, 0x8E, 0x26, 0x5C, 0xB4, 0x45,
- 0x1C, 0xB8, 0x6E, 0x4C, 0xBC, 0xAE, 0xD6, 0x92,
- 0x63, 0x16, 0xF6, 0x8C, 0x7A, 0xFE, 0x6E, 0xBA,
- 0xC6, 0x86, 0xAA, 0xAE, 0xDB, 0xA4, 0xD4, 0x56,
- 0x0E, 0x6E, 0xB6, 0xB2, 0xBE, 0xBE
-};
-
-unsigned char linux_logo_blue[] __initdata = {
- 0x04, 0x28, 0x10, 0x0B, 0x14, 0x14, 0x74, 0xC7,
- 0x64, 0x0E, 0xC3, 0x24, 0xA4, 0x0C, 0x10, 0x20,
- 0x0D, 0x04, 0xD1, 0x0D, 0x13, 0x22, 0x0A, 0x40,
- 0x14, 0x0C, 0x11, 0x94, 0x0C, 0x08, 0x0B, 0x56,
- 0x09, 0x47, 0xF4, 0x0B, 0x9C, 0x07, 0x54, 0x74,
- 0x0F, 0x0C, 0x0F, 0xC7, 0x6C, 0x14, 0x14, 0x11,
- 0x0B, 0x04, 0x12, 0x0C, 0x05, 0x94, 0x94, 0x0A,
- 0x34, 0x09, 0x14, 0x08, 0x2F, 0x15, 0x19, 0x11,
- 0x28, 0x0C, 0x0B, 0x94, 0x08, 0xFA, 0x08, 0x7C,
- 0xBC, 0x15, 0x0A, 0xEC, 0x64, 0xBB, 0x0A, 0x0C,
- 0x84, 0x2C, 0xA0, 0x15, 0x10, 0x0D, 0x0B, 0x0E,
- 0x0A, 0x07, 0x10, 0x3C, 0x24, 0x2C, 0x28, 0x5C,
- 0x0A, 0x0D, 0x0A, 0xC1, 0x22, 0x4C, 0x10, 0x94,
- 0x04, 0x0F, 0x45, 0x08, 0x31, 0x54, 0x3C, 0xBC,
- 0x8C, 0x09, 0x3C, 0x18, 0x7C, 0x9C, 0x7C, 0x91,
- 0x0C, 0x4D, 0x17, 0x74, 0x0C, 0x48, 0x9C, 0x3C,
- 0x6A, 0xAC, 0x5C, 0xE3, 0x29, 0x3C, 0x2C, 0x7C,
- 0x6C, 0x04, 0x14, 0xA9, 0x74, 0x07, 0x2C, 0x74,
- 0x4C, 0x34, 0x97, 0x5C, 0x38, 0x0C, 0x5C, 0x04,
- 0x0C, 0xBA, 0xBC, 0x78, 0x18, 0x88, 0x24, 0xC2,
- 0x3C, 0xB4, 0x87, 0x0C, 0x14, 0x4C, 0x3C, 0x10,
- 0x17, 0x2C, 0x0A, 0x8C, 0x04, 0x1C, 0x44, 0x2C,
- 0xCD, 0xD8, 0xD4, 0x34, 0x0C, 0x5B, 0xB4, 0x1E,
- 0x1D, 0xAC, 0x24, 0x18, 0x20, 0x5C, 0xB4, 0x1C,
- 0x09, 0x14, 0xFC, 0x0C, 0x10, 0xFC, 0x6C, 0x7C,
- 0xB4, 0x1C, 0x15, 0x17, 0xDB, 0x18, 0x21, 0x24,
- 0x04, 0x04, 0x44, 0x8C, 0x8C, 0xB7
-};
-
-unsigned char linux_logo[] __initdata = {
- 0xBF, 0x95, 0x90, 0xCB, 0x95, 0xA1, 0x2C, 0x2C,
- 0x95, 0x55, 0xCB, 0x90, 0xCB, 0x95, 0x2C, 0x95,
- 0xCB, 0x47, 0x94, 0x95, 0xA1, 0xD6, 0xD6, 0x2C,
- 0x90, 0x47, 0x70, 0x2C, 0x6D, 0x2A, 0x6D, 0xD6,
- 0xA1, 0x2C, 0x55, 0x95, 0x2C, 0x2C, 0x55, 0x55,
- 0x95, 0xA1, 0xA1, 0xA1, 0x6D, 0xBF, 0x2A, 0x2A,
- 0xBF, 0x83, 0xBF, 0x95, 0x90, 0xCB, 0x95, 0xA1,
- 0x2C, 0x2C, 0x95, 0x55, 0xCB, 0x90, 0xCB, 0x95,
- 0x2C, 0x95, 0xCB, 0x47, 0x94, 0x95, 0xA1, 0xD6,
- 0xD6, 0x2C, 0x90, 0x47, 0x70, 0x2C, 0x6D, 0x2A,
- 0x95, 0x47, 0x47, 0x90, 0x2C, 0x2C, 0x2C, 0x95,
- 0x55, 0x55, 0xCB, 0x90, 0xCB, 0x55, 0x55, 0xCB,
- 0x47, 0xE6, 0x70, 0x95, 0xD6, 0xD6, 0xA1, 0x2C,
- 0x55, 0x55, 0x95, 0xD6, 0x6D, 0xD6, 0xA1, 0x2C,
- 0x2C, 0x95, 0x55, 0x95, 0x95, 0x95, 0x2C, 0x2C,
- 0xA1, 0xA1, 0x2C, 0x2C, 0xA1, 0xD6, 0xD6, 0xD6,
- 0xD6, 0xD6, 0x95, 0x47, 0x47, 0x90, 0x2C, 0x2C,
- 0x2C, 0x95, 0x55, 0x55, 0xCB, 0x90, 0xCB, 0x55,
- 0x55, 0xCB, 0x47, 0xE6, 0x70, 0x95, 0xD6, 0xD6,
- 0xA1, 0x2C, 0x55, 0x55, 0x95, 0xD6, 0x6D, 0xD6,
- 0x90, 0x47, 0x47, 0x70, 0x2C, 0xA1, 0x2C, 0x95,
- 0x55, 0x55, 0x90, 0xCB, 0x55, 0x55, 0x55, 0x70,
- 0x94, 0x70, 0x95, 0xA1, 0xD6, 0xD6, 0xA1, 0x2C,
- 0x95, 0x95, 0x2C, 0xA1, 0xD6, 0xA1, 0x2C, 0x2C,
- 0x95, 0x55, 0xCB, 0x95, 0xD6, 0xA1, 0x2C, 0x95,
- 0xA1, 0xD6, 0xD6, 0xA1, 0xA1, 0xD6, 0xA1, 0xA1,
- 0xA1, 0x2C, 0x90, 0x47, 0x47, 0x70, 0x2C, 0xA1,
- 0x2C, 0x95, 0x55, 0x55, 0x90, 0xCB, 0x55, 0x55,
- 0x55, 0x70, 0x94, 0x70, 0x95, 0xA1, 0xD6, 0xD6,
- 0xA1, 0x2C, 0x95, 0x95, 0x2C, 0xD6, 0xD6, 0xA1,
- 0x94, 0xA0, 0x47, 0x55, 0x2C, 0xD6, 0xA1, 0x95,
- 0x55, 0x55, 0xCB, 0xCB, 0x55, 0x55, 0xCB, 0xCB,
- 0x55, 0x95, 0x2C, 0xA1, 0xD6, 0xD6, 0xA1, 0x2C,
- 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x95,
- 0x55, 0x55, 0x2C, 0x3F, 0x80, 0x20, 0x88, 0x88,
- 0x88, 0x20, 0x88, 0xB1, 0x2C, 0xA1, 0x2C, 0x2C,
- 0x95, 0xCB, 0x94, 0xA0, 0x47, 0x55, 0x2C, 0xD6,
- 0xA1, 0x95, 0x55, 0x55, 0xCB, 0xCB, 0x55, 0x55,
- 0xCB, 0xCB, 0x55, 0x95, 0x2C, 0xA1, 0xD6, 0xD6,
- 0xA1, 0x2C, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
- 0x94, 0x94, 0x70, 0x2C, 0xA1, 0xD6, 0xA1, 0x2C,
- 0x55, 0x55, 0xCB, 0x55, 0x55, 0x55, 0x55, 0x55,
- 0x95, 0x2C, 0xD6, 0xD6, 0xD6, 0xA1, 0x2C, 0x95,
- 0x55, 0x55, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
- 0x2C, 0x94, 0x80, 0x20, 0x20, 0x20, 0x20, 0x20,
- 0x20, 0x20, 0x20, 0x20, 0x88, 0x92, 0xA1, 0x95,
- 0x55, 0x90, 0x94, 0x94, 0x70, 0x2C, 0xA1, 0xD6,
- 0xA1, 0x2C, 0x55, 0x55, 0xCB, 0x55, 0x55, 0x55,
- 0x55, 0x55, 0x95, 0x2C, 0xD6, 0xD6, 0xD6, 0xA1,
- 0x2C, 0x95, 0x55, 0x55, 0x55, 0x95, 0x95, 0x95,
- 0x70, 0x70, 0x55, 0x2C, 0xD6, 0xD6, 0xA1, 0x95,
- 0x55, 0x90, 0xCB, 0xCB, 0x55, 0x55, 0x2C, 0x2C,
- 0xA1, 0xD6, 0xA1, 0xA1, 0x2C, 0x2C, 0x95, 0x55,
- 0x55, 0x55, 0x95, 0x95, 0x2C, 0x95, 0x95, 0xD6,
- 0xB1, 0x88, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
- 0x20, 0x20, 0x20, 0x80, 0x34, 0x88, 0x43, 0x47,
- 0x95, 0xCB, 0x70, 0x70, 0x55, 0x2C, 0xD6, 0xD6,
- 0xA1, 0x95, 0x55, 0x90, 0xCB, 0xCB, 0x55, 0x55,
- 0x2C, 0x2C, 0xA1, 0xD6, 0xA1, 0xA1, 0xA1, 0x2C,
- 0x55, 0x55, 0x55, 0x55, 0x2C, 0x95, 0x2C, 0x2C,
- 0x55, 0x55, 0x95, 0x2C, 0xA1, 0xA1, 0x2C, 0x55,
- 0x90, 0x70, 0x90, 0x55, 0x95, 0x95, 0xA1, 0xA1,
- 0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0x95, 0x95, 0x95,
- 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0xD5,
- 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
- 0x20, 0x20, 0x88, 0x7D, 0x3F, 0xB1, 0x80, 0x20,
- 0x99, 0x2C, 0x55, 0x55, 0x95, 0x2C, 0xA1, 0xA1,
- 0x2C, 0x55, 0x90, 0x70, 0x90, 0x55, 0x95, 0x95,
- 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0x2C, 0x2C,
- 0x95, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
- 0x95, 0x90, 0x55, 0x2C, 0xA1, 0xA1, 0x95, 0xCB,
- 0x70, 0x94, 0x90, 0x55, 0x95, 0xA1, 0xA1, 0xA1,
- 0x2C, 0x2C, 0x2C, 0x2C, 0x95, 0x95, 0x95, 0x95,
- 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0xA1, 0x88,
- 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
- 0x20, 0x20, 0x20, 0xB1, 0x47, 0xD5, 0x7D, 0x43,
- 0x20, 0x70, 0x95, 0x90, 0x55, 0x2C, 0xA1, 0xA1,
- 0x95, 0xCB, 0x70, 0x94, 0x90, 0x55, 0x95, 0xA1,
- 0xA1, 0xA1, 0x2C, 0x95, 0x2C, 0x2C, 0x95, 0x95,
- 0x95, 0x95, 0x95, 0x2C, 0x95, 0x95, 0x95, 0x95,
- 0x95, 0x90, 0x55, 0x2C, 0xD6, 0xD6, 0x2C, 0x90,
- 0x94, 0x70, 0x55, 0x95, 0x2C, 0xD6, 0xD6, 0xA1,
- 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x95, 0x55, 0x55,
- 0xCB, 0xCB, 0xCB, 0x55, 0xCB, 0x55, 0x47, 0x20,
- 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
- 0x20, 0x20, 0x88, 0xB1, 0x3F, 0x92, 0x2B, 0x80,
- 0x20, 0x80, 0xD6, 0x70, 0x55, 0x2C, 0xD6, 0xD6,
- 0x2C, 0x90, 0x94, 0x70, 0x55, 0x95, 0x2C, 0xD6,
- 0xD6, 0xA1, 0x2C, 0x95, 0x95, 0x2C, 0x2C, 0x95,
- 0x95, 0x55, 0x90, 0xCB, 0xCB, 0xCB, 0xCB, 0x55,
- 0xD6, 0x55, 0x95, 0xA1, 0xD6, 0xA1, 0x55, 0x70,
- 0x94, 0x55, 0x95, 0xA1, 0xA1, 0xA1, 0xA1, 0x95,
- 0x55, 0x55, 0x55, 0x95, 0x55, 0x55, 0xCB, 0x90,
- 0x70, 0x90, 0xCB, 0x55, 0x55, 0xA1, 0xD8, 0x20,
- 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
- 0x20, 0x20, 0x88, 0xD8, 0xE1, 0x88, 0x20, 0x20,
- 0x88, 0x88, 0xE6, 0x55, 0x2C, 0xA1, 0xD6, 0xA1,
- 0x55, 0x70, 0x94, 0x55, 0x95, 0xA1, 0xA1, 0xA1,
- 0xA1, 0x95, 0x55, 0x55, 0x95, 0x95, 0x55, 0x55,
- 0x90, 0x90, 0x90, 0x90, 0xCB, 0x55, 0x55, 0x55,
- 0xD6, 0x2C, 0xA1, 0xD6, 0xD6, 0xA1, 0xCB, 0x70,
- 0x70, 0x95, 0x2C, 0xA1, 0xA1, 0x2C, 0x2C, 0x55,
- 0xCB, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55,
- 0x55, 0x95, 0x2C, 0x95, 0x2C, 0xD6, 0x20, 0x20,
- 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
- 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
- 0x20, 0x20, 0x80, 0xD6, 0xA1, 0xD6, 0xD6, 0xA1,
- 0xCB, 0x70, 0x70, 0x95, 0x2C, 0xA1, 0xA1, 0x2C,
- 0x2C, 0x55, 0xCB, 0xCB, 0x55, 0x55, 0x55, 0x55,
- 0x55, 0x55, 0x55, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
- 0xD6, 0xA1, 0xA1, 0xA1, 0xA1, 0x55, 0x70, 0x94,
- 0xCB, 0x95, 0xA1, 0xA1, 0x2C, 0x95, 0xCB, 0x55,
- 0x90, 0xCB, 0x55, 0x55, 0x55, 0x55, 0x95, 0xA1,
- 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0x95, 0x20, 0x20,
- 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
- 0x88, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
- 0x20, 0x20, 0x88, 0x95, 0xA1, 0xA1, 0xA1, 0x55,
- 0x70, 0x94, 0xCB, 0x95, 0xA1, 0xA1, 0x2C, 0x95,
- 0xCB, 0xCB, 0x90, 0xCB, 0x55, 0x55, 0x55, 0x55,
- 0x95, 0x2C, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1,
- 0x2C, 0x2C, 0x2C, 0x95, 0x95, 0xCB, 0x70, 0x70,
- 0x95, 0x2C, 0x2C, 0x95, 0xCB, 0x70, 0x90, 0xCB,
- 0xCB, 0x55, 0x55, 0xCB, 0x55, 0x55, 0x2C, 0xD6,
- 0xD6, 0xD6, 0xD6, 0xA1, 0x2C, 0x70, 0x20, 0x20,
- 0x88, 0x43, 0xD8, 0x43, 0x20, 0x20, 0x20, 0x20,
- 0x20, 0x88, 0x88, 0x43, 0x2B, 0xD8, 0x20, 0x20,
- 0x20, 0x20, 0x20, 0x3F, 0x2C, 0x95, 0x95, 0xCB,
- 0x70, 0x70, 0x95, 0x2C, 0x2C, 0x95, 0xCB, 0x90,
- 0x90, 0xCB, 0x55, 0xCB, 0x55, 0xCB, 0x55, 0x95,
- 0x2C, 0xD6, 0xD6, 0xD6, 0xD6, 0xA1, 0x2C, 0x2C,
- 0xA1, 0x95, 0x95, 0x55, 0xCB, 0x70, 0x90, 0x55,
- 0x2C, 0x2C, 0x2C, 0x55, 0x70, 0x70, 0x55, 0x95,
- 0x95, 0xCB, 0x90, 0x90, 0x90, 0x95, 0x2C, 0xA1,
- 0xD6, 0xD6, 0x2C, 0x2C, 0x95, 0x70, 0x20, 0x20,
- 0x80, 0x2B, 0x34, 0x2B, 0x88, 0x20, 0x20, 0x20,
- 0x88, 0xB1, 0x28, 0x28, 0x2B, 0x7D, 0x80, 0x20,
- 0x20, 0x20, 0x20, 0x92, 0x95, 0x55, 0xCB, 0x70,
- 0x90, 0x55, 0x2C, 0x2C, 0x2C, 0x55, 0x70, 0x70,
- 0x55, 0x95, 0x55, 0x55, 0x90, 0x90, 0x90, 0x55,
- 0x2C, 0xA1, 0xD6, 0xA1, 0x2C, 0x2C, 0x95, 0x95,
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- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0x42, 0x73, 0x50, 0xBE, 0x79,
- 0x20, 0x20, 0x20, 0x20, 0x66, 0xCC, 0x37, 0x9C,
- 0x3E, 0xCE, 0xBF, 0x95, 0x95, 0x95, 0x2C, 0x95,
- 0x95, 0x55, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB, 0x55,
- 0xA1, 0x55, 0x95, 0xA1, 0xD6, 0xA1, 0x55, 0x94,
- 0x94, 0xE8, 0x60, 0xC4, 0x3E, 0x2D, 0x2D, 0x2D,
- 0x33, 0x5D, 0x82, 0x49, 0x49, 0x49, 0x49, 0x49,
- 0x89, 0xAA, 0x59, 0x20, 0x20, 0x28, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xEC, 0x4A, 0x2D, 0x50, 0x78, 0x2E,
- 0x57, 0x51, 0xF0, 0x57, 0x31, 0x4D, 0x50, 0x2D,
- 0x5D, 0xF2, 0xA1, 0x2C, 0x95, 0x95, 0x55, 0x55,
- 0x90, 0x90, 0x70, 0x90, 0xCB, 0x55, 0x55, 0x55,
- 0x6D, 0x2C, 0xA1, 0xD6, 0xD6, 0xA1, 0x55, 0x94,
- 0x70, 0xB9, 0x75, 0x50, 0x3E, 0x49, 0x49, 0x49,
- 0x5D, 0x82, 0x49, 0x49, 0x82, 0x49, 0x49, 0x49,
- 0x89, 0x69, 0x4F, 0x20, 0x20, 0x20, 0x8A, 0x42,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0x83, 0x4A, 0x3A, 0x50, 0x62, 0x23,
- 0x81, 0xB8, 0xB8, 0xE9, 0x5F, 0x29, 0x33, 0x5D,
- 0x5D, 0x73, 0xE8, 0xCB, 0x55, 0x55, 0x55, 0x55,
- 0x55, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
- 0xD6, 0xA1, 0xA1, 0xA1, 0xA1, 0x55, 0x70, 0x70,
- 0xCB, 0x68, 0x75, 0x50, 0x82, 0x49, 0x49, 0x49,
- 0x5D, 0x49, 0x49, 0x5D, 0x49, 0x49, 0x5D, 0x82,
- 0x69, 0x5D, 0x25, 0xF0, 0x20, 0x20, 0x20, 0xE1,
- 0x2A, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0x4B, 0xF4, 0xDF, 0x50, 0x73, 0x76, 0x48,
- 0x75, 0xDF, 0x75, 0x62, 0xC4, 0x33, 0x82, 0x49,
- 0x5D, 0x5D, 0xA8, 0xF5, 0x55, 0x55, 0x55, 0x55,
- 0x2C, 0x2C, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1,
- 0x2C, 0x2C, 0x2C, 0x95, 0x95, 0xCB, 0x70, 0x70,
- 0x95, 0x83, 0x5F, 0xEA, 0x2D, 0x49, 0x49, 0x49,
- 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
- 0x5D, 0x49, 0x22, 0x5A, 0x79, 0x20, 0x20, 0x20,
- 0x80, 0xD2, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0x65, 0xD0, 0x63, 0x5F, 0x29, 0x2D, 0x2D, 0xEA,
- 0x29, 0x29, 0x76, 0x50, 0x2D, 0x82, 0x49, 0x49,
- 0x3E, 0x49, 0x5C, 0xB0, 0xBA, 0x95, 0x55, 0x55,
- 0x2C, 0xA1, 0xD6, 0xD6, 0xD6, 0xA1, 0x2C, 0x2C,
- 0xA1, 0x95, 0x95, 0x55, 0xCB, 0x70, 0x70, 0x55,
- 0x2C, 0x83, 0x60, 0x76, 0x5D, 0x49, 0x49, 0x49,
- 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
- 0x49, 0x5D, 0x89, 0xDC, 0x8B, 0x20, 0x20, 0x20,
- 0x20, 0x95, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE2, 0x32, 0x85, 0xE3, 0x29, 0x2D, 0x33, 0x2D,
- 0x2D, 0x2D, 0x6A, 0x2D, 0x33, 0x5D, 0x49, 0x82,
- 0x49, 0x49, 0x82, 0x73, 0x5C, 0x9E, 0x2C, 0x55,
- 0x2C, 0xA1, 0xD6, 0xA1, 0x2C, 0x2C, 0x95, 0x95,
- 0x2C, 0x95, 0x55, 0xCB, 0x90, 0x90, 0xCB, 0x95,
- 0x2C, 0x6D, 0x41, 0x6F, 0x3E, 0x49, 0x49, 0x49,
- 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
- 0x49, 0x82, 0x3E, 0x4E, 0x38, 0xCA, 0x20, 0x20,
- 0x20, 0x55, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0x65,
- 0x42, 0xA0, 0xD4, 0xE3, 0x29, 0x2D, 0x82, 0x5D,
- 0x5D, 0x82, 0x82, 0x49, 0x49, 0x49, 0x49, 0x49,
- 0x49, 0x3E, 0x49, 0x49, 0x49, 0x5C, 0x56, 0xD6,
- 0xA1, 0xA1, 0xA1, 0x95, 0x55, 0x55, 0x55, 0x95,
- 0xA1, 0x55, 0x90, 0x70, 0x94, 0x70, 0x95, 0x2C,
- 0x2C, 0xD6, 0xDD, 0x6F, 0x33, 0x49, 0x49, 0x49,
- 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
- 0x5D, 0x5D, 0x82, 0x69, 0x22, 0x62, 0x80, 0x34,
- 0x94, 0x6B, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0x65, 0xE5, 0x65, 0x6B,
- 0xD5, 0x88, 0x5B, 0xE3, 0x29, 0x5D, 0x5D, 0x5D,
- 0x5D, 0x5D, 0x5D, 0x5D, 0x49, 0x49, 0x49, 0x82,
- 0x49, 0x49, 0x89, 0x49, 0x82, 0x49, 0x71, 0xBA,
- 0x6D, 0x6D, 0xA1, 0x95, 0x55, 0xCB, 0x55, 0x55,
- 0x2C, 0x55, 0x70, 0x70, 0x70, 0x90, 0x95, 0xA1,
- 0x2C, 0xA1, 0x41, 0x76, 0x5D, 0x5D, 0x49, 0x49,
- 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
- 0x49, 0x5D, 0x82, 0x5D, 0x89, 0x5E, 0x96, 0x65,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0xE5, 0xE5, 0xE5, 0xE5, 0x65, 0x65, 0xEC, 0xB1,
- 0x20, 0x20, 0xCA, 0x23, 0x29, 0x33, 0x49, 0x5D,
- 0x49, 0x82, 0x49, 0x49, 0x49, 0x49, 0x49, 0x82,
- 0x49, 0x82, 0x5D, 0x5D, 0x5D, 0x2D, 0x5C, 0x8F,
- 0x6D, 0xD6, 0x2C, 0x55, 0x90, 0xCB, 0x95, 0x95,
- 0x95, 0x55, 0x70, 0x94, 0x70, 0x55, 0x2C, 0xA1,
- 0x95, 0xE8, 0x5F, 0x76, 0x33, 0x5D, 0x49, 0x49,
- 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
- 0x49, 0x49, 0x49, 0x49, 0x3E, 0x9C, 0x2F, 0x68,
- 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
- 0x65, 0xE5, 0x65, 0xE5, 0x6B, 0x90, 0x80, 0x20,
- 0x20, 0x20, 0x4F, 0x81, 0x50, 0x3E, 0x49, 0x49,
- 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
- 0x69, 0x69, 0x49, 0x5D, 0x2D, 0xC4, 0x46, 0xA3,
- 0xD6, 0x55, 0x70, 0x94, 0x94, 0x70, 0xCB, 0x55,
- 0x55, 0xCB, 0x70, 0x47, 0x70, 0x95, 0xA1, 0xA1,
- 0x95, 0xBD, 0x75, 0x2D, 0x33, 0x49, 0x49, 0x49,
- 0x49, 0x49, 0x5D, 0x49, 0x49, 0x49, 0x49, 0x49,
- 0x49, 0x49, 0x49, 0x49, 0x5D, 0x2D, 0xB5, 0xDB,
- 0xD6, 0x65, 0xE5, 0x65, 0xE5, 0xE5, 0x65, 0xE5,
- 0x65, 0x65, 0x6B, 0x95, 0x2B, 0x88, 0x20, 0x20,
- 0x20, 0x20, 0x8B, 0x81, 0x29, 0x33, 0x49, 0x49,
- 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
- 0x49, 0x3E, 0x3E, 0x5E, 0x41, 0x97, 0x27, 0xD6,
- 0x55, 0x94, 0xE6, 0xE6, 0x47, 0x70, 0x55, 0x55,
- 0x94, 0x70, 0x94, 0x94, 0x70, 0x55, 0xA1, 0x2C,
- 0x6D, 0xC5, 0x39, 0x6A, 0x5D, 0x5D, 0x49, 0x49,
- 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
- 0x49, 0x49, 0x49, 0x49, 0x3E, 0xEA, 0x30, 0x77,
- 0xE1, 0xC9, 0x94, 0x2C, 0xD6, 0xD6, 0xA1, 0x55,
- 0x47, 0x9F, 0x43, 0x20, 0x20, 0x20, 0x20, 0x20,
- 0x20, 0x80, 0x91, 0x81, 0x6A, 0x2D, 0x49, 0x49,
- 0x49, 0x5D, 0x5D, 0x49, 0x49, 0x5D, 0x5D, 0x82,
- 0xEB, 0x4A, 0x41, 0xC2, 0x8F, 0xF5, 0xA1, 0x55,
- 0x94, 0x28, 0xA0, 0x47, 0x70, 0x55, 0x95, 0x95,
- 0x47, 0x70, 0x70, 0x94, 0x90, 0x95, 0xA1, 0x2C,
- 0xE8, 0xA6, 0x39, 0x76, 0x50, 0x50, 0x2D, 0x2D,
- 0x3E, 0x3E, 0x5D, 0x3E, 0x5D, 0x5D, 0x49, 0x82,
- 0x49, 0x49, 0x49, 0x82, 0x82, 0x50, 0x75, 0xE0,
- 0x57, 0x20, 0x88, 0x88, 0x20, 0x20, 0x88, 0x20,
- 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
- 0x20, 0x79, 0x91, 0x81, 0x76, 0x33, 0x49, 0x49,
- 0x5D, 0x82, 0x49, 0x49, 0x3E, 0x6A, 0xEA, 0x29,
- 0xDF, 0x97, 0xBF, 0x6D, 0x6D, 0xD6, 0x55, 0x47,
- 0x28, 0x28, 0x47, 0x70, 0x55, 0x95, 0x2C, 0x2C,
- 0x95, 0x95, 0x55, 0x90, 0x90, 0x95, 0xA1, 0xA1,
- 0xD6, 0x26, 0x45, 0x81, 0x5F, 0x30, 0x48, 0x6F,
- 0x6F, 0x29, 0x29, 0x6A, 0x2D, 0x2D, 0x5D, 0x49,
- 0x49, 0x49, 0x49, 0x49, 0x2D, 0x76, 0x6E, 0x77,
- 0x5B, 0x66, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
- 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
- 0x20, 0x79, 0xA9, 0xB8, 0x39, 0x50, 0x5D, 0x5D,
- 0x5D, 0x5D, 0x3E, 0x2D, 0x29, 0x76, 0xCD, 0x37,
- 0xB9, 0xA1, 0xA1, 0x6D, 0x6D, 0x2C, 0x94, 0x28,
- 0xD5, 0xE6, 0x70, 0x55, 0x95, 0xA1, 0x2C, 0xA1,
- 0xBF, 0xA1, 0x95, 0xCB, 0x55, 0x95, 0xA1, 0x2C,
- 0x95, 0x83, 0xDE, 0x87, 0xB6, 0xBE, 0x40, 0x6E,
- 0x81, 0x81, 0x78, 0x78, 0x39, 0x6F, 0xEA, 0x2D,
- 0x2D, 0x33, 0x33, 0x33, 0x76, 0x30, 0x64, 0x54,
- 0x5B, 0x66, 0x20, 0x20, 0x66, 0x20, 0x88, 0x20,
- 0x20, 0x20, 0x88, 0x20, 0x20, 0x20, 0x20, 0x20,
- 0x88, 0x34, 0x8B, 0xF1, 0x23, 0x6F, 0x50, 0x2D,
- 0x2D, 0x6A, 0x29, 0x6F, 0x78, 0x84, 0x9B, 0xD2,
- 0x2C, 0x2C, 0xD6, 0x6D, 0x6D, 0x2C, 0x47, 0xA0,
- 0xE6, 0x70, 0x55, 0x95, 0x2C, 0xA1, 0xA1, 0xA1,
- 0xD2, 0x95, 0x55, 0xCB, 0x55, 0x2C, 0xD6, 0xA1,
- 0x95, 0x95, 0xA1, 0xD6, 0x6D, 0x6D, 0xBA, 0xF3,
- 0x8D, 0x36, 0x74, 0x36, 0xF1, 0xB8, 0x23, 0x78,
- 0x62, 0x4A, 0x29, 0x62, 0x23, 0xF1, 0x54, 0x31,
- 0x57, 0x2B, 0x90, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
- 0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0x2C, 0x2C, 0xCB,
- 0xE6, 0x7D, 0xCA, 0xB7, 0xB8, 0x75, 0x6F, 0x6F,
- 0x76, 0x6F, 0x78, 0x81, 0x53, 0xBD, 0x6D, 0x2C,
- 0x95, 0x95, 0xA1, 0x6D, 0xA1, 0x55, 0x94, 0xE6,
- 0x70, 0xCB, 0x55, 0x95, 0xA1, 0xD6, 0xD6, 0xA1,
- 0xD0, 0x94, 0x94, 0x90, 0x95, 0x2C, 0xD6, 0xA1,
- 0x95, 0x55, 0x2C, 0xA1, 0xD6, 0xA1, 0x95, 0x2C,
- 0xD6, 0x68, 0xAB, 0x6C, 0xA4, 0x77, 0x77, 0xAD,
- 0x40, 0x53, 0x6E, 0x40, 0xB7, 0x54, 0x31, 0xD7,
- 0xAC, 0xD6, 0x55, 0x55, 0x95, 0x95, 0x95, 0x55,
- 0x95, 0x2C, 0x2C, 0xA1, 0x95, 0x95, 0x2C, 0xA1,
- 0x6D, 0xD2, 0x7C, 0x54, 0xAD, 0x40, 0x6E, 0x81,
- 0x81, 0x6E, 0x36, 0xDA, 0xE8, 0xD6, 0xD6, 0x2C,
- 0x2C, 0x2C, 0xA1, 0xD6, 0x95, 0x90, 0x94, 0x47,
- 0x94, 0x94, 0x70, 0x55, 0x2C, 0xD6, 0xA1, 0x95,
- 0x95, 0x28, 0x47, 0x90, 0x95, 0x2C, 0xA1, 0x2C,
- 0x55, 0x95, 0x2C, 0xA1, 0xA1, 0x2C, 0x2C, 0x2C,
- 0x2C, 0xA1, 0x55, 0x70, 0x95, 0x2C, 0xB2, 0xB4,
- 0xC3, 0xC3, 0x54, 0x54, 0xA9, 0x31, 0xCA, 0x2A,
- 0x95, 0x90, 0x55, 0x95, 0x2C, 0xA1, 0x2C, 0x95,
- 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0xD6,
- 0x6D, 0x2A, 0xB2, 0x4F, 0x31, 0x2E, 0xE0, 0xAD,
- 0xB7, 0xC8, 0xB4, 0xF5, 0x2C, 0xA1, 0xA1, 0xA1,
- 0x95, 0x2C, 0xA1, 0x2C, 0x95, 0x70, 0x94, 0x94,
- 0x94, 0x94, 0x70, 0x95, 0xD6, 0xD6, 0x2C, 0x95,
- 0x94, 0x28, 0x47, 0xCB, 0x95, 0x2C, 0xA1, 0xA1,
- 0x95, 0x55, 0x2C, 0xA1, 0xD6, 0xA1, 0x95, 0x95,
- 0x95, 0x2C, 0x55, 0x70, 0x70, 0x70, 0x94, 0x2C,
- 0x63, 0xBB, 0xA5, 0xD7, 0xCA, 0xB3, 0x6D, 0x2C,
- 0x55, 0x55, 0x95, 0x2C, 0x2C, 0x2C, 0x95, 0x95,
- 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0xA1,
- 0xD6, 0x2C, 0x70, 0x95, 0xAC, 0xC0, 0xDB, 0xEF,
- 0xEF, 0xA2, 0xE8, 0x95, 0x95, 0xA1, 0xD6, 0xA1,
- 0x95, 0x55, 0x2C, 0x95, 0x55, 0x70, 0x70, 0x70,
- 0x94, 0x70, 0x55, 0xD6, 0x6D, 0x6D, 0x95, 0x55,
- 0x70, 0x47, 0x70, 0x95, 0x2C, 0x2C, 0x2C, 0xA1,
- 0x2C, 0x95, 0x2C, 0xA1, 0xD6, 0xA1, 0x95, 0x55,
- 0x55, 0x95, 0x55, 0x55, 0x55, 0x55, 0x55, 0x95,
- 0xA1, 0xF5, 0xBF, 0xBF, 0xA1, 0x95, 0x95, 0x95,
- 0x95, 0x55, 0x2C, 0x2C, 0x95, 0x55, 0x55, 0x95,
- 0x95, 0x95, 0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0xA1,
- 0x2C, 0x55, 0x70, 0x94, 0x90, 0x2C, 0x6D, 0x6D,
- 0x6D, 0xA1, 0x2C, 0x95, 0x2C, 0xA1, 0xD6, 0xA1,
- 0x2C, 0x55, 0x55, 0x95, 0x55, 0x55, 0x55, 0x55,
- 0x55, 0x95, 0xD6, 0x6D, 0xBF, 0xD6, 0x55, 0xCB,
- 0x55, 0x55, 0x55, 0x2C, 0x2C, 0x2C, 0x2C, 0xA1,
- 0xA1, 0x95, 0x2C, 0xA1, 0xA1, 0xA1, 0x2C, 0x95,
- 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0xA1,
- 0x6D, 0xBF, 0x6D, 0x2C, 0x55, 0x55, 0x95, 0x95,
- 0xCB, 0xCB, 0x55, 0x55, 0xCB, 0x55, 0x55, 0x95,
- 0x95, 0x2C, 0x2C, 0xA1, 0xA1, 0xA1, 0x2C, 0x2C,
- 0xA1, 0x95, 0xCB, 0xCB, 0x95, 0x95, 0x2C, 0x2C,
- 0x2C, 0xA1, 0x2C, 0x2C, 0x2C, 0xA1, 0xA1, 0x2C,
- 0x2C, 0x95, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C,
- 0x2C, 0xA1, 0x6D, 0xBF, 0x6D, 0xA1, 0x55, 0x55,
- 0x95, 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
- 0x2C, 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x95,
- 0x55, 0x95, 0x2C, 0x2C, 0xA1, 0xA1, 0xD6, 0xD6,
- 0x6D, 0x6D, 0xA1, 0x95, 0xCB, 0x55, 0x95, 0x55,
- 0x90, 0x70, 0xCB, 0xCB, 0x90, 0xCB, 0x95, 0x95,
- 0x2C, 0x2C, 0xA1, 0xD6, 0xA1, 0xA1, 0xA1, 0xA1,
- 0xA1, 0xA1, 0x2C, 0x95, 0x95, 0x2C, 0x2C, 0x2C,
- 0x2C, 0xA1, 0x2C, 0x95, 0x95, 0x95, 0x2C, 0x2C,
- 0x2C, 0x95, 0x55, 0x55, 0x2C, 0x2C, 0xA1, 0xA1,
- 0xD6, 0xD6, 0x6D, 0x6D, 0xA1, 0x55, 0xCB, 0x55
-};
-
-#endif
-
-#ifdef INCLUDE_LINUX_LOGOBW
-
-unsigned char linux_logo_bw[] __initdata = {
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x80, 0x00, 0x3F,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x1F,
- 0xFE, 0x1F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFE, 0x3F, 0xFF, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFE, 0x7F, 0xFF, 0xC7, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, 0xFF, 0xC3,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF,
- 0xFB, 0xE3, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFD, 0xFF, 0xFF, 0xE1, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xF9, 0xFF, 0xFF, 0xF1, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xFF, 0xFF, 0xF1,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xFF,
- 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xF9, 0xFF, 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xF9, 0xCF, 0xC3, 0xF8, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x87, 0x81, 0xF9,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xA7,
- 0x99, 0xF9, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xF9, 0xF3, 0xBC, 0xF9, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xF9, 0xE3, 0xBC, 0xF9, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xB0, 0x3C, 0xF9,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xB0,
- 0x19, 0xF0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xF9, 0xC0, 0x03, 0xF0, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xF9, 0x80, 0x01, 0xF8, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x80, 0x01, 0xF8,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x80,
- 0x01, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xF9, 0xC0, 0x21, 0xD8, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xF9, 0xB1, 0x80, 0xEC, 0xC0, 0x1F,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xF1, 0x90, 0x00, 0xE4,
- 0x00, 0x01, 0xFF, 0xFF, 0xFF, 0xFF, 0xF1, 0x8C,
- 0xC0, 0x7C, 0x04, 0x81, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xE3, 0x80, 0x00, 0x7C, 0x40, 0x11, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xE3, 0x80, 0x00, 0x7F, 0xD2, 0x29,
- 0xFF, 0xFF, 0xFF, 0xFF, 0x87, 0x00, 0x00, 0x3F,
- 0x80, 0x19, 0xFF, 0xFF, 0xFF, 0xFF, 0x0E, 0x00,
- 0x00, 0x3F, 0x80, 0x19, 0xFF, 0xFF, 0xFF, 0xFF,
- 0x1E, 0x00, 0x00, 0x1F, 0x80, 0x19, 0xFF, 0xFF,
- 0xFF, 0xFE, 0x1C, 0x00, 0x00, 0x1E, 0x80, 0x19,
- 0xFF, 0xFF, 0xFF, 0xFE, 0x3C, 0x00, 0x00, 0x1E,
- 0x80, 0x11, 0xFF, 0xFF, 0xFF, 0xFC, 0x7C, 0x00,
- 0x00, 0x0F, 0x80, 0x11, 0xFF, 0xFF, 0xFF, 0xFC,
- 0xF8, 0x00, 0x00, 0x0E, 0x80, 0x11, 0xFF, 0xFF,
- 0xFF, 0xFC, 0xF8, 0x00, 0x00, 0x06, 0x00, 0x11,
- 0xFF, 0xFF, 0xFF, 0xF8, 0xF8, 0x00, 0x00, 0x06,
- 0x00, 0x01, 0xFF, 0xFF, 0xFF, 0xF9, 0xF0, 0x00,
- 0x00, 0x02, 0x00, 0x09, 0xFF, 0xFF, 0xFF, 0xF1,
- 0xF0, 0x00, 0x00, 0x02, 0x80, 0x10, 0xFF, 0xFF,
- 0xFF, 0xF1, 0xE0, 0x00, 0x00, 0x00, 0x97, 0x10,
- 0xFF, 0xFF, 0xFF, 0xE3, 0xE0, 0x00, 0x00, 0x00,
- 0xDF, 0xF0, 0xFF, 0xFF, 0xFF, 0xE3, 0xC0, 0x00,
- 0x00, 0x00, 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0xC7,
- 0xC0, 0x00, 0x00, 0x01, 0xFF, 0xF8, 0xFF, 0xFF,
- 0xFF, 0xC7, 0x80, 0x00, 0x00, 0x01, 0xFF, 0xF8,
- 0xFF, 0xFF, 0xFF, 0x8F, 0x80, 0x00, 0x00, 0x01,
- 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0x8F, 0x80, 0x00,
- 0x00, 0x01, 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0x9F,
- 0x80, 0x00, 0x00, 0x01, 0xFF, 0xF8, 0xFF, 0xFF,
- 0xFF, 0x9F, 0x80, 0x00, 0x00, 0x01, 0x80, 0x18,
- 0xFF, 0xFF, 0xFF, 0x9E, 0x80, 0x00, 0x00, 0x03,
- 0xA8, 0x11, 0xFF, 0xFF, 0xFF, 0x9F, 0x80, 0x00,
- 0x00, 0x02, 0x00, 0x01, 0xFF, 0xFF, 0xFF, 0x99,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x09, 0xFF, 0xFF,
- 0xFF, 0x00, 0x80, 0x00, 0x00, 0x01, 0xC0, 0x01,
- 0xFF, 0xFF, 0xFE, 0x20, 0x60, 0x00, 0x00, 0x00,
- 0xFF, 0xC3, 0xFF, 0xFF, 0xF8, 0x00, 0x30, 0x00,
- 0x00, 0x00, 0xFF, 0x0F, 0xFF, 0xFF, 0xC0, 0x40,
- 0x38, 0x00, 0x00, 0x00, 0xFE, 0x47, 0xFF, 0xFF,
- 0x81, 0x00, 0x1C, 0x00, 0x00, 0x00, 0xFC, 0x23,
- 0xFF, 0xFF, 0x90, 0x00, 0x1E, 0x00, 0x00, 0x00,
- 0x78, 0x11, 0xFF, 0xFF, 0x80, 0x00, 0x0F, 0x80,
- 0x00, 0x00, 0x00, 0x01, 0xFF, 0xFF, 0x80, 0x00,
- 0x07, 0xC0, 0x00, 0x00, 0x00, 0x08, 0xFF, 0xFF,
- 0xC0, 0x00, 0x07, 0xC0, 0x00, 0x00, 0x00, 0x04,
- 0x7F, 0xFF, 0x80, 0x00, 0x03, 0xC0, 0x00, 0x10,
- 0x00, 0x00, 0x1F, 0xFF, 0x80, 0x00, 0x01, 0x80,
- 0x00, 0x30, 0x00, 0x00, 0x0F, 0xFF, 0x80, 0x00,
- 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, 0x4F, 0xFF,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00,
- 0x0F, 0xFF, 0xC0, 0x00, 0x00, 0x80, 0x03, 0xF0,
- 0x00, 0x00, 0x8F, 0xFF, 0x80, 0x00, 0x00, 0x40,
- 0x0F, 0xF0, 0x00, 0x04, 0x1F, 0xFF, 0x80, 0x00,
- 0x00, 0x7F, 0xFF, 0xF0, 0x00, 0x10, 0x1F, 0xFF,
- 0xC0, 0x00, 0x00, 0x7F, 0xFF, 0xF0, 0x00, 0x40,
- 0xFF, 0xFF, 0x98, 0x00, 0x00, 0xFF, 0xFF, 0xF0,
- 0x00, 0x83, 0xFF, 0xFF, 0x81, 0xE0, 0x01, 0xFF,
- 0xFF, 0xF8, 0x02, 0x07, 0xFF, 0xFF, 0x80, 0x3F,
- 0x07, 0xE0, 0x00, 0x1C, 0x0C, 0x1F, 0xFF, 0xFF,
- 0xF8, 0x03, 0xFF, 0x80, 0x00, 0x1F, 0x78, 0x1F,
- 0xFF, 0xFF, 0xFF, 0x80, 0x7F, 0x00, 0x07, 0x0F,
- 0xF0, 0x7F, 0xFF, 0xFF, 0xFF, 0xFE, 0x0C, 0x07,
- 0xFF, 0x83, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0x00, 0x1F, 0xFF, 0xC0, 0x03, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF8, 0x07, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-};
-
-#endif
-
-#ifdef INCLUDE_LINUX_LOGO16
-
-unsigned char linux_logo16_red[] __initdata = {
- 0x00, 0x90, 0xb0, 0x9c, 0xf7, 0x35, 0x83, 0xa5,
- 0x65, 0x8f, 0x98, 0xc9, 0xdb, 0xe1, 0xe7, 0xf8
-};
-
-unsigned char linux_logo16_green[] __initdata = {
- 0x00, 0x90, 0xb0, 0x9c, 0xf7, 0x2e, 0x83, 0xa5,
- 0x65, 0x6e, 0x98, 0x89, 0xbf, 0xac, 0xda, 0xf8
-};
-
-unsigned char linux_logo16_blue[] __initdata = {
- 0x00, 0x90, 0xaf, 0x9c, 0xf7, 0x2b, 0x82, 0xa5,
- 0x65, 0x41, 0x97, 0x1e, 0x60, 0x29, 0xa5, 0xf8
-};
-
-unsigned char linux_logo16[] __initdata = {
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa1, 0x11, 0x11,
- 0x61, 0x16, 0x66, 0x66, 0x11, 0x11, 0x11, 0x11,
- 0x11, 0x11, 0x1a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0xa8, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x87, 0x77, 0x77, 0x77, 0x77,
- 0x77, 0x77, 0x73, 0x33, 0x33, 0x3a, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xa3, 0x33, 0x33, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x77, 0x77, 0x77, 0x77,
- 0x77, 0x27, 0x77, 0x77, 0x77, 0x33, 0x3a, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xa3, 0x33, 0x33, 0x30, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x55, 0x50, 0x08, 0x33, 0x77, 0x77,
- 0x77, 0x72, 0x72, 0x27, 0x77, 0x77, 0x33, 0x33,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xa3, 0x33, 0x33, 0x77, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x58, 0x85, 0x00, 0x11, 0x11, 0xaa,
- 0xa3, 0x37, 0x77, 0x72, 0x22, 0x22, 0x77, 0x73,
- 0x33, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa3,
- 0x33, 0x37, 0x77, 0x33, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x56, 0x85, 0x00, 0x06, 0x66, 0x11,
- 0x11, 0x1a, 0xa3, 0x37, 0x77, 0x72, 0x22, 0x77,
- 0x73, 0x33, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33,
- 0x33, 0x33, 0x33, 0x30, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x55, 0x00, 0x00, 0x06, 0x66, 0x66,
- 0x66, 0x66, 0x11, 0x1a, 0xa3, 0x77, 0x72, 0x22,
- 0x77, 0x73, 0x3a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0x33,
- 0x33, 0x33, 0x33, 0xa0, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x11,
- 0x66, 0x66, 0x66, 0x66, 0x11, 0xa3, 0x77, 0x22,
- 0x22, 0x77, 0x33, 0x33, 0xaa, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0x33, 0x33,
- 0x33, 0x3a, 0xa1, 0x10, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x33,
- 0xaa, 0x11, 0x16, 0x66, 0x66, 0x61, 0x1a, 0x37,
- 0x22, 0x22, 0x77, 0x33, 0x3a, 0xaa, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xa3, 0x33, 0x33, 0x33,
- 0x3a, 0xa1, 0x11, 0x10, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x02, 0x22,
- 0x22, 0x77, 0x3a, 0x11, 0x66, 0x66, 0x66, 0x1a,
- 0x37, 0x22, 0x22, 0x77, 0x33, 0x3a, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0x33, 0x33, 0x3a,
- 0xa1, 0x11, 0x11, 0x10, 0x00, 0x00, 0x50, 0x00,
- 0x00, 0x05, 0x80, 0x50, 0x00, 0x00, 0x07, 0x72,
- 0x22, 0x22, 0x22, 0x73, 0xa1, 0x66, 0x66, 0x61,
- 0x1a, 0x77, 0x22, 0x27, 0x73, 0x33, 0xaa, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0x33, 0x3a, 0xaa,
- 0x11, 0x11, 0x1a, 0xa0, 0x08, 0x71, 0x05, 0x00,
- 0x00, 0x12, 0x22, 0x50, 0x00, 0x00, 0x07, 0x77,
- 0x77, 0x72, 0x22, 0x22, 0x27, 0x31, 0x16, 0x66,
- 0x61, 0x13, 0x77, 0x22, 0x77, 0x33, 0x3a, 0xaa,
- 0xaa, 0xaa, 0xaa, 0xa3, 0x33, 0x33, 0xaa, 0xa1,
- 0x11, 0x1a, 0x33, 0x70, 0x07, 0x2e, 0x70, 0x00,
- 0x01, 0x44, 0x42, 0x60, 0x00, 0x00, 0x02, 0x22,
- 0x22, 0x22, 0x22, 0x22, 0x22, 0x27, 0x31, 0x66,
- 0x66, 0x61, 0xa3, 0x72, 0x22, 0x77, 0x33, 0xaa,
- 0xaa, 0xaa, 0xa3, 0x33, 0x33, 0xaa, 0xaa, 0x11,
- 0x1a, 0x33, 0x77, 0x30, 0x04, 0x82, 0x40, 0x00,
- 0x54, 0x48, 0x54, 0x40, 0x00, 0x00, 0x01, 0xaa,
- 0x32, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x31,
- 0x66, 0x66, 0x11, 0x37, 0x22, 0x27, 0x73, 0x3a,
- 0xaa, 0xaa, 0xa3, 0x33, 0x3a, 0xaa, 0xaa, 0xaa,
- 0xa3, 0x77, 0xaa, 0x10, 0x50, 0x08, 0x46, 0x05,
- 0x54, 0x80, 0x50, 0x42, 0x00, 0x00, 0x08, 0x66,
- 0x66, 0x1a, 0x32, 0x22, 0x22, 0x22, 0x22, 0x27,
- 0x31, 0x66, 0x66, 0x13, 0x72, 0x22, 0x77, 0x33,
- 0xaa, 0xaa, 0xaa, 0x33, 0xaa, 0xa1, 0xaa, 0xa3,
- 0x37, 0xa1, 0x1a, 0x30, 0x50, 0x06, 0x26, 0x00,
- 0x54, 0x00, 0x00, 0x44, 0x00, 0x00, 0x08, 0xe2,
- 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0x22, 0x22,
- 0x27, 0xa6, 0x66, 0x61, 0xa7, 0x72, 0x27, 0x73,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33,
- 0x31, 0x11, 0x37, 0x70, 0x02, 0x00, 0xab, 0xbb,
- 0xb6, 0x00, 0x00, 0xf4, 0x00, 0x00, 0xee, 0xee,
- 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0x22,
- 0x22, 0x23, 0x16, 0x66, 0x1a, 0x37, 0x22, 0x77,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa3, 0x3a,
- 0x11, 0xa7, 0x33, 0x10, 0x04, 0x09, 0xbd, 0xdd,
- 0xbd, 0xd0, 0x04, 0x45, 0x00, 0x0e, 0xee, 0xee,
- 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0x22,
- 0x22, 0x22, 0x71, 0x66, 0x66, 0x13, 0x72, 0x27,
- 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0x11,
- 0xa3, 0x73, 0xa1, 0x60, 0x08, 0xbd, 0xdd, 0xdd,
- 0xdd, 0xdd, 0xdb, 0x90, 0x00, 0x02, 0xec, 0xee,
- 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xce, 0x22,
- 0x22, 0x22, 0x27, 0xa6, 0x66, 0x61, 0x37, 0x27,
- 0x1a, 0xaa, 0xaa, 0xaa, 0xaa, 0xa3, 0xa1, 0x1a,
- 0x33, 0xa1, 0x16, 0x60, 0x0b, 0xbd, 0xdd, 0xdd,
- 0xcd, 0xdd, 0xdd, 0xd9, 0x00, 0x00, 0xec, 0xcc,
- 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xce, 0xa2,
- 0x22, 0x22, 0x22, 0x7a, 0x66, 0x66, 0x13, 0x77,
- 0x1a, 0xaa, 0xaa, 0xaa, 0xaa, 0x3a, 0x11, 0x33,
- 0xaa, 0x11, 0x66, 0x60, 0x9b, 0xdd, 0xdd, 0xdd,
- 0xcd, 0xdd, 0xdb, 0xb9, 0x00, 0x00, 0xec, 0xcc,
- 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xee, 0x61,
- 0x72, 0x22, 0x22, 0x22, 0xa1, 0x66, 0x61, 0x37,
- 0x1a, 0xaa, 0xaa, 0xaa, 0xa3, 0xa1, 0x13, 0x3a,
- 0x11, 0x11, 0x11, 0x10, 0x5b, 0xdd, 0xdd, 0xdc,
- 0xdd, 0xdd, 0xbd, 0xd9, 0x00, 0x00, 0xec, 0xcc,
- 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xee, 0x86,
- 0x17, 0x22, 0x22, 0x22, 0x23, 0x16, 0x66, 0xaa,
- 0xaa, 0xa3, 0x3a, 0xaa, 0xaa, 0x1a, 0x3a, 0xa1,
- 0x11, 0x11, 0x1a, 0x70, 0x05, 0xbd, 0xdd, 0xdd,
- 0xdb, 0x5b, 0xdd, 0xb0, 0x00, 0x60, 0x2e, 0xcc,
- 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xe6, 0x88,
- 0x66, 0x32, 0x22, 0x22, 0x22, 0x36, 0x66, 0x11,
- 0x33, 0x33, 0x3a, 0xaa, 0x11, 0xaa, 0xaa, 0xa1,
- 0x11, 0x1a, 0x3a, 0x60, 0x02, 0x99, 0xbb, 0xb9,
- 0x9b, 0xbb, 0xbc, 0x22, 0x00, 0x86, 0x5e, 0xcc,
- 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xe1, 0x68,
- 0x86, 0x63, 0x22, 0x22, 0x22, 0x2a, 0x66, 0x66,
- 0x33, 0x33, 0xaa, 0xaa, 0x1a, 0xaa, 0xaa, 0x11,
- 0x1a, 0xa7, 0x68, 0x80, 0x02, 0x2b, 0xbd, 0xbb,
- 0xbb, 0xb9, 0x22, 0x22, 0x00, 0x06, 0x6e, 0xcc,
- 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xc7, 0xa6,
- 0x88, 0x86, 0x32, 0x22, 0x22, 0x27, 0xa6, 0x66,
- 0x33, 0x3a, 0xaa, 0xa1, 0xaa, 0xaa, 0xa1, 0x11,
- 0xa3, 0xa6, 0x88, 0x80, 0x02, 0x22, 0x9b, 0xbb,
- 0xbb, 0x22, 0x24, 0xf4, 0x60, 0x00, 0x0c, 0xcc,
- 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xc2, 0x21,
- 0x68, 0x88, 0x63, 0x22, 0x22, 0x22, 0x71, 0x66,
- 0x33, 0x3a, 0x11, 0x11, 0xaa, 0xaa, 0x11, 0xaa,
- 0x71, 0x88, 0x88, 0x00, 0x02, 0xe2, 0x26, 0x99,
- 0x22, 0x22, 0x4f, 0xf4, 0x40, 0x00, 0x0c, 0xcc,
- 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x22, 0x22,
- 0x16, 0x88, 0x86, 0xa2, 0x22, 0x22, 0x27, 0x11,
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- 0x25, 0x55, 0x95, 0x55, 0x6a, 0xa2, 0x2a, 0x88,
- 0x62, 0x27, 0x37, 0x38, 0x88, 0x87, 0x55, 0x59,
- 0x95, 0x58, 0x16, 0x88, 0x8a, 0x66, 0x63, 0x68,
- 0x86, 0x67, 0x66, 0x66, 0x68, 0x88, 0x12, 0x11,
- 0x88, 0x88, 0x72, 0x77, 0x78, 0x85, 0x58, 0x17,
- 0x23, 0x32, 0x55, 0x55, 0x81, 0x13, 0x73, 0x66,
- 0x62, 0x7a, 0xaa, 0x38, 0x88, 0x58, 0x27, 0x55,
- 0x58, 0x32, 0x38, 0x88, 0x81, 0x66, 0xa2, 0x88,
- 0x86, 0x61, 0x66, 0x61, 0x66, 0x68, 0x13, 0x11,
- 0x88, 0x88, 0x12, 0x22, 0x71, 0x85, 0x58, 0x62,
- 0x23, 0xa2, 0x68, 0x88, 0x81, 0x66, 0x88, 0x88,
- 0x63, 0x2a, 0xaa, 0x28, 0x88, 0x55, 0x86, 0x61,
- 0x66, 0x66, 0x68, 0x88, 0x66, 0x66, 0x77, 0x88,
- 0x68, 0x16, 0x66, 0x62, 0x66, 0x68, 0xa1, 0x61,
- 0x88, 0x88, 0x62, 0x22, 0x22, 0x85, 0x55, 0x83,
- 0x72, 0x37, 0xa8, 0x88, 0x61, 0x66, 0x85, 0x55,
- 0x86, 0x23, 0xaa, 0x71, 0x88, 0x85, 0x88, 0x66,
- 0x88, 0x86, 0x88, 0x88, 0x16, 0x61, 0x21, 0x88,
- 0x66, 0xa6, 0x86, 0x17, 0x66, 0x66, 0x31, 0x61,
- 0x88, 0x88, 0x87, 0x72, 0x22, 0x68, 0x55, 0x86,
- 0x77, 0x77, 0x36, 0x88, 0x13, 0x68, 0x85, 0x55,
- 0x58, 0x12, 0x73, 0x72, 0x76, 0x88, 0x88, 0x68,
- 0x88, 0x88, 0x88, 0x66, 0x36, 0x63, 0x26, 0x86,
- 0x86, 0x36, 0x86, 0x11, 0x66, 0x66, 0x76, 0x61,
- 0x88, 0x88, 0x81, 0x22, 0x22, 0x38, 0x85, 0x58,
- 0x37, 0x22, 0x21, 0x68, 0xa2, 0x31, 0x68, 0x55,
- 0x55, 0x81, 0x22, 0x22, 0xa8, 0x88, 0x88, 0x68,
- 0x86, 0x88, 0x68, 0x81, 0x36, 0x17, 0x21, 0x68,
- 0x86, 0x16, 0x66, 0x26, 0x66, 0x61, 0x36, 0x66,
- 0x68, 0x88, 0x86, 0x27, 0x22, 0x28, 0x88, 0x88,
- 0x17, 0x72, 0x2a, 0x66, 0xa2, 0x22, 0x36, 0x55,
- 0x55, 0x58, 0x37, 0x3a, 0x16, 0x66, 0x66, 0x66,
- 0x66, 0x18, 0x88, 0x67, 0x16, 0x12, 0x71, 0x68,
- 0x81, 0x68, 0x61, 0x76, 0x66, 0x6a, 0x16, 0x66,
- 0x88, 0x88, 0x86, 0x77, 0x22, 0x26, 0x88, 0x88,
- 0x13, 0x37, 0x71, 0x66, 0xa2, 0x33, 0x2a, 0x85,
- 0x55, 0x55, 0x17, 0x73, 0x16, 0x66, 0x66, 0x68,
- 0x63, 0x88, 0x88, 0xa2, 0x66, 0xa2, 0xa6, 0x88,
- 0x61, 0x68, 0x6a, 0x76, 0x66, 0x6a, 0x66, 0x6a
-};
-
-#endif
diff --git a/include/nand.h b/include/nand.h
deleted file mode 100644
index 23493f7e98..0000000000
--- a/include/nand.h
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * (C) Copyright 2005
- * 2N Telekomunikace, a.s. <www.2n.cz>
- * Ladislav Michl <michl@2n.cz>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _NAND_H_
-#define _NAND_H_
-
-#include <linux/mtd/compat.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/nand.h>
-
-typedef struct mtd_info nand_info_t;
-
-extern int nand_curr_device;
-extern nand_info_t nand_info[];
-
-static inline int nand_read(nand_info_t *info, ulong ofs, ulong *len, u_char *buf)
-{
- return info->read(info, ofs, *len, (size_t *)len, buf);
-}
-
-static inline int nand_write(nand_info_t *info, ulong ofs, ulong *len, u_char *buf)
-{
- return info->write(info, ofs, *len, (size_t *)len, buf);
-}
-
-static inline int nand_block_isbad(nand_info_t *info, ulong ofs)
-{
- return info->block_isbad(info, ofs);
-}
-
-static inline int nand_erase(nand_info_t *info, ulong off, ulong size)
-{
- struct erase_info instr;
-
- instr.mtd = info;
- instr.addr = off;
- instr.len = size;
- instr.callback = 0;
-
- return info->erase(info, &instr);
-}
-
-
-/*****************************************************************************
- * declarations from nand_util.c
- ****************************************************************************/
-
-struct nand_write_options {
- u_char *buffer; /* memory block containing image to write */
- ulong length; /* number of bytes to write */
- ulong offset; /* start address in NAND */
- int quiet; /* don't display progress messages */
- int autoplace; /* if true use auto oob layout */
- int forcejffs2; /* force jffs2 oob layout */
- int forceyaffs; /* force yaffs oob layout */
- int noecc; /* write without ecc */
- int writeoob; /* image contains oob data */
- int pad; /* pad to page size */
- int blockalign; /* 1|2|4 set multiple of eraseblocks
- * to align to */
-};
-
-typedef struct nand_write_options nand_write_options_t;
-
-struct nand_read_options {
- u_char *buffer; /* memory block in which read image is written*/
- ulong length; /* number of bytes to read */
- ulong offset; /* start address in NAND */
- int quiet; /* don't display progress messages */
- int readoob; /* put oob data in image */
-};
-
-typedef struct nand_read_options nand_read_options_t;
-
-struct nand_erase_options {
- ulong length; /* number of bytes to erase */
- ulong offset; /* first address in NAND to erase */
- int quiet; /* don't display progress messages */
- int jffs2; /* if true: format for jffs2 usage
- * (write appropriate cleanmarker blocks) */
- int scrub; /* if true, really clean NAND by erasing
- * bad blocks (UNSAFE) */
-};
-
-typedef struct nand_erase_options nand_erase_options_t;
-
-int nand_write_opts(nand_info_t *meminfo, const nand_write_options_t *opts);
-
-int nand_read_opts(nand_info_t *meminfo, const nand_read_options_t *opts);
-int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts);
-
-#define NAND_LOCK_STATUS_TIGHT 0x01
-#define NAND_LOCK_STATUS_LOCK 0x02
-#define NAND_LOCK_STATUS_UNLOCK 0x04
-
-int nand_lock( nand_info_t *meminfo, int tight );
-int nand_unlock( nand_info_t *meminfo, ulong start, ulong length );
-int nand_get_lock_status(nand_info_t *meminfo, ulong offset);
-
-#ifdef CFG_NAND_SELECT_DEVICE
-void board_nand_select_device(struct nand_chip *nand, int chip);
-#endif
-
-#endif
diff --git a/include/ns16550.h b/include/ns16550.h
deleted file mode 100644
index 34888a1028..0000000000
--- a/include/ns16550.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * NS16550 Serial Port
- * originally from linux source (arch/ppc/boot/ns16550.h)
- * modified slightly to
- * have addresses as offsets from CFG_ISA_BASE
- * added a few more definitions
- * added prototypes for ns16550.c
- * reduced no of com ports to 2
- * modifications (c) Rob Taylor, Flying Pig Systems. 2000.
- *
- * added support for port on 64-bit bus
- * by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems
- */
-
-#if (CFG_NS16550_REG_SIZE == 1)
-struct NS16550 {
- unsigned char rbr; /* 0 */
- unsigned char ier; /* 1 */
- unsigned char fcr; /* 2 */
- unsigned char lcr; /* 3 */
- unsigned char mcr; /* 4 */
- unsigned char lsr; /* 5 */
- unsigned char msr; /* 6 */
- unsigned char scr; /* 7 */
-#if defined(CONFIG_OMAP730)
- unsigned char mdr1; /* 8 */
- unsigned char reg9; /* 9 */
- unsigned char regA; /* A */
- unsigned char regB; /* B */
- unsigned char regC; /* C */
- unsigned char regD; /* D */
- unsigned char regE; /* E */
- unsigned char regF; /* F */
- unsigned char reg10; /* 10 */
- unsigned char ssr; /* 11*/
-#endif
-} __attribute__ ((packed));
-#elif (CFG_NS16550_REG_SIZE == 2)
-struct NS16550 {
- unsigned short rbr; /* 0 */
- unsigned short ier; /* 1 */
- unsigned short fcr; /* 2 */
- unsigned short lcr; /* 3 */
- unsigned short mcr; /* 4 */
- unsigned short lsr; /* 5 */
- unsigned short msr; /* 6 */
- unsigned short scr; /* 7 */
-} __attribute__ ((packed));
-#elif (CFG_NS16550_REG_SIZE == 4)
-struct NS16550 {
- unsigned long rbr; /* 0 r */
- unsigned long ier; /* 1 rw */
- unsigned long fcr; /* 2 w */
- unsigned long lcr; /* 3 rw */
- unsigned long mcr; /* 4 rw */
- unsigned long lsr; /* 5 r */
- unsigned long msr; /* 6 r */
- unsigned long scr; /* 7 rw */
-}; /* No need to pack an already aligned struct */
-#elif (CFG_NS16550_REG_SIZE == -4)
-struct NS16550 {
- unsigned char rbr; /* 0 */
- int pad1:24;
- unsigned char ier; /* 1 */
- int pad2:24;
- unsigned char fcr; /* 2 */
- int pad3:24;
- unsigned char lcr; /* 3 */
- int pad4:24;
- unsigned char mcr; /* 4 */
- int pad5:24;
- unsigned char lsr; /* 5 */
- int pad6:24;
- unsigned char msr; /* 6 */
- int pad7:24;
- unsigned char scr; /* 7 */
- int pad8:24;
-#if defined(CONFIG_OMAP)
- unsigned char mdr1; /* mode select reset TL16C750*/
-#endif
-#ifdef CONFIG_OMAP1510
- int pad9:24;
- unsigned long pad[10];
- unsigned char osc_12m_sel;
- int pad10:24;
-#endif
-} __attribute__ ((packed));
-#elif (CFG_NS16550_REG_SIZE == -8)
-struct NS16550 {
- unsigned char rbr; /* 0 */
- unsigned char pad0[7];
- unsigned char ier; /* 1 */
- unsigned char pad1[7];
- unsigned char fcr; /* 2 */
- unsigned char pad2[7];
- unsigned char lcr; /* 3 */
- unsigned char pad3[7];
- unsigned char mcr; /* 4 */
- unsigned char pad4[7];
- unsigned char lsr; /* 5 */
- unsigned char pad5[7];
- unsigned char msr; /* 6 */
- unsigned char pad6[7];
- unsigned char scr; /* 7 */
- unsigned char pad7[7];
-} __attribute__ ((packed));
-#else
-#error "Please define NS16550 registers size."
-#endif
-
-#define thr rbr
-#define iir fcr
-#define dll rbr
-#define dlm ier
-
-typedef volatile struct NS16550 *NS16550_t;
-
-#define FCR_FIFO_EN 0x01 /* Fifo enable */
-#define FCR_RXSR 0x02 /* Receiver soft reset */
-#define FCR_TXSR 0x04 /* Transmitter soft reset */
-
-#define MCR_DTR 0x01
-#define MCR_RTS 0x02
-#define MCR_DMA_EN 0x04
-#define MCR_TX_DFR 0x08
-
-#define LCR_WLS_MSK 0x03 /* character length select mask */
-#define LCR_WLS_5 0x00 /* 5 bit character length */
-#define LCR_WLS_6 0x01 /* 6 bit character length */
-#define LCR_WLS_7 0x02 /* 7 bit character length */
-#define LCR_WLS_8 0x03 /* 8 bit character length */
-#define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
-#define LCR_PEN 0x08 /* Parity eneble */
-#define LCR_EPS 0x10 /* Even Parity Select */
-#define LCR_STKP 0x20 /* Stick Parity */
-#define LCR_SBRK 0x40 /* Set Break */
-#define LCR_BKSE 0x80 /* Bank select enable */
-
-#define LSR_DR 0x01 /* Data ready */
-#define LSR_OE 0x02 /* Overrun */
-#define LSR_PE 0x04 /* Parity error */
-#define LSR_FE 0x08 /* Framing error */
-#define LSR_BI 0x10 /* Break */
-#define LSR_THRE 0x20 /* Xmit holding register empty */
-#define LSR_TEMT 0x40 /* Xmitter empty */
-#define LSR_ERR 0x80 /* Error */
-
-#ifdef CONFIG_OMAP1510
-#define OSC_12M_SEL 0x01 /* selects 6.5 * current clk div */
-#endif
-
-/* useful defaults for LCR */
-#define LCR_8N1 0x03
-
-void NS16550_init (NS16550_t com_port, int baud_divisor);
-void NS16550_putc (NS16550_t com_port, char c);
-char NS16550_getc (NS16550_t com_port);
-int NS16550_tstc (NS16550_t com_port);
-void NS16550_reinit (NS16550_t com_port, int baud_divisor);
diff --git a/include/pc_keyb.h b/include/pc_keyb.h
deleted file mode 100644
index 39f17351ef..0000000000
--- a/include/pc_keyb.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * include/linux/pc_keyb.h
- *
- * PC Keyboard And Keyboard Controller
- *
- * (c) 1997 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
- */
-
-/*
- * Configuration Switches
- */
-#undef KBD_REPORT_ERR /* Report keyboard errors */
-#define KBD_REPORT_UNKN /* Report unknown scan codes */
-#define KBD_REPORT_TIMEOUTS /* Report keyboard timeouts */
-#undef KBD_IS_FOCUS_9000 /* We have the brain-damaged FOCUS-9000 keyboard */
-#undef INITIALIZE_MOUSE /* Define if your PS/2 mouse needs initialization. */
-
-#define KBD_INIT_TIMEOUT 1000 /* Timeout in ms for initializing the keyboard */
-#define KBC_TIMEOUT 250 /* Timeout in ms for sending to keyboard controller */
-#define KBD_TIMEOUT 1000 /* Timeout in ms for keyboard command acknowledge */
-
-/*
- * Internal variables of the driver
- */
-extern unsigned char pckbd_read_mask;
-extern unsigned char aux_device_present;
-
-/*
- * Keyboard Controller Registers on normal PCs.
- */
-#define KBD_STATUS_REG 0x64 /* Status register (R) */
-#define KBD_CNTL_REG 0x64 /* Controller command register (W) */
-#define KBD_DATA_REG 0x60 /* Keyboard data register (R/W) */
-
-/*
- * Keyboard Controller Commands
- */
-#define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */
-#define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */
-#define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */
-#define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */
-#define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */
-#define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */
-#define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */
-#define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */
-#define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */
-#define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */
-#define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if
- initiated by the auxiliary device */
-#define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */
-
-/*
- * Keyboard Commands
- */
-#define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */
-#define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */
-#define KBD_CMD_ENABLE 0xF4 /* Enable scanning */
-#define KBD_CMD_DISABLE 0xF5 /* Disable scanning */
-#define KBD_CMD_RESET 0xFF /* Reset */
-
-/*
- * Keyboard Replies
- */
-#define KBD_REPLY_POR 0xAA /* Power on reset */
-#define KBD_REPLY_ACK 0xFA /* Command ACK */
-#define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */
-
-/*
- * Status Register Bits
- */
-#define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */
-#define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */
-#define KBD_STAT_SELFTEST 0x04 /* Self test successful */
-#define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */
-#define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */
-#define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */
-#define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */
-#define KBD_STAT_PERR 0x80 /* Parity error */
-
-#define AUX_STAT_OBF (KBD_STAT_OBF | KBD_STAT_MOUSE_OBF)
-
-/*
- * Controller Mode Register Bits
- */
-#define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */
-#define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */
-#define KBD_MODE_SYS 0x04 /* The system flag (?) */
-#define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */
-#define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */
-#define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */
-#define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */
-#define KBD_MODE_RFU 0x80
-
-/*
- * Mouse Commands
- */
-#define AUX_SET_RES 0xE8 /* Set resolution */
-#define AUX_SET_SCALE11 0xE6 /* Set 1:1 scaling */
-#define AUX_SET_SCALE21 0xE7 /* Set 2:1 scaling */
-#define AUX_GET_SCALE 0xE9 /* Get scaling factor */
-#define AUX_SET_STREAM 0xEA /* Set stream mode */
-#define AUX_SET_SAMPLE 0xF3 /* Set sample rate */
-#define AUX_ENABLE_DEV 0xF4 /* Enable aux device */
-#define AUX_DISABLE_DEV 0xF5 /* Disable aux device */
-#define AUX_RESET 0xFF /* Reset aux device */
-#define AUX_ACK 0xFA /* Command byte ACK. */
-
-#define AUX_BUF_SIZE 2048 /* This might be better divisible by
- three to make overruns stay in sync
- but then the read function would need
- a lock etc - ick */
-
diff --git a/include/pci.h b/include/pci.h
deleted file mode 100644
index 250954707e..0000000000
--- a/include/pci.h
+++ /dev/null
@@ -1,528 +0,0 @@
-/*
- * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Andreas Heppel <aheppel@sysgo.de>
- *
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * aloong with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _PCI_H
-#define _PCI_H
-
-/*
- * Under PCI, each device has 256 bytes of configuration address space,
- * of which the first 64 bytes are standardized as follows:
- */
-#define PCI_VENDOR_ID 0x00 /* 16 bits */
-#define PCI_DEVICE_ID 0x02 /* 16 bits */
-#define PCI_COMMAND 0x04 /* 16 bits */
-#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
-#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
-#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
-#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
-#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
-#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
-#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
-#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
-#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
-#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
-
-#define PCI_STATUS 0x06 /* 16 bits */
-#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
-#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
-#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
-#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
-#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
-#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
-#define PCI_STATUS_DEVSEL_FAST 0x000
-#define PCI_STATUS_DEVSEL_MEDIUM 0x200
-#define PCI_STATUS_DEVSEL_SLOW 0x400
-#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
-#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
-#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
-#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
-#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
-
-#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
- revision */
-#define PCI_REVISION_ID 0x08 /* Revision ID */
-#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
-#define PCI_CLASS_DEVICE 0x0a /* Device class */
-#define PCI_CLASS_CODE 0x0b /* Device class code */
-#define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */
-
-#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
-#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
-#define PCI_HEADER_TYPE 0x0e /* 8 bits */
-#define PCI_HEADER_TYPE_NORMAL 0
-#define PCI_HEADER_TYPE_BRIDGE 1
-#define PCI_HEADER_TYPE_CARDBUS 2
-
-#define PCI_BIST 0x0f /* 8 bits */
-#define PCI_BIST_CODE_MASK 0x0f /* Return result */
-#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
-#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
-
-/*
- * Base addresses specify locations in memory or I/O space.
- * Decoded size can be determined by writing a value of
- * 0xffffffff to the register, and reading it back. Only
- * 1 bits are decoded.
- */
-#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
-#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
-#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
-#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
-#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
-#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
-#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
-#define PCI_BASE_ADDRESS_SPACE_IO 0x01
-#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
-#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
-#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
-#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
-#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
-#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
-#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
-#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
-/* bit 1 is reserved if address_space = 1 */
-
-/* Header type 0 (normal devices) */
-#define PCI_CARDBUS_CIS 0x28
-#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
-#define PCI_SUBSYSTEM_ID 0x2e
-#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
-#define PCI_ROM_ADDRESS_ENABLE 0x01
-#define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
-
-#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
-
-/* 0x35-0x3b are reserved */
-#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
-#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
-#define PCI_MIN_GNT 0x3e /* 8 bits */
-#define PCI_MAX_LAT 0x3f /* 8 bits */
-
-/* Header type 1 (PCI-to-PCI bridges) */
-#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
-#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
-#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
-#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
-#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
-#define PCI_IO_LIMIT 0x1d
-#define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
-#define PCI_IO_RANGE_TYPE_16 0x00
-#define PCI_IO_RANGE_TYPE_32 0x01
-#define PCI_IO_RANGE_MASK ~0x0f
-#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
-#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
-#define PCI_MEMORY_LIMIT 0x22
-#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
-#define PCI_MEMORY_RANGE_MASK ~0x0f
-#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
-#define PCI_PREF_MEMORY_LIMIT 0x26
-#define PCI_PREF_RANGE_TYPE_MASK 0x0f
-#define PCI_PREF_RANGE_TYPE_32 0x00
-#define PCI_PREF_RANGE_TYPE_64 0x01
-#define PCI_PREF_RANGE_MASK ~0x0f
-#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
-#define PCI_PREF_LIMIT_UPPER32 0x2c
-#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
-#define PCI_IO_LIMIT_UPPER16 0x32
-/* 0x34 same as for htype 0 */
-/* 0x35-0x3b is reserved */
-#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
-/* 0x3c-0x3d are same as for htype 0 */
-#define PCI_BRIDGE_CONTROL 0x3e
-#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
-#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
-#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
-#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
-#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
-#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
-#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
-
-/* From 440ep */
-#define PCI_ERREN 0x48 /* Error Enable */
-#define PCI_ERRSTS 0x49 /* Error Status */
-#define PCI_BRDGOPT1 0x4A /* PCI Bridge Options 1 */
-#define PCI_PLBSESR0 0x4C /* PCI PLB Slave Error Syndrome 0 */
-#define PCI_PLBSESR1 0x50 /* PCI PLB Slave Error Syndrome 1 */
-#define PCI_PLBSEAR 0x54 /* PCI PLB Slave Error Address */
-#define PCI_CAPID 0x58 /* Capability Identifier */
-#define PCI_NEXTITEMPTR 0x59 /* Next Item Pointer */
-#define PCI_PMC 0x5A /* Power Management Capabilities */
-#define PCI_PMCSR 0x5C /* Power Management Control Status */
-#define PCI_PMCSRBSE 0x5E /* PMCSR PCI to PCI Bridge Support Extensions */
-#define PCI_BRDGOPT2 0x60 /* PCI Bridge Options 2 */
-#define PCI_PMSCRR 0x64 /* Power Management State Change Request Re. */
-
-/* Header type 2 (CardBus bridges) */
-#define PCI_CB_CAPABILITY_LIST 0x14
-/* 0x15 reserved */
-#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
-#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
-#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
-#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
-#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
-#define PCI_CB_MEMORY_BASE_0 0x1c
-#define PCI_CB_MEMORY_LIMIT_0 0x20
-#define PCI_CB_MEMORY_BASE_1 0x24
-#define PCI_CB_MEMORY_LIMIT_1 0x28
-#define PCI_CB_IO_BASE_0 0x2c
-#define PCI_CB_IO_BASE_0_HI 0x2e
-#define PCI_CB_IO_LIMIT_0 0x30
-#define PCI_CB_IO_LIMIT_0_HI 0x32
-#define PCI_CB_IO_BASE_1 0x34
-#define PCI_CB_IO_BASE_1_HI 0x36
-#define PCI_CB_IO_LIMIT_1 0x38
-#define PCI_CB_IO_LIMIT_1_HI 0x3a
-#define PCI_CB_IO_RANGE_MASK ~0x03
-/* 0x3c-0x3d are same as for htype 0 */
-#define PCI_CB_BRIDGE_CONTROL 0x3e
-#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
-#define PCI_CB_BRIDGE_CTL_SERR 0x02
-#define PCI_CB_BRIDGE_CTL_ISA 0x04
-#define PCI_CB_BRIDGE_CTL_VGA 0x08
-#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
-#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
-#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
-#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
-#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
-#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
-#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
-#define PCI_CB_SUBSYSTEM_ID 0x42
-#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
-/* 0x48-0x7f reserved */
-
-/* Capability lists */
-
-#define PCI_CAP_LIST_ID 0 /* Capability ID */
-#define PCI_CAP_ID_PM 0x01 /* Power Management */
-#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
-#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
-#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
-#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
-#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
-#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
-#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
-#define PCI_CAP_SIZEOF 4
-
-/* Power Management Registers */
-
-#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
-#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
-#define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
-#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
-#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
-#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
-#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
-#define PCI_PM_CTRL 4 /* PM control and status register */
-#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
-#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
-#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
-#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
-#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
-#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
-#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
-#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
-#define PCI_PM_DATA_REGISTER 7 /* (??) */
-#define PCI_PM_SIZEOF 8
-
-/* AGP registers */
-
-#define PCI_AGP_VERSION 2 /* BCD version number */
-#define PCI_AGP_RFU 3 /* Rest of capability flags */
-#define PCI_AGP_STATUS 4 /* Status register */
-#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
-#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
-#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
-#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
-#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
-#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
-#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
-#define PCI_AGP_COMMAND 8 /* Control register */
-#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
-#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
-#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
-#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
-#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
-#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
-#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */
-#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */
-#define PCI_AGP_SIZEOF 12
-
-/* PCI-X registers */
-
-#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
-#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
-#define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */
-#define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */
-#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
-
-
-/* Slot Identification */
-
-#define PCI_SID_ESR 2 /* Expansion Slot Register */
-#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
-#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
-#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
-
-/* Message Signalled Interrupts registers */
-
-#define PCI_MSI_FLAGS 2 /* Various flags */
-#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
-#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
-#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
-#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
-#define PCI_MSI_RFU 3 /* Rest of capability flags */
-#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
-#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
-#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
-#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
-
-#define PCI_MAX_PCI_DEVICES 32
-#define PCI_MAX_PCI_FUNCTIONS 8
-
-/* Include the ID list */
-
-#include <pci_ids.h>
-
-struct pci_region {
- unsigned long bus_start; /* Start on the bus */
- unsigned long phys_start; /* Start in physical address space */
- unsigned long size; /* Size */
- unsigned long flags; /* Resource flags */
-
- unsigned long bus_lower;
-};
-
-#define PCI_REGION_MEM 0x00000000 /* PCI memory space */
-#define PCI_REGION_IO 0x00000001 /* PCI IO space */
-#define PCI_REGION_TYPE 0x00000001
-#define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */
-
-#define PCI_REGION_MEMORY 0x00000100 /* System memory */
-#define PCI_REGION_RO 0x00000200 /* Read-only memory */
-
-extern __inline__ void pci_set_region(struct pci_region *reg,
- unsigned long bus_start,
- unsigned long phys_start,
- unsigned long size,
- unsigned long flags) {
- reg->bus_start = bus_start;
- reg->phys_start = phys_start;
- reg->size = size;
- reg->flags = flags;
-}
-
-typedef int pci_dev_t;
-
-#define PCI_BUS(d) (((d) >> 16) & 0xff)
-#define PCI_DEV(d) (((d) >> 11) & 0x1f)
-#define PCI_FUNC(d) (((d) >> 8) & 0x7)
-#define PCI_BDF(b,d,f) ((b) << 16 | (d) << 11 | (f) << 8)
-
-#define PCI_ANY_ID (~0)
-
-struct pci_device_id {
- unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
-};
-
-struct pci_controller;
-
-struct pci_config_table {
- unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
- unsigned int class; /* Class ID, or PCI_ANY_ID */
- unsigned int bus; /* Bus number, or PCI_ANY_ID */
- unsigned int dev; /* Device number, or PCI_ANY_ID */
- unsigned int func; /* Function number, or PCI_ANY_ID */
-
- void (*config_device)(struct pci_controller* hose, pci_dev_t dev,
- struct pci_config_table *);
- unsigned long priv[3];
-};
-
-extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev,
- struct pci_config_table *);
-extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
- struct pci_config_table *);
-
-#define MAX_PCI_REGIONS 7
-
-/*
- * Structure of a PCI controller (host bridge)
- */
-struct pci_controller {
- struct pci_controller *next;
-
- int first_busno;
- int last_busno;
-
- volatile unsigned int *cfg_addr;
- volatile unsigned char *cfg_data;
-
- struct pci_region regions[MAX_PCI_REGIONS];
- int region_count;
-
- struct pci_config_table *config_table;
-
- void (*fixup_irq)(struct pci_controller *, pci_dev_t);
-
- /* Low-level architecture-dependent routines */
- int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *);
- int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *);
- int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *);
- int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8);
- int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16);
- int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32);
-
- /* Used by auto config */
- struct pci_region *pci_mem, *pci_io, *pci_prefetch;
-
- /* Used by ppc405 autoconfig*/
- struct pci_region *pci_fb;
- int current_busno;
-};
-
-extern __inline__ void pci_set_ops(struct pci_controller *hose,
- int (*read_byte)(struct pci_controller*,
- pci_dev_t, int where, u8 *),
- int (*read_word)(struct pci_controller*,
- pci_dev_t, int where, u16 *),
- int (*read_dword)(struct pci_controller*,
- pci_dev_t, int where, u32 *),
- int (*write_byte)(struct pci_controller*,
- pci_dev_t, int where, u8),
- int (*write_word)(struct pci_controller*,
- pci_dev_t, int where, u16),
- int (*write_dword)(struct pci_controller*,
- pci_dev_t, int where, u32)) {
- hose->read_byte = read_byte;
- hose->read_word = read_word;
- hose->read_dword = read_dword;
- hose->write_byte = write_byte;
- hose->write_word = write_word;
- hose->write_dword = write_dword;
-}
-
-extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
-
-extern unsigned long pci_hose_bus_to_phys(struct pci_controller* hose,
- unsigned long addr, unsigned long flags);
-extern unsigned long pci_hose_phys_to_bus(struct pci_controller* hose,
- unsigned long addr, unsigned long flags);
-
-#define pci_phys_to_bus(dev, addr, flags) \
- pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
-#define pci_bus_to_phys(dev, addr, flags) \
- pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
-
-#define pci_phys_to_mem(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
-#define pci_mem_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
-#define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
-#define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
-
-extern int pci_hose_read_config_byte(struct pci_controller *hose,
- pci_dev_t dev, int where, u8 *val);
-extern int pci_hose_read_config_word(struct pci_controller *hose,
- pci_dev_t dev, int where, u16 *val);
-extern int pci_hose_read_config_dword(struct pci_controller *hose,
- pci_dev_t dev, int where, u32 *val);
-extern int pci_hose_write_config_byte(struct pci_controller *hose,
- pci_dev_t dev, int where, u8 val);
-extern int pci_hose_write_config_word(struct pci_controller *hose,
- pci_dev_t dev, int where, u16 val);
-extern int pci_hose_write_config_dword(struct pci_controller *hose,
- pci_dev_t dev, int where, u32 val);
-
-extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val);
-extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val);
-extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val);
-extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val);
-extern int pci_write_config_word(pci_dev_t dev, int where, u16 val);
-extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val);
-
-extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose,
- pci_dev_t dev, int where, u8 *val);
-extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose,
- pci_dev_t dev, int where, u16 *val);
-extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose,
- pci_dev_t dev, int where, u8 val);
-extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose,
- pci_dev_t dev, int where, u16 val);
-
-extern void pci_register_hose(struct pci_controller* hose);
-extern struct pci_controller* pci_bus_to_hose(int bus);
-
-extern int pci_hose_scan(struct pci_controller *hose);
-extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);
-
-extern void pciauto_region_init(struct pci_region* res);
-extern void pciauto_region_align(struct pci_region *res, unsigned long size);
-extern int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar);
-extern void pciauto_setup_device(struct pci_controller *hose,
- pci_dev_t dev, int bars_num,
- struct pci_region *mem,
- struct pci_region *prefetch,
- struct pci_region *io);
-int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
-
-extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index);
-extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);
-extern pci_dev_t pci_find_class(int wanted_class, int wanted_sub_code,
- int wanted_prog_if, int index);
-
-extern int pci_hose_config_device(struct pci_controller *hose,
- pci_dev_t dev,
- unsigned long io,
- unsigned long mem,
- unsigned long command);
-
-#ifdef CONFIG_MPC824X
-extern void pci_mpc824x_init (struct pci_controller *hose);
-#endif
-
-#ifdef CONFIG_MPC85xx
-extern void pci_mpc85xx_init (struct pci_controller *hose);
-#endif
-
-void pci_init (void);
-void pci_init_board(void);
-void pciinfo (int, int);
-
-#if defined(CONFIG_PCI) && defined(CONFIG_440)
-# if defined(CFG_PCI_PRE_INIT)
- int pci_pre_init (struct pci_controller * );
-# endif
-# if defined(CFG_PCI_TARGET_INIT)
- void pci_target_init (struct pci_controller *);
-# endif
-# if defined(CFG_PCI_MASTER_INIT)
- void pci_master_init (struct pci_controller *);
-# endif
- int is_pci_host (struct pci_controller *);
-#if defined(CONFIG_440SPE)
- void pcie_setup_hoses(void);
-#endif
-#endif
-
-#endif /* _PCI_H */
diff --git a/include/pci_ids.h b/include/pci_ids.h
deleted file mode 100644
index 3b10452416..0000000000
--- a/include/pci_ids.h
+++ /dev/null
@@ -1,2052 +0,0 @@
-/*
- * PCI Class, Vendor and Device IDs
- *
- * Please keep sorted.
- */
-
-/* Device classes and subclasses */
-
-#define PCI_CLASS_NOT_DEFINED 0x0000
-#define PCI_CLASS_NOT_DEFINED_VGA 0x0001
-
-#define PCI_BASE_CLASS_STORAGE 0x01
-#define PCI_CLASS_STORAGE_SCSI 0x0100
-#define PCI_CLASS_STORAGE_IDE 0x0101
-#define PCI_CLASS_STORAGE_FLOPPY 0x0102
-#define PCI_CLASS_STORAGE_IPI 0x0103
-#define PCI_CLASS_STORAGE_RAID 0x0104
-#define PCI_CLASS_STORAGE_OTHER 0x0180
-
-#define PCI_BASE_CLASS_NETWORK 0x02
-#define PCI_CLASS_NETWORK_ETHERNET 0x0200
-#define PCI_CLASS_NETWORK_TOKEN_RING 0x0201
-#define PCI_CLASS_NETWORK_FDDI 0x0202
-#define PCI_CLASS_NETWORK_ATM 0x0203
-#define PCI_CLASS_NETWORK_OTHER 0x0280
-
-#define PCI_BASE_CLASS_DISPLAY 0x03
-#define PCI_CLASS_DISPLAY_VGA 0x0300
-#define PCI_CLASS_DISPLAY_XGA 0x0301
-#define PCI_CLASS_DISPLAY_3D 0x0302
-#define PCI_CLASS_DISPLAY_OTHER 0x0380
-
-#define PCI_BASE_CLASS_MULTIMEDIA 0x04
-#define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400
-#define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401
-#define PCI_CLASS_MULTIMEDIA_PHONE 0x0402
-#define PCI_CLASS_MULTIMEDIA_OTHER 0x0480
-
-#define PCI_BASE_CLASS_MEMORY 0x05
-#define PCI_CLASS_MEMORY_RAM 0x0500
-#define PCI_CLASS_MEMORY_FLASH 0x0501
-#define PCI_CLASS_MEMORY_OTHER 0x0580
-
-#define PCI_BASE_CLASS_BRIDGE 0x06
-#define PCI_CLASS_BRIDGE_HOST 0x0600
-#define PCI_CLASS_BRIDGE_ISA 0x0601
-#define PCI_CLASS_BRIDGE_EISA 0x0602
-#define PCI_CLASS_BRIDGE_MC 0x0603
-#define PCI_CLASS_BRIDGE_PCI 0x0604
-#define PCI_CLASS_BRIDGE_PCMCIA 0x0605
-#define PCI_CLASS_BRIDGE_NUBUS 0x0606
-#define PCI_CLASS_BRIDGE_CARDBUS 0x0607
-#define PCI_CLASS_BRIDGE_RACEWAY 0x0608
-#define PCI_CLASS_BRIDGE_OTHER 0x0680
-
-#define PCI_BASE_CLASS_COMMUNICATION 0x07
-#define PCI_CLASS_COMMUNICATION_SERIAL 0x0700
-#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
-#define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702
-#define PCI_CLASS_COMMUNICATION_MODEM 0x0703
-#define PCI_CLASS_COMMUNICATION_OTHER 0x0780
-
-#define PCI_BASE_CLASS_SYSTEM 0x08
-#define PCI_CLASS_SYSTEM_PIC 0x0800
-#define PCI_CLASS_SYSTEM_DMA 0x0801
-#define PCI_CLASS_SYSTEM_TIMER 0x0802
-#define PCI_CLASS_SYSTEM_RTC 0x0803
-#define PCI_CLASS_SYSTEM_PCI_HOTPLUG 0x0804
-#define PCI_CLASS_SYSTEM_OTHER 0x0880
-
-#define PCI_BASE_CLASS_INPUT 0x09
-#define PCI_CLASS_INPUT_KEYBOARD 0x0900
-#define PCI_CLASS_INPUT_PEN 0x0901
-#define PCI_CLASS_INPUT_MOUSE 0x0902
-#define PCI_CLASS_INPUT_SCANNER 0x0903
-#define PCI_CLASS_INPUT_GAMEPORT 0x0904
-#define PCI_CLASS_INPUT_OTHER 0x0980
-
-#define PCI_BASE_CLASS_DOCKING 0x0a
-#define PCI_CLASS_DOCKING_GENERIC 0x0a00
-#define PCI_CLASS_DOCKING_OTHER 0x0a80
-
-#define PCI_BASE_CLASS_PROCESSOR 0x0b
-#define PCI_CLASS_PROCESSOR_386 0x0b00
-#define PCI_CLASS_PROCESSOR_486 0x0b01
-#define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02
-#define PCI_CLASS_PROCESSOR_ALPHA 0x0b10
-#define PCI_CLASS_PROCESSOR_POWERPC 0x0b20
-#define PCI_CLASS_PROCESSOR_MIPS 0x0b30
-#define PCI_CLASS_PROCESSOR_CO 0x0b40
-
-#define PCI_BASE_CLASS_SERIAL 0x0c
-#define PCI_CLASS_SERIAL_FIREWIRE 0x0c00
-#define PCI_CLASS_SERIAL_ACCESS 0x0c01
-#define PCI_CLASS_SERIAL_SSA 0x0c02
-#define PCI_CLASS_SERIAL_USB 0x0c03
-#define PCI_CLASS_SERIAL_FIBER 0x0c04
-#define PCI_CLASS_SERIAL_SMBUS 0x0c05
-
-#define PCI_BASE_CLASS_INTELLIGENT 0x0e
-#define PCI_CLASS_INTELLIGENT_I2O 0x0e00
-
-#define PCI_BASE_CLASS_SATELLITE 0x0f
-#define PCI_CLASS_SATELLITE_TV 0x0f00
-#define PCI_CLASS_SATELLITE_AUDIO 0x0f01
-#define PCI_CLASS_SATELLITE_VOICE 0x0f03
-#define PCI_CLASS_SATELLITE_DATA 0x0f04
-
-#define PCI_BASE_CLASS_CRYPT 0x10
-#define PCI_CLASS_CRYPT_NETWORK 0x1000
-#define PCI_CLASS_CRYPT_ENTERTAINMENT 0x1001
-#define PCI_CLASS_CRYPT_OTHER 0x1080
-
-#define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11
-#define PCI_CLASS_SP_DPIO 0x1100
-#define PCI_CLASS_SP_OTHER 0x1180
-
-#define PCI_CLASS_OTHERS 0xff
-
-/* Vendors and devices. Sort key: vendor first, device next. */
-
-#define PCI_VENDOR_ID_DYNALINK 0x0675
-#define PCI_DEVICE_ID_DYNALINK_IS64PH 0x1702
-
-#define PCI_VENDOR_ID_BERKOM 0x0871
-#define PCI_DEVICE_ID_BERKOM_A1T 0xffa1
-#define PCI_DEVICE_ID_BERKOM_T_CONCEPT 0xffa2
-#define PCI_DEVICE_ID_BERKOM_A4T 0xffa4
-#define PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO 0xffa8
-
-#define PCI_VENDOR_ID_COMPAQ 0x0e11
-#define PCI_DEVICE_ID_COMPAQ_TOKENRING 0x0508
-#define PCI_DEVICE_ID_COMPAQ_1280 0x3033
-#define PCI_DEVICE_ID_COMPAQ_TRIFLEX 0x4000
-#define PCI_DEVICE_ID_COMPAQ_6010 0x6010
-#define PCI_DEVICE_ID_COMPAQ_TACHYON 0xa0fc
-#define PCI_DEVICE_ID_COMPAQ_SMART2P 0xae10
-#define PCI_DEVICE_ID_COMPAQ_NETEL100 0xae32
-#define PCI_DEVICE_ID_COMPAQ_TRIFLEX_IDE 0xae33
-#define PCI_DEVICE_ID_COMPAQ_NETEL10 0xae34
-#define PCI_DEVICE_ID_COMPAQ_NETFLEX3I 0xae35
-#define PCI_DEVICE_ID_COMPAQ_NETEL100D 0xae40
-#define PCI_DEVICE_ID_COMPAQ_NETEL100PI 0xae43
-#define PCI_DEVICE_ID_COMPAQ_NETEL100I 0xb011
-#define PCI_DEVICE_ID_COMPAQ_CISS 0xb060
-#define PCI_DEVICE_ID_COMPAQ_CISSB 0xb178
-#define PCI_DEVICE_ID_COMPAQ_CISSC 0x0046
-#define PCI_DEVICE_ID_COMPAQ_THUNDER 0xf130
-#define PCI_DEVICE_ID_COMPAQ_NETFLEX3B 0xf150
-
-#define PCI_VENDOR_ID_NCR 0x1000
-#define PCI_VENDOR_ID_LSI_LOGIC 0x1000
-#define PCI_DEVICE_ID_NCR_53C810 0x0001
-#define PCI_DEVICE_ID_NCR_53C820 0x0002
-#define PCI_DEVICE_ID_NCR_53C825 0x0003
-#define PCI_DEVICE_ID_NCR_53C815 0x0004
-#define PCI_DEVICE_ID_LSI_53C810AP 0x0005
-#define PCI_DEVICE_ID_NCR_53C860 0x0006
-#define PCI_DEVICE_ID_LSI_53C1510 0x000a
-#define PCI_DEVICE_ID_NCR_53C896 0x000b
-#define PCI_DEVICE_ID_NCR_53C895 0x000c
-#define PCI_DEVICE_ID_NCR_53C885 0x000d
-#define PCI_DEVICE_ID_NCR_53C875 0x000f
-#define PCI_DEVICE_ID_NCR_53C1510 0x0010
-#define PCI_DEVICE_ID_LSI_53C895A 0x0012
-#define PCI_DEVICE_ID_LSI_53C875A 0x0013
-#define PCI_DEVICE_ID_LSI_53C1010_33 0x0020
-#define PCI_DEVICE_ID_LSI_53C1010_66 0x0021
-#define PCI_DEVICE_ID_LSI_53C1030 0x0030
-#define PCI_DEVICE_ID_LSI_53C1035 0x0040
-#define PCI_DEVICE_ID_NCR_53C875J 0x008f
-#define PCI_DEVICE_ID_LSI_FC909 0x0621
-#define PCI_DEVICE_ID_LSI_FC929 0x0622
-#define PCI_DEVICE_ID_LSI_FC929_LAN 0x0623
-#define PCI_DEVICE_ID_LSI_FC919 0x0624
-#define PCI_DEVICE_ID_LSI_FC919_LAN 0x0625
-#define PCI_DEVICE_ID_LSI_FC929X 0x0626
-#define PCI_DEVICE_ID_LSI_FC919X 0x0628
-#define PCI_DEVICE_ID_NCR_YELLOWFIN 0x0701
-#define PCI_DEVICE_ID_LSI_61C102 0x0901
-#define PCI_DEVICE_ID_LSI_63C815 0x1000
-
-#define PCI_VENDOR_ID_ATI 0x1002
-/* Mach64 */
-#define PCI_DEVICE_ID_ATI_68800 0x4158
-#define PCI_DEVICE_ID_ATI_215CT222 0x4354
-#define PCI_DEVICE_ID_ATI_210888CX 0x4358
-#define PCI_DEVICE_ID_ATI_215ET222 0x4554
-/* Mach64 / Rage */
-#define PCI_DEVICE_ID_ATI_215GB 0x4742
-#define PCI_DEVICE_ID_ATI_215GD 0x4744
-#define PCI_DEVICE_ID_ATI_215GI 0x4749
-#define PCI_DEVICE_ID_ATI_215GP 0x4750
-#define PCI_DEVICE_ID_ATI_215GQ 0x4751
-#define PCI_DEVICE_ID_ATI_215XL 0x4752
-#define PCI_DEVICE_ID_ATI_215GT 0x4754
-#define PCI_DEVICE_ID_ATI_215GTB 0x4755
-#define PCI_DEVICE_ID_ATI_215_IV 0x4756
-#define PCI_DEVICE_ID_ATI_215_IW 0x4757
-#define PCI_DEVICE_ID_ATI_215_IZ 0x475A
-#define PCI_DEVICE_ID_ATI_210888GX 0x4758
-#define PCI_DEVICE_ID_ATI_215_LB 0x4c42
-#define PCI_DEVICE_ID_ATI_215_LD 0x4c44
-#define PCI_DEVICE_ID_ATI_215_LG 0x4c47
-#define PCI_DEVICE_ID_ATI_215_LI 0x4c49
-#define PCI_DEVICE_ID_ATI_215_LM 0x4c4D
-#define PCI_DEVICE_ID_ATI_215_LN 0x4c4E
-#define PCI_DEVICE_ID_ATI_215_LR 0x4c52
-#define PCI_DEVICE_ID_ATI_215_LS 0x4c53
-#define PCI_DEVICE_ID_ATI_264_LT 0x4c54
-/* Mach64 VT */
-#define PCI_DEVICE_ID_ATI_264VT 0x5654
-#define PCI_DEVICE_ID_ATI_264VU 0x5655
-#define PCI_DEVICE_ID_ATI_264VV 0x5656
-/* Rage128 Pro GL */
-#define PCI_DEVICE_ID_ATI_Rage128_PA 0x5041
-#define PCI_DEVICE_ID_ATI_Rage128_PB 0x5042
-#define PCI_DEVICE_ID_ATI_Rage128_PC 0x5043
-#define PCI_DEVICE_ID_ATI_Rage128_PD 0x5044
-#define PCI_DEVICE_ID_ATI_Rage128_PE 0x5045
-#define PCI_DEVICE_ID_ATI_RAGE128_PF 0x5046
-/* Rage128 Pro VR */
-#define PCI_DEVICE_ID_ATI_RAGE128_PG 0x5047
-#define PCI_DEVICE_ID_ATI_RAGE128_PH 0x5048
-#define PCI_DEVICE_ID_ATI_RAGE128_PI 0x5049
-#define PCI_DEVICE_ID_ATI_RAGE128_PJ 0x504A
-#define PCI_DEVICE_ID_ATI_RAGE128_PK 0x504B
-#define PCI_DEVICE_ID_ATI_RAGE128_PL 0x504C
-#define PCI_DEVICE_ID_ATI_RAGE128_PM 0x504D
-#define PCI_DEVICE_ID_ATI_RAGE128_PN 0x504E
-#define PCI_DEVICE_ID_ATI_RAGE128_PO 0x504F
-#define PCI_DEVICE_ID_ATI_RAGE128_PP 0x5050
-#define PCI_DEVICE_ID_ATI_RAGE128_PQ 0x5051
-#define PCI_DEVICE_ID_ATI_RAGE128_PR 0x5052
-#define PCI_DEVICE_ID_ATI_RAGE128_TR 0x5452
-#define PCI_DEVICE_ID_ATI_RAGE128_PS 0x5053
-#define PCI_DEVICE_ID_ATI_RAGE128_PT 0x5054
-#define PCI_DEVICE_ID_ATI_RAGE128_PU 0x5055
-#define PCI_DEVICE_ID_ATI_RAGE128_PV 0x5056
-#define PCI_DEVICE_ID_ATI_RAGE128_PW 0x5057
-#define PCI_DEVICE_ID_ATI_RAGE128_PX 0x5058
-/* Rage128 GL */
-#define PCI_DEVICE_ID_ATI_RAGE128_RE 0x5245
-#define PCI_DEVICE_ID_ATI_RAGE128_RF 0x5246
-#define PCI_DEVICE_ID_ATI_RAGE128_RG 0x534b
-#define PCI_DEVICE_ID_ATI_RAGE128_RH 0x534c
-#define PCI_DEVICE_ID_ATI_RAGE128_RI 0x534d
-/* Rage128 VR */
-#define PCI_DEVICE_ID_ATI_RAGE128_RK 0x524b
-#define PCI_DEVICE_ID_ATI_RAGE128_RL 0x524c
-#define PCI_DEVICE_ID_ATI_RAGE128_RM 0x5345
-#define PCI_DEVICE_ID_ATI_RAGE128_RN 0x5346
-#define PCI_DEVICE_ID_ATI_RAGE128_RO 0x5347
-/* Rage128 M3 */
-#define PCI_DEVICE_ID_ATI_RAGE128_LE 0x4c45
-#define PCI_DEVICE_ID_ATI_RAGE128_LF 0x4c46
-/* Rage128 Pro Ultra */
-#define PCI_DEVICE_ID_ATI_RAGE128_U1 0x5446
-#define PCI_DEVICE_ID_ATI_RAGE128_U2 0x544C
-#define PCI_DEVICE_ID_ATI_RAGE128_U3 0x5452
-/* Rage M4 */
-#define PCI_DEVICE_ID_ATI_RADEON_LE 0x4d45
-#define PCI_DEVICE_ID_ATI_RADEON_LF 0x4d46
-/* Radeon R100 */
-#define PCI_DEVICE_ID_ATI_RADEON_QD 0x5144
-#define PCI_DEVICE_ID_ATI_RADEON_QE 0x5145
-#define PCI_DEVICE_ID_ATI_RADEON_QF 0x5146
-#define PCI_DEVICE_ID_ATI_RADEON_QG 0x5147
-/* Radeon RV100 (VE) */
-#define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159
-#define PCI_DEVICE_ID_ATI_RADEON_QZ 0x515a
-/* Radeon R200 (8500) */
-#define PCI_DEVICE_ID_ATI_RADEON_QL 0x514c
-#define PCI_DEVICE_ID_ATI_RADEON_QN 0x514e
-#define PCI_DEVICE_ID_ATI_RADEON_QO 0x514f
-#define PCI_DEVICE_ID_ATI_RADEON_Ql 0x516c
-#define PCI_DEVICE_ID_ATI_RADEON_BB 0x4242
-/* Radeon R200 (9100) */
-#define PCI_DEVICE_ID_ATI_RADEON_QM 0x514d
-/* Radeon RV200 (7500) */
-#define PCI_DEVICE_ID_ATI_RADEON_QW 0x5157
-#define PCI_DEVICE_ID_ATI_RADEON_QX 0x5158
-/* Radeon RV250 (9000) */
-#define PCI_DEVICE_ID_ATI_RADEON_Id 0x4964
-#define PCI_DEVICE_ID_ATI_RADEON_Ie 0x4965
-#define PCI_DEVICE_ID_ATI_RADEON_If 0x4966
-#define PCI_DEVICE_ID_ATI_RADEON_Ig 0x4967
-/* Radeon RV280 (9200) */
-#define PCI_DEVICE_ID_ATI_RADEON_Y_ 0x5960
-#define PCI_DEVICE_ID_ATI_RADEON_Ya 0x5961
-#define PCI_DEVICE_ID_ATI_RADEON_Yd 0x5964
-/* Radeon R300 (9700) */
-#define PCI_DEVICE_ID_ATI_RADEON_ND 0x4e44
-#define PCI_DEVICE_ID_ATI_RADEON_NE 0x4e45
-#define PCI_DEVICE_ID_ATI_RADEON_NF 0x4e46
-#define PCI_DEVICE_ID_ATI_RADEON_NG 0x4e47
-#define PCI_DEVICE_ID_ATI_RADEON_AE 0x4145
-#define PCI_DEVICE_ID_ATI_RADEON_AF 0x4146
-/* Radeon R300 (9500) */
-#define PCI_DEVICE_ID_ATI_RADEON_AD 0x4144
-/* Radeon R350 (9800) */
-#define PCI_DEVICE_ID_ATI_RADEON_NH 0x4e48
-#define PCI_DEVICE_ID_ATI_RADEON_NI 0x4e49
-/* Radeon RV350 (9600) */
-#define PCI_DEVICE_ID_ATI_RADEON_AP 0x4150
-#define PCI_DEVICE_ID_ATI_RADEON_AR 0x4152
-/* Radeon M6 */
-#define PCI_DEVICE_ID_ATI_RADEON_LY 0x4c59
-#define PCI_DEVICE_ID_ATI_RADEON_LZ 0x4c5a
-/* Radeon M7 */
-#define PCI_DEVICE_ID_ATI_RADEON_LW 0x4c57
-#define PCI_DEVICE_ID_ATI_RADEON_LX 0x4c58
-/* Radeon M9 */
-#define PCI_DEVICE_ID_ATI_RADEON_Ld 0x4c64
-#define PCI_DEVICE_ID_ATI_RADEON_Le 0x4c65
-#define PCI_DEVICE_ID_ATI_RADEON_Lf 0x4c66
-#define PCI_DEVICE_ID_ATI_RADEON_Lg 0x4c67
-/* RadeonIGP */
-#define PCI_DEVICE_ID_ATI_RADEON_IGP 0xCAB0
-/* ATI IXP Chipset */
-#define PCI_DEVICE_ID_ATI_IXP_IDE 0x4349
-
-#define PCI_VENDOR_ID_VLSI 0x1004
-#define PCI_DEVICE_ID_VLSI_82C592 0x0005
-#define PCI_DEVICE_ID_VLSI_82C593 0x0006
-#define PCI_DEVICE_ID_VLSI_82C594 0x0007
-#define PCI_DEVICE_ID_VLSI_82C597 0x0009
-#define PCI_DEVICE_ID_VLSI_82C541 0x000c
-#define PCI_DEVICE_ID_VLSI_82C543 0x000d
-#define PCI_DEVICE_ID_VLSI_82C532 0x0101
-#define PCI_DEVICE_ID_VLSI_82C534 0x0102
-#define PCI_DEVICE_ID_VLSI_82C535 0x0104
-#define PCI_DEVICE_ID_VLSI_82C147 0x0105
-#define PCI_DEVICE_ID_VLSI_VAS96011 0x0702
-
-#define PCI_VENDOR_ID_ADL 0x1005
-#define PCI_DEVICE_ID_ADL_2301 0x2301
-
-#define PCI_VENDOR_ID_NS 0x100b
-#define PCI_DEVICE_ID_NS_87415 0x0002
-#define PCI_DEVICE_ID_NS_87560_LIO 0x000e
-#define PCI_DEVICE_ID_NS_87560_USB 0x0012
-#define PCI_DEVICE_ID_NS_83815 0x0020
-#define PCI_DEVICE_ID_NS_83820 0x0022
-#define PCI_DEVICE_ID_NS_SCx200_BRIDGE 0x0500
-#define PCI_DEVICE_ID_NS_SCx200_SMI 0x0501
-#define PCI_DEVICE_ID_NS_SCx200_IDE 0x0502
-#define PCI_DEVICE_ID_NS_SCx200_AUDIO 0x0503
-#define PCI_DEVICE_ID_NS_SCx200_VIDEO 0x0504
-#define PCI_DEVICE_ID_NS_SCx200_XBUS 0x0505
-#define PCI_DEVICE_ID_NS_87410 0xd001
-
-#define PCI_VENDOR_ID_TSENG 0x100c
-#define PCI_DEVICE_ID_TSENG_W32P_2 0x3202
-#define PCI_DEVICE_ID_TSENG_W32P_b 0x3205
-#define PCI_DEVICE_ID_TSENG_W32P_c 0x3206
-#define PCI_DEVICE_ID_TSENG_W32P_d 0x3207
-#define PCI_DEVICE_ID_TSENG_ET6000 0x3208
-
-#define PCI_VENDOR_ID_WEITEK 0x100e
-#define PCI_DEVICE_ID_WEITEK_P9000 0x9001
-#define PCI_DEVICE_ID_WEITEK_P9100 0x9100
-
-#define PCI_VENDOR_ID_DEC 0x1011
-#define PCI_DEVICE_ID_DEC_BRD 0x0001
-#define PCI_DEVICE_ID_DEC_TULIP 0x0002
-#define PCI_DEVICE_ID_DEC_TGA 0x0004
-#define PCI_DEVICE_ID_DEC_TULIP_FAST 0x0009
-#define PCI_DEVICE_ID_DEC_TGA2 0x000D
-#define PCI_DEVICE_ID_DEC_FDDI 0x000F
-#define PCI_DEVICE_ID_DEC_TULIP_PLUS 0x0014
-#define PCI_DEVICE_ID_DEC_21142 0x0019
-#define PCI_DEVICE_ID_DEC_21052 0x0021
-#define PCI_DEVICE_ID_DEC_21150 0x0022
-#define PCI_DEVICE_ID_DEC_21152 0x0024
-#define PCI_DEVICE_ID_DEC_21153 0x0025
-#define PCI_DEVICE_ID_DEC_21154 0x0026
-#define PCI_DEVICE_ID_DEC_21285 0x1065
-#define PCI_DEVICE_ID_COMPAQ_42XX 0x0046
-
-#define PCI_VENDOR_ID_CIRRUS 0x1013
-#define PCI_DEVICE_ID_CIRRUS_7548 0x0038
-#define PCI_DEVICE_ID_CIRRUS_5430 0x00a0
-#define PCI_DEVICE_ID_CIRRUS_5434_4 0x00a4
-#define PCI_DEVICE_ID_CIRRUS_5434_8 0x00a8
-#define PCI_DEVICE_ID_CIRRUS_5436 0x00ac
-#define PCI_DEVICE_ID_CIRRUS_5446 0x00b8
-#define PCI_DEVICE_ID_CIRRUS_5480 0x00bc
-#define PCI_DEVICE_ID_CIRRUS_5462 0x00d0
-#define PCI_DEVICE_ID_CIRRUS_5464 0x00d4
-#define PCI_DEVICE_ID_CIRRUS_5465 0x00d6
-#define PCI_DEVICE_ID_CIRRUS_6729 0x1100
-#define PCI_DEVICE_ID_CIRRUS_6832 0x1110
-#define PCI_DEVICE_ID_CIRRUS_7542 0x1200
-#define PCI_DEVICE_ID_CIRRUS_7543 0x1202
-#define PCI_DEVICE_ID_CIRRUS_7541 0x1204
-
-#define PCI_VENDOR_ID_IBM 0x1014
-#define PCI_DEVICE_ID_IBM_FIRE_CORAL 0x000a
-#define PCI_DEVICE_ID_IBM_TR 0x0018
-#define PCI_DEVICE_ID_IBM_82G2675 0x001d
-#define PCI_DEVICE_ID_IBM_MCA 0x0020
-#define PCI_DEVICE_ID_IBM_82351 0x0022
-#define PCI_DEVICE_ID_IBM_PYTHON 0x002d
-#define PCI_DEVICE_ID_IBM_SERVERAID 0x002e
-#define PCI_DEVICE_ID_IBM_TR_WAKE 0x003e
-#define PCI_DEVICE_ID_IBM_MPIC 0x0046
-#define PCI_DEVICE_ID_IBM_3780IDSP 0x007d
-#define PCI_DEVICE_ID_IBM_CHUKAR 0x0096
-#define PCI_DEVICE_ID_IBM_CPC700 0x00f9
-#define PCI_DEVICE_ID_IBM_CPC710_PCI64 0x00fc
-#define PCI_DEVICE_ID_IBM_CPC710_PCI32 0x0105
-#define PCI_DEVICE_ID_IBM_405GP 0x0156
-#define PCI_DEVICE_ID_IBM_SERVERAIDI960 0x01bd
-#define PCI_DEVICE_ID_IBM_MPIC_2 0xffff
-
-#define PCI_VENDOR_ID_COMPEX2 0x101a /* pci.ids says "AT&T GIS (NCR)" */
-#define PCI_DEVICE_ID_COMPEX2_100VG 0x0005
-
-#define PCI_VENDOR_ID_WD 0x101c
-#define PCI_DEVICE_ID_WD_7197 0x3296
-#define PCI_DEVICE_ID_WD_90C 0xc24a
-
-#define PCI_VENDOR_ID_AMI 0x101e
-#define PCI_DEVICE_ID_AMI_MEGARAID3 0x1960
-#define PCI_DEVICE_ID_AMI_MEGARAID 0x9010
-#define PCI_DEVICE_ID_AMI_MEGARAID2 0x9060
-
-#define PCI_VENDOR_ID_AMD 0x1022
-#define PCI_DEVICE_ID_AMD_LANCE 0x2000
-#define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001
-#define PCI_DEVICE_ID_AMD_SCSI 0x2020
-#define PCI_DEVICE_ID_AMD_SERENADE 0x36c0
-#define PCI_DEVICE_ID_AMD_FE_GATE_7006 0x7006
-#define PCI_DEVICE_ID_AMD_FE_GATE_7007 0x7007
-#define PCI_DEVICE_ID_AMD_FE_GATE_700C 0x700C
-#define PCI_DEVICE_ID_AMD_FE_GATE_700D 0x700D
-#define PCI_DEVICE_ID_AMD_FE_GATE_700E 0x700E
-#define PCI_DEVICE_ID_AMD_FE_GATE_700F 0x700F
-#define PCI_DEVICE_ID_AMD_COBRA_7400 0x7400
-#define PCI_DEVICE_ID_AMD_COBRA_7401 0x7401
-#define PCI_DEVICE_ID_AMD_COBRA_7403 0x7403
-#define PCI_DEVICE_ID_AMD_COBRA_7404 0x7404
-#define PCI_DEVICE_ID_AMD_VIPER_7408 0x7408
-#define PCI_DEVICE_ID_AMD_VIPER_7409 0x7409
-#define PCI_DEVICE_ID_AMD_VIPER_740B 0x740B
-#define PCI_DEVICE_ID_AMD_VIPER_740C 0x740C
-#define PCI_DEVICE_ID_AMD_VIPER_7410 0x7410
-#define PCI_DEVICE_ID_AMD_VIPER_7411 0x7411
-#define PCI_DEVICE_ID_AMD_VIPER_7413 0x7413
-#define PCI_DEVICE_ID_AMD_VIPER_7414 0x7414
-#define PCI_DEVICE_ID_AMD_OPUS_7440 0x7440
-# define PCI_DEVICE_ID_AMD_VIPER_7440 PCI_DEVICE_ID_AMD_OPUS_7440
-#define PCI_DEVICE_ID_AMD_OPUS_7441 0x7441
-# define PCI_DEVICE_ID_AMD_VIPER_7441 PCI_DEVICE_ID_AMD_OPUS_7441
-#define PCI_DEVICE_ID_AMD_OPUS_7443 0x7443
-# define PCI_DEVICE_ID_AMD_VIPER_7443 PCI_DEVICE_ID_AMD_OPUS_7443
-#define PCI_DEVICE_ID_AMD_OPUS_7448 0x7448
-# define PCI_DEVICE_ID_AMD_VIPER_7448 PCI_DEVICE_ID_AMD_OPUS_7448
-#define PCI_DEVICE_ID_AMD_OPUS_7449 0x7449
-# define PCI_DEVICE_ID_AMD_VIPER_7449 PCI_DEVICE_ID_AMD_OPUS_7449
-#define PCI_DEVICE_ID_AMD_8111_LAN 0x7462
-#define PCI_DEVICE_ID_AMD_8111_IDE 0x7469
-#define PCI_DEVICE_ID_AMD_8111_AC97 0x746d
-#define PCI_DEVICE_ID_AMD_8131_APIC 0x7450
-
-#define PCI_VENDOR_ID_TRIDENT 0x1023
-#define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX 0x2000
-#define PCI_DEVICE_ID_TRIDENT_4DWAVE_NX 0x2001
-#define PCI_DEVICE_ID_TRIDENT_9320 0x9320
-#define PCI_DEVICE_ID_TRIDENT_9388 0x9388
-#define PCI_DEVICE_ID_TRIDENT_9397 0x9397
-#define PCI_DEVICE_ID_TRIDENT_939A 0x939A
-#define PCI_DEVICE_ID_TRIDENT_9520 0x9520
-#define PCI_DEVICE_ID_TRIDENT_9525 0x9525
-#define PCI_DEVICE_ID_TRIDENT_9420 0x9420
-#define PCI_DEVICE_ID_TRIDENT_9440 0x9440
-#define PCI_DEVICE_ID_TRIDENT_9660 0x9660
-#define PCI_DEVICE_ID_TRIDENT_9750 0x9750
-#define PCI_DEVICE_ID_TRIDENT_9850 0x9850
-#define PCI_DEVICE_ID_TRIDENT_9880 0x9880
-#define PCI_DEVICE_ID_TRIDENT_8400 0x8400
-#define PCI_DEVICE_ID_TRIDENT_8420 0x8420
-#define PCI_DEVICE_ID_TRIDENT_8500 0x8500
-
-#define PCI_VENDOR_ID_AI 0x1025
-#define PCI_DEVICE_ID_AI_M1435 0x1435
-
-#define PCI_VENDOR_ID_DELL 0x1028
-
-#define PCI_VENDOR_ID_MATROX 0x102B
-#define PCI_DEVICE_ID_MATROX_MGA_2 0x0518
-#define PCI_DEVICE_ID_MATROX_MIL 0x0519
-#define PCI_DEVICE_ID_MATROX_MYS 0x051A
-#define PCI_DEVICE_ID_MATROX_MIL_2 0x051b
-#define PCI_DEVICE_ID_MATROX_MIL_2_AGP 0x051f
-#define PCI_DEVICE_ID_MATROX_MGA_IMP 0x0d10
-#define PCI_DEVICE_ID_MATROX_G100_MM 0x1000
-#define PCI_DEVICE_ID_MATROX_G100_AGP 0x1001
-#define PCI_DEVICE_ID_MATROX_G200_PCI 0x0520
-#define PCI_DEVICE_ID_MATROX_G200_AGP 0x0521
-#define PCI_DEVICE_ID_MATROX_G400 0x0525
-#define PCI_DEVICE_ID_MATROX_G550 0x2527
-#define PCI_DEVICE_ID_MATROX_VIA 0x4536
-
-#define PCI_VENDOR_ID_CT 0x102c
-#define PCI_DEVICE_ID_CT_65545 0x00d8
-#define PCI_DEVICE_ID_CT_65548 0x00dc
-#define PCI_DEVICE_ID_CT_65550 0x00e0
-#define PCI_DEVICE_ID_CT_65554 0x00e4
-#define PCI_DEVICE_ID_CT_65555 0x00e5
-#define PCI_DEVICE_ID_CT_69000 0x00c0
-#define PCI_DEVICE_ID_CT_69030 0x0c30
-
-#define PCI_VENDOR_ID_MIRO 0x1031
-#define PCI_DEVICE_ID_MIRO_36050 0x5601
-
-#define PCI_VENDOR_ID_NEC 0x1033
-#define PCI_DEVICE_ID_NEC_NAPCCARD 0x003e
-#define PCI_DEVICE_ID_NEC_PCX2 0x0046
-#define PCI_DEVICE_ID_NEC_NILE4 0x005a
-#define PCI_DEVICE_ID_NEC_VRC5476 0x009b
-#define PCI_DEVICE_ID_NEC_VRC4173 0x00a5
-#define PCI_DEVICE_ID_NEC_VRC5477_AC97 0x00a6
-
-#define PCI_VENDOR_ID_FD 0x1036
-#define PCI_DEVICE_ID_FD_36C70 0x0000
-
-#define PCI_VENDOR_ID_SI 0x1039
-#define PCI_DEVICE_ID_SI_5591_AGP 0x0001
-#define PCI_DEVICE_ID_SI_6202 0x0002
-#define PCI_DEVICE_ID_SI_503 0x0008
-#define PCI_DEVICE_ID_SI_ACPI 0x0009
-#define PCI_DEVICE_ID_SI_180 0x0180
-#define PCI_DEVICE_ID_SI_5597_VGA 0x0200
-#define PCI_DEVICE_ID_SI_6205 0x0205
-#define PCI_DEVICE_ID_SI_501 0x0406
-#define PCI_DEVICE_ID_SI_496 0x0496
-#define PCI_DEVICE_ID_SI_300 0x0300
-#define PCI_DEVICE_ID_SI_315H 0x0310
-#define PCI_DEVICE_ID_SI_315 0x0315
-#define PCI_DEVICE_ID_SI_315PRO 0x0325
-#define PCI_DEVICE_ID_SI_530 0x0530
-#define PCI_DEVICE_ID_SI_540 0x0540
-#define PCI_DEVICE_ID_SI_550 0x0550
-#define PCI_DEVICE_ID_SI_540_VGA 0x5300
-#define PCI_DEVICE_ID_SI_550_VGA 0x5315
-#define PCI_DEVICE_ID_SI_601 0x0601
-#define PCI_DEVICE_ID_SI_620 0x0620
-#define PCI_DEVICE_ID_SI_630 0x0630
-#define PCI_DEVICE_ID_SI_633 0x0633
-#define PCI_DEVICE_ID_SI_635 0x0635
-#define PCI_DEVICE_ID_SI_640 0x0640
-#define PCI_DEVICE_ID_SI_645 0x0645
-#define PCI_DEVICE_ID_SI_646 0x0646
-#define PCI_DEVICE_ID_SI_648 0x0648
-#define PCI_DEVICE_ID_SI_650 0x0650
-#define PCI_DEVICE_ID_SI_651 0x0651
-#define PCI_DEVICE_ID_SI_652 0x0652
-#define PCI_DEVICE_ID_SI_655 0x0655
-#define PCI_DEVICE_ID_SI_730 0x0730
-#define PCI_DEVICE_ID_SI_733 0x0733
-#define PCI_DEVICE_ID_SI_630_VGA 0x6300
-#define PCI_DEVICE_ID_SI_730_VGA 0x7300
-#define PCI_DEVICE_ID_SI_735 0x0735
-#define PCI_DEVICE_ID_SI_740 0x0740
-#define PCI_DEVICE_ID_SI_745 0x0745
-#define PCI_DEVICE_ID_SI_746 0x0746
-#define PCI_DEVICE_ID_SI_748 0x0748
-#define PCI_DEVICE_ID_SI_750 0x0750
-#define PCI_DEVICE_ID_SI_751 0x0751
-#define PCI_DEVICE_ID_SI_752 0x0752
-#define PCI_DEVICE_ID_SI_755 0x0755
-#define PCI_DEVICE_ID_SI_900 0x0900
-#define PCI_DEVICE_ID_SI_5107 0x5107
-#define PCI_DEVICE_ID_SI_5300 0x5300
-#define PCI_DEVICE_ID_SI_5511 0x5511
-#define PCI_DEVICE_ID_SI_5513 0x5513
-#define PCI_DEVICE_ID_SI_5518 0x5518
-#define PCI_DEVICE_ID_SI_5571 0x5571
-#define PCI_DEVICE_ID_SI_5581 0x5581
-#define PCI_DEVICE_ID_SI_5582 0x5582
-#define PCI_DEVICE_ID_SI_5591 0x5591
-#define PCI_DEVICE_ID_SI_5596 0x5596
-#define PCI_DEVICE_ID_SI_5597 0x5597
-#define PCI_DEVICE_ID_SI_5598 0x5598
-#define PCI_DEVICE_ID_SI_5600 0x5600
-#define PCI_DEVICE_ID_SI_6300 0x6300
-#define PCI_DEVICE_ID_SI_6306 0x6306
-#define PCI_DEVICE_ID_SI_6326 0x6326
-#define PCI_DEVICE_ID_SI_7001 0x7001
-#define PCI_DEVICE_ID_SI_7016 0x7016
-
-#define PCI_VENDOR_ID_HP 0x103c
-#define PCI_DEVICE_ID_HP_DONNER_GFX 0x1008
-#define PCI_DEVICE_ID_HP_TACHYON 0x1028
-#define PCI_DEVICE_ID_HP_TACHLITE 0x1029
-#define PCI_DEVICE_ID_HP_J2585A 0x1030
-#define PCI_DEVICE_ID_HP_J2585B 0x1031
-#define PCI_DEVICE_ID_HP_SAS 0x1048
-#define PCI_DEVICE_ID_HP_DIVA1 0x1049
-#define PCI_DEVICE_ID_HP_DIVA2 0x104A
-#define PCI_DEVICE_ID_HP_SP2_0 0x104B
-#define PCI_DEVICE_ID_HP_PCI_LBA 0x1054
-#define PCI_DEVICE_ID_HP_REO_SBA 0x10f0
-#define PCI_DEVICE_ID_HP_REO_IOC 0x10f1
-#define PCI_DEVICE_ID_HP_ZX1_SBA 0x1229
-#define PCI_DEVICE_ID_HP_ZX1_IOC 0x122a
-#define PCI_DEVICE_ID_HP_PCIX_LBA 0x122e
-#define PCI_DEVICE_ID_HP_SX1000_IOC 0x127c
-
-#define PCI_VENDOR_ID_PCTECH 0x1042
-#define PCI_DEVICE_ID_PCTECH_RZ1000 0x1000
-#define PCI_DEVICE_ID_PCTECH_RZ1001 0x1001
-#define PCI_DEVICE_ID_PCTECH_SAMURAI_0 0x3000
-#define PCI_DEVICE_ID_PCTECH_SAMURAI_1 0x3010
-#define PCI_DEVICE_ID_PCTECH_SAMURAI_IDE 0x3020
-
-#define PCI_VENDOR_ID_ASUSTEK 0x1043
-#define PCI_DEVICE_ID_ASUSTEK_0675 0x0675
-
-#define PCI_VENDOR_ID_DPT 0x1044
-#define PCI_DEVICE_ID_DPT 0xa400
-
-#define PCI_VENDOR_ID_OPTI 0x1045
-#define PCI_DEVICE_ID_OPTI_92C178 0xc178
-#define PCI_DEVICE_ID_OPTI_82C557 0xc557
-#define PCI_DEVICE_ID_OPTI_82C558 0xc558
-#define PCI_DEVICE_ID_OPTI_82C621 0xc621
-#define PCI_DEVICE_ID_OPTI_82C700 0xc700
-#define PCI_DEVICE_ID_OPTI_82C701 0xc701
-#define PCI_DEVICE_ID_OPTI_82C814 0xc814
-#define PCI_DEVICE_ID_OPTI_82C822 0xc822
-#define PCI_DEVICE_ID_OPTI_82C861 0xc861
-#define PCI_DEVICE_ID_OPTI_82C825 0xd568
-
-#define PCI_VENDOR_ID_ELSA 0x1048
-#define PCI_DEVICE_ID_ELSA_MICROLINK 0x1000
-#define PCI_DEVICE_ID_ELSA_QS3000 0x3000
-
-#define PCI_VENDOR_ID_SGS 0x104a
-#define PCI_DEVICE_ID_SGS_2000 0x0008
-#define PCI_DEVICE_ID_SGS_1764 0x0009
-
-#define PCI_VENDOR_ID_BUSLOGIC 0x104B
-#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC 0x0140
-#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER 0x1040
-#define PCI_DEVICE_ID_BUSLOGIC_FLASHPOINT 0x8130
-
-#define PCI_VENDOR_ID_TI 0x104c
-#define PCI_DEVICE_ID_TI_TVP4010 0x3d04
-#define PCI_DEVICE_ID_TI_TVP4020 0x3d07
-#define PCI_DEVICE_ID_TI_1130 0xac12
-#define PCI_DEVICE_ID_TI_1031 0xac13
-#define PCI_DEVICE_ID_TI_1131 0xac15
-#define PCI_DEVICE_ID_TI_1250 0xac16
-#define PCI_DEVICE_ID_TI_1220 0xac17
-#define PCI_DEVICE_ID_TI_1221 0xac19
-#define PCI_DEVICE_ID_TI_1210 0xac1a
-#define PCI_DEVICE_ID_TI_1410 0xac50
-#define PCI_DEVICE_ID_TI_1450 0xac1b
-#define PCI_DEVICE_ID_TI_1225 0xac1c
-#define PCI_DEVICE_ID_TI_1251A 0xac1d
-#define PCI_DEVICE_ID_TI_1211 0xac1e
-#define PCI_DEVICE_ID_TI_1251B 0xac1f
-#define PCI_DEVICE_ID_TI_4410 0xac41
-#define PCI_DEVICE_ID_TI_4451 0xac42
-#define PCI_DEVICE_ID_TI_1420 0xac51
-#define PCI_DEVICE_ID_TI_1520 0xac55
-#define PCI_DEVICE_ID_TI_1510 0xac56
-
-#define PCI_VENDOR_ID_SONY 0x104d
-#define PCI_DEVICE_ID_SONY_CXD3222 0x8039
-
-#define PCI_VENDOR_ID_OAK 0x104e
-#define PCI_DEVICE_ID_OAK_OTI107 0x0107
-
-/* Winbond have two vendor IDs! See 0x10ad as well */
-#define PCI_VENDOR_ID_WINBOND2 0x1050
-#define PCI_DEVICE_ID_WINBOND2_89C940 0x0940
-#define PCI_DEVICE_ID_WINBOND2_89C940F 0x5a5a
-#define PCI_DEVICE_ID_WINBOND2_6692 0x6692
-
-#define PCI_VENDOR_ID_ANIGMA 0x1051
-#define PCI_DEVICE_ID_ANIGMA_MC145575 0x0100
-
-#define PCI_VENDOR_ID_EFAR 0x1055
-#define PCI_DEVICE_ID_EFAR_SLC90E66_1 0x9130
-#define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460
-#define PCI_DEVICE_ID_EFAR_SLC90E66_2 0x9462
-#define PCI_DEVICE_ID_EFAR_SLC90E66_3 0x9463
-
-#define PCI_VENDOR_ID_MOTOROLA 0x1057
-#define PCI_VENDOR_ID_MOTOROLA_OOPS 0x1507
-#define PCI_DEVICE_ID_MOTOROLA_MPC105 0x0001
-#define PCI_DEVICE_ID_MOTOROLA_MPC106 0x0002
-#define PCI_DEVICE_ID_MOTOROLA_MPC107 0x0004
-#define PCI_DEVICE_ID_MOTOROLA_MPC8540 0x0008
-#define PCI_DEVICE_ID_MOTOROLA_MPC8560 0x0009
-#define PCI_DEVICE_ID_MOTOROLA_MPC8265A 0x18c0
-#define PCI_DEVICE_ID_MOTOROLA_RAVEN 0x4801
-#define PCI_DEVICE_ID_MOTOROLA_FALCON 0x4802
-#define PCI_DEVICE_ID_MOTOROLA_HAWK 0x4803
-#define PCI_DEVICE_ID_MOTOROLA_CPX8216 0x4806
-#define PCI_DEVICE_ID_MOTOROLA_MPC190 0x6400
-
-#define PCI_VENDOR_ID_PROMISE 0x105a
-#define PCI_DEVICE_ID_PROMISE_20265 0x0d30
-#define PCI_DEVICE_ID_PROMISE_20267 0x4d30
-#define PCI_DEVICE_ID_PROMISE_20246 0x4d33
-#define PCI_DEVICE_ID_PROMISE_20262 0x4d38
-#define PCI_DEVICE_ID_PROMISE_20263 0x0D38
-#define PCI_DEVICE_ID_PROMISE_20268 0x4d68
-#define PCI_DEVICE_ID_PROMISE_20270 0x6268
-#define PCI_DEVICE_ID_PROMISE_20269 0x4d69
-#define PCI_DEVICE_ID_PROMISE_20271 0x6269
-#define PCI_DEVICE_ID_PROMISE_20275 0x1275
-#define PCI_DEVICE_ID_PROMISE_20276 0x5275
-#define PCI_DEVICE_ID_PROMISE_20277 0x7275
-#define PCI_DEVICE_ID_PROMISE_5300 0x5300
-
-#define PCI_VENDOR_ID_N9 0x105d
-#define PCI_DEVICE_ID_N9_I128 0x2309
-#define PCI_DEVICE_ID_N9_I128_2 0x2339
-#define PCI_DEVICE_ID_N9_I128_T2R 0x493d
-
-#define PCI_VENDOR_ID_UMC 0x1060
-#define PCI_DEVICE_ID_UMC_UM8673F 0x0101
-#define PCI_DEVICE_ID_UMC_UM8891A 0x0891
-#define PCI_DEVICE_ID_UMC_UM8886BF 0x673a
-#define PCI_DEVICE_ID_UMC_UM8886A 0x886a
-#define PCI_DEVICE_ID_UMC_UM8881F 0x8881
-#define PCI_DEVICE_ID_UMC_UM8886F 0x8886
-#define PCI_DEVICE_ID_UMC_UM9017F 0x9017
-#define PCI_DEVICE_ID_UMC_UM8886N 0xe886
-#define PCI_DEVICE_ID_UMC_UM8891N 0xe891
-
-#define PCI_VENDOR_ID_X 0x1061
-#define PCI_DEVICE_ID_X_AGX016 0x0001
-
-#define PCI_VENDOR_ID_MYLEX 0x1069
-#define PCI_DEVICE_ID_MYLEX_DAC960_P 0x0001
-#define PCI_DEVICE_ID_MYLEX_DAC960_PD 0x0002
-#define PCI_DEVICE_ID_MYLEX_DAC960_PG 0x0010
-#define PCI_DEVICE_ID_MYLEX_DAC960_LA 0x0020
-#define PCI_DEVICE_ID_MYLEX_DAC960_LP 0x0050
-#define PCI_DEVICE_ID_MYLEX_DAC960_BA 0xBA56
-
-#define PCI_VENDOR_ID_PICOP 0x1066
-#define PCI_DEVICE_ID_PICOP_PT86C52X 0x0001
-#define PCI_DEVICE_ID_PICOP_PT80C524 0x8002
-
-#define PCI_VENDOR_ID_APPLE 0x106b
-#define PCI_DEVICE_ID_APPLE_BANDIT 0x0001
-#define PCI_DEVICE_ID_APPLE_GC 0x0002
-#define PCI_DEVICE_ID_APPLE_HYDRA 0x000e
-#define PCI_DEVICE_ID_APPLE_UNI_N_FW 0x0018
-#define PCI_DEVICE_ID_APPLE_KL_USB 0x0019
-#define PCI_DEVICE_ID_APPLE_UNI_N_AGP 0x0020
-#define PCI_DEVICE_ID_APPLE_UNI_N_GMAC 0x0021
-#define PCI_DEVICE_ID_APPLE_KEYLARGO 0x0022
-#define PCI_DEVICE_ID_APPLE_UNI_N_GMACP 0x0024
-#define PCI_DEVICE_ID_APPLE_KEYLARGO_P 0x0025
-#define PCI_DEVICE_ID_APPLE_KL_USB_P 0x0026
-#define PCI_DEVICE_ID_APPLE_UNI_N_AGP_P 0x0027
-#define PCI_DEVICE_ID_APPLE_UNI_N_AGP15 0x002d
-#define PCI_DEVICE_ID_APPLE_UNI_N_FW2 0x0030
-#define PCI_DEVICE_ID_APPLE_TIGON3 0x1645
-
-#define PCI_VENDOR_ID_YAMAHA 0x1073
-#define PCI_DEVICE_ID_YAMAHA_724 0x0004
-#define PCI_DEVICE_ID_YAMAHA_724F 0x000d
-#define PCI_DEVICE_ID_YAMAHA_740 0x000a
-#define PCI_DEVICE_ID_YAMAHA_740C 0x000c
-#define PCI_DEVICE_ID_YAMAHA_744 0x0010
-#define PCI_DEVICE_ID_YAMAHA_754 0x0012
-
-#define PCI_VENDOR_ID_NEXGEN 0x1074
-#define PCI_DEVICE_ID_NEXGEN_82C501 0x4e78
-
-#define PCI_VENDOR_ID_QLOGIC 0x1077
-#define PCI_DEVICE_ID_QLOGIC_ISP1020 0x1020
-#define PCI_DEVICE_ID_QLOGIC_ISP1022 0x1022
-#define PCI_DEVICE_ID_QLOGIC_ISP2100 0x2100
-#define PCI_DEVICE_ID_QLOGIC_ISP2200 0x2200
-
-#define PCI_VENDOR_ID_CYRIX 0x1078
-#define PCI_DEVICE_ID_CYRIX_5510 0x0000
-#define PCI_DEVICE_ID_CYRIX_PCI_MASTER 0x0001
-#define PCI_DEVICE_ID_CYRIX_5520 0x0002
-#define PCI_DEVICE_ID_CYRIX_5530_LEGACY 0x0100
-#define PCI_DEVICE_ID_CYRIX_5530_SMI 0x0101
-#define PCI_DEVICE_ID_CYRIX_5530_IDE 0x0102
-#define PCI_DEVICE_ID_CYRIX_5530_AUDIO 0x0103
-#define PCI_DEVICE_ID_CYRIX_5530_VIDEO 0x0104
-
-#define PCI_VENDOR_ID_LEADTEK 0x107d
-#define PCI_DEVICE_ID_LEADTEK_805 0x0000
-
-#define PCI_VENDOR_ID_INTERPHASE 0x107e
-#define PCI_DEVICE_ID_INTERPHASE_5526 0x0004
-#define PCI_DEVICE_ID_INTERPHASE_55x6 0x0005
-#define PCI_DEVICE_ID_INTERPHASE_5575 0x0008
-
-#define PCI_VENDOR_ID_CONTAQ 0x1080
-#define PCI_DEVICE_ID_CONTAQ_82C599 0x0600
-#define PCI_DEVICE_ID_CONTAQ_82C693 0xc693
-
-#define PCI_VENDOR_ID_FOREX 0x1083
-
-#define PCI_VENDOR_ID_OLICOM 0x108d
-#define PCI_DEVICE_ID_OLICOM_OC3136 0x0001
-#define PCI_DEVICE_ID_OLICOM_OC2315 0x0011
-#define PCI_DEVICE_ID_OLICOM_OC2325 0x0012
-#define PCI_DEVICE_ID_OLICOM_OC2183 0x0013
-#define PCI_DEVICE_ID_OLICOM_OC2326 0x0014
-#define PCI_DEVICE_ID_OLICOM_OC6151 0x0021
-
-#define PCI_VENDOR_ID_SUN 0x108e
-#define PCI_DEVICE_ID_SUN_EBUS 0x1000
-#define PCI_DEVICE_ID_SUN_HAPPYMEAL 0x1001
-#define PCI_DEVICE_ID_SUN_RIO_EBUS 0x1100
-#define PCI_DEVICE_ID_SUN_RIO_GEM 0x1101
-#define PCI_DEVICE_ID_SUN_RIO_1394 0x1102
-#define PCI_DEVICE_ID_SUN_RIO_USB 0x1103
-#define PCI_DEVICE_ID_SUN_GEM 0x2bad
-#define PCI_DEVICE_ID_SUN_SIMBA 0x5000
-#define PCI_DEVICE_ID_SUN_PBM 0x8000
-#define PCI_DEVICE_ID_SUN_SCHIZO 0x8001
-#define PCI_DEVICE_ID_SUN_SABRE 0xa000
-#define PCI_DEVICE_ID_SUN_HUMMINGBIRD 0xa001
-#define PCI_DEVICE_ID_SUN_TOMATILLO 0xa801
-
-#define PCI_VENDOR_ID_CMD 0x1095
-#define PCI_DEVICE_ID_SII_1210SA 0x0240
-
-#define PCI_DEVICE_ID_CMD_640 0x0640
-#define PCI_DEVICE_ID_CMD_643 0x0643
-#define PCI_DEVICE_ID_CMD_646 0x0646
-#define PCI_DEVICE_ID_CMD_647 0x0647
-#define PCI_DEVICE_ID_CMD_648 0x0648
-#define PCI_DEVICE_ID_CMD_649 0x0649
-#define PCI_DEVICE_ID_CMD_670 0x0670
-
-#define PCI_DEVICE_ID_SII_680 0x0680
-#define PCI_DEVICE_ID_SII_3112 0x3112
-
-#define PCI_VENDOR_ID_VISION 0x1098
-#define PCI_DEVICE_ID_VISION_QD8500 0x0001
-#define PCI_DEVICE_ID_VISION_QD8580 0x0002
-
-#define PCI_VENDOR_ID_BROOKTREE 0x109e
-#define PCI_DEVICE_ID_BROOKTREE_848 0x0350
-#define PCI_DEVICE_ID_BROOKTREE_849A 0x0351
-#define PCI_DEVICE_ID_BROOKTREE_878_1 0x036e
-#define PCI_DEVICE_ID_BROOKTREE_878 0x0878
-#define PCI_DEVICE_ID_BROOKTREE_8474 0x8474
-
-#define PCI_VENDOR_ID_SIERRA 0x10a8
-#define PCI_DEVICE_ID_SIERRA_STB 0x0000
-
-#define PCI_VENDOR_ID_SGI 0x10a9
-#define PCI_DEVICE_ID_SGI_IOC3 0x0003
-#define PCI_DEVICE_ID_SGI_IOC4 0x100a
-
-#define PCI_VENDOR_ID_ACC 0x10aa
-#define PCI_DEVICE_ID_ACC_2056 0x0000
-
-#define PCI_VENDOR_ID_WINBOND 0x10ad
-#define PCI_DEVICE_ID_WINBOND_83769 0x0001
-#define PCI_DEVICE_ID_WINBOND_82C105 0x0105
-#define PCI_DEVICE_ID_WINBOND_83C553 0x0565
-
-#define PCI_VENDOR_ID_DATABOOK 0x10b3
-#define PCI_DEVICE_ID_DATABOOK_87144 0xb106
-
-#define PCI_VENDOR_ID_PLX 0x10b5
-#define PCI_DEVICE_ID_PLX_R685 0x1030
-#define PCI_DEVICE_ID_PLX_ROMULUS 0x106a
-#define PCI_DEVICE_ID_PLX_SPCOM800 0x1076
-#define PCI_DEVICE_ID_PLX_1077 0x1077
-#define PCI_DEVICE_ID_PLX_SPCOM200 0x1103
-#define PCI_DEVICE_ID_PLX_DJINN_ITOO 0x1151
-#define PCI_DEVICE_ID_PLX_R753 0x1152
-#define PCI_DEVICE_ID_PLX_9050 0x9050
-#define PCI_DEVICE_ID_PLX_9060 0x9060
-#define PCI_DEVICE_ID_PLX_9060ES 0x906E
-#define PCI_DEVICE_ID_PLX_9060SD 0x906D
-#define PCI_DEVICE_ID_PLX_9080 0x9080
-#define PCI_DEVICE_ID_PLX_GTEK_SERIAL2 0xa001
-
-#define PCI_VENDOR_ID_MADGE 0x10b6
-#define PCI_DEVICE_ID_MADGE_MK2 0x0002
-#define PCI_DEVICE_ID_MADGE_C155S 0x1001
-
-#define PCI_VENDOR_ID_3COM 0x10b7
-#define PCI_DEVICE_ID_3COM_3C985 0x0001
-#define PCI_DEVICE_ID_3COM_3C339 0x3390
-#define PCI_DEVICE_ID_3COM_3C590 0x5900
-#define PCI_DEVICE_ID_3COM_3C595TX 0x5950
-#define PCI_DEVICE_ID_3COM_3C595T4 0x5951
-#define PCI_DEVICE_ID_3COM_3C595MII 0x5952
-#define PCI_DEVICE_ID_3COM_3C900TPO 0x9000
-#define PCI_DEVICE_ID_3COM_3C900COMBO 0x9001
-#define PCI_DEVICE_ID_3COM_3C905TX 0x9050
-#define PCI_DEVICE_ID_3COM_3C905T4 0x9051
-#define PCI_DEVICE_ID_3COM_3C905B_TX 0x9055
-#define PCI_DEVICE_ID_3COM_3CR990 0x9900
-#define PCI_DEVICE_ID_3COM_3CR990_TX_95 0x9902
-#define PCI_DEVICE_ID_3COM_3CR990_TX_97 0x9903
-#define PCI_DEVICE_ID_3COM_3CR990B 0x9904
-#define PCI_DEVICE_ID_3COM_3CR990_FX 0x9905
-#define PCI_DEVICE_ID_3COM_3CR990SVR95 0x9908
-#define PCI_DEVICE_ID_3COM_3CR990SVR97 0x9909
-#define PCI_DEVICE_ID_3COM_3CR990SVR 0x990a
-
-#define PCI_VENDOR_ID_SMC 0x10b8
-#define PCI_DEVICE_ID_SMC_EPIC100 0x0005
-
-#define PCI_VENDOR_ID_AL 0x10b9
-#define PCI_DEVICE_ID_AL_M1445 0x1445
-#define PCI_DEVICE_ID_AL_M1449 0x1449
-#define PCI_DEVICE_ID_AL_M1451 0x1451
-#define PCI_DEVICE_ID_AL_M1461 0x1461
-#define PCI_DEVICE_ID_AL_M1489 0x1489
-#define PCI_DEVICE_ID_AL_M1511 0x1511
-#define PCI_DEVICE_ID_AL_M1513 0x1513
-#define PCI_DEVICE_ID_AL_M1521 0x1521
-#define PCI_DEVICE_ID_AL_M1523 0x1523
-#define PCI_DEVICE_ID_AL_M1531 0x1531
-#define PCI_DEVICE_ID_AL_M1533 0x1533
-#define PCI_DEVICE_ID_AL_M1535 0x1535
-#define PCI_DEVICE_ID_AL_M1541 0x1541
-#define PCI_DEVICE_ID_AL_M1621 0x1621
-#define PCI_DEVICE_ID_AL_M1631 0x1631
-#define PCI_DEVICE_ID_AL_M1641 0x1641
-#define PCI_DEVICE_ID_AL_M1644 0x1644
-#define PCI_DEVICE_ID_AL_M1647 0x1647
-#define PCI_DEVICE_ID_AL_M1651 0x1651
-#define PCI_DEVICE_ID_AL_M1543 0x1543
-#define PCI_DEVICE_ID_AL_M3307 0x3307
-#define PCI_DEVICE_ID_AL_M4803 0x5215
-#define PCI_DEVICE_ID_AL_M5219 0x5219
-#define PCI_DEVICE_ID_AL_M5229 0x5229
-#define PCI_DEVICE_ID_AL_M5237 0x5237
-#define PCI_DEVICE_ID_AL_M5243 0x5243
-#define PCI_DEVICE_ID_AL_M5451 0x5451
-#define PCI_DEVICE_ID_AL_M7101 0x7101
-
-#define PCI_VENDOR_ID_MITSUBISHI 0x10ba
-
-#define PCI_VENDOR_ID_SURECOM 0x10bd
-#define PCI_DEVICE_ID_SURECOM_NE34 0x0e34
-
-#define PCI_VENDOR_ID_NEOMAGIC 0x10c8
-#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2070 0x0001
-#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128V 0x0002
-#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZV 0x0003
-#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2160 0x0004
-#define PCI_DEVICE_ID_NEOMAGIC_MAGICMEDIA_256AV 0x0005
-#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZVPLUS 0x0083
-
-#define PCI_VENDOR_ID_ASP 0x10cd
-#define PCI_DEVICE_ID_ASP_ABP940 0x1200
-#define PCI_DEVICE_ID_ASP_ABP940U 0x1300
-#define PCI_DEVICE_ID_ASP_ABP940UW 0x2300
-
-#define PCI_VENDOR_ID_MACRONIX 0x10d9
-#define PCI_DEVICE_ID_MACRONIX_MX98713 0x0512
-#define PCI_DEVICE_ID_MACRONIX_MX987x5 0x0531
-
-#define PCI_VENDOR_ID_TCONRAD 0x10da
-#define PCI_DEVICE_ID_TCONRAD_TOKENRING 0x0508
-
-#define PCI_VENDOR_ID_CERN 0x10dc
-#define PCI_DEVICE_ID_CERN_SPSB_PMC 0x0001
-#define PCI_DEVICE_ID_CERN_SPSB_PCI 0x0002
-#define PCI_DEVICE_ID_CERN_HIPPI_DST 0x0021
-#define PCI_DEVICE_ID_CERN_HIPPI_SRC 0x0022
-
-#define PCI_VENDOR_ID_NVIDIA 0x10de
-#define PCI_DEVICE_ID_NVIDIA_TNT 0x0020
-#define PCI_DEVICE_ID_NVIDIA_TNT2 0x0028
-#define PCI_DEVICE_ID_NVIDIA_UTNT2 0x0029
-#define PCI_DEVICE_ID_NVIDIA_VTNT2 0x002C
-#define PCI_DEVICE_ID_NVIDIA_UVTNT2 0x002D
-#define PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE 0x0065
-#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE 0x0085
-#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA 0x008e
-#define PCI_DEVICE_ID_NVIDIA_ITNT2 0x00A0
-#define PCI_DEVICE_ID_NVIDIA_NFORCE3 0x00d1
-#define PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE 0x00d5
-#define PCI_DEVICE_ID_NVIDIA_NFORCE3S 0x00e1
-#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA 0x00e3
-#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE 0x00e5
-#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2 0x00ee
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR 0x0100
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR 0x0101
-#define PCI_DEVICE_ID_NVIDIA_QUADRO 0x0103
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX 0x0110
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2 0x0111
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO 0x0112
-#define PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR 0x0113
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS 0x0150
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2 0x0151
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA 0x0152
-#define PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO 0x0153
-#define PCI_DEVICE_ID_NVIDIA_IGEFORCE2 0x01a0
-#define PCI_DEVICE_ID_NVIDIA_NFORCE 0x01a4
-#define PCI_DEVICE_ID_NVIDIA_NFORCE_IDE 0x01bc
-#define PCI_DEVICE_ID_NVIDIA_NFORCE2 0x01e0
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE3 0x0200
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_1 0x0201
-#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_2 0x0202
-#define PCI_DEVICE_ID_NVIDIA_QUADRO_DDC 0x0203
-
-#define PCI_VENDOR_ID_IMS 0x10e0
-#define PCI_DEVICE_ID_IMS_8849 0x8849
-#define PCI_DEVICE_ID_IMS_TT128 0x9128
-#define PCI_DEVICE_ID_IMS_TT3D 0x9135
-
-#define PCI_VENDOR_ID_TEKRAM2 0x10e1
-#define PCI_DEVICE_ID_TEKRAM2_690c 0x690c
-
-#define PCI_VENDOR_ID_TUNDRA 0x10e3
-#define PCI_DEVICE_ID_TUNDRA_CA91C042 0x0000
-
-#define PCI_VENDOR_ID_AMCC 0x10e8
-#define PCI_DEVICE_ID_AMCC_MYRINET 0x8043
-#define PCI_DEVICE_ID_AMCC_PARASTATION 0x8062
-#define PCI_DEVICE_ID_AMCC_S5933 0x807d
-#define PCI_DEVICE_ID_AMCC_S5933_HEPC3 0x809c
-
-#define PCI_VENDOR_ID_INTERG 0x10ea
-#define PCI_DEVICE_ID_INTERG_1680 0x1680
-#define PCI_DEVICE_ID_INTERG_1682 0x1682
-#define PCI_DEVICE_ID_INTERG_2000 0x2000
-#define PCI_DEVICE_ID_INTERG_2010 0x2010
-#define PCI_DEVICE_ID_INTERG_5000 0x5000
-#define PCI_DEVICE_ID_INTERG_5050 0x5050
-
-#define PCI_VENDOR_ID_REALTEK 0x10ec
-#define PCI_DEVICE_ID_REALTEK_8029 0x8029
-#define PCI_DEVICE_ID_REALTEK_8129 0x8129
-#define PCI_DEVICE_ID_REALTEK_8139 0x8139
-#define PCI_DEVICE_ID_REALTEK_8169 0x8169
-
-#define PCI_VENDOR_ID_DLINK 0x1186
-#define PCI_DEVICE_ID_DLINK_8139 0x1300
-
-#define PCI_VENDOR_ID_XILINX 0x10ee
-#define PCI_DEVICE_ID_TURBOPAM 0x4020
-
-#define PCI_VENDOR_ID_TRUEVISION 0x10fa
-#define PCI_DEVICE_ID_TRUEVISION_T1000 0x000c
-
-#define PCI_VENDOR_ID_INIT 0x1101
-#define PCI_DEVICE_ID_INIT_320P 0x9100
-#define PCI_DEVICE_ID_INIT_360P 0x9500
-
-#define PCI_VENDOR_ID_CREATIVE 0x1102 /* duplicate: ECTIVA */
-#define PCI_DEVICE_ID_CREATIVE_EMU10K1 0x0002
-
-#define PCI_VENDOR_ID_ECTIVA 0x1102 /* duplicate: CREATIVE */
-#define PCI_DEVICE_ID_ECTIVA_EV1938 0x8938
-
-#define PCI_VENDOR_ID_TTI 0x1103
-#define PCI_DEVICE_ID_TTI_HPT343 0x0003
-#define PCI_DEVICE_ID_TTI_HPT366 0x0004
-#define PCI_DEVICE_ID_TTI_HPT372 0x0005
-#define PCI_DEVICE_ID_TTI_HPT302 0x0006
-#define PCI_DEVICE_ID_TTI_HPT371 0x0007
-#define PCI_DEVICE_ID_TTI_HPT374 0x0008
-#define PCI_DEVICE_ID_TTI_HPT372N 0x0009 /* appoarently a 372N variant? */
-
-#define PCI_VENDOR_ID_VIA 0x1106
-#define PCI_DEVICE_ID_VIA_8363_0 0x0305
-#define PCI_DEVICE_ID_VIA_8371_0 0x0391
-#define PCI_DEVICE_ID_VIA_8501_0 0x0501
-#define PCI_DEVICE_ID_VIA_82C505 0x0505
-#define PCI_DEVICE_ID_VIA_82C561 0x0561
-#define PCI_DEVICE_ID_VIA_82C586_1 0x0571
-#define PCI_DEVICE_ID_VIA_82C576 0x0576
-#define PCI_DEVICE_ID_VIA_82C585 0x0585
-#define PCI_DEVICE_ID_VIA_82C586_0 0x0586
-#define PCI_DEVICE_ID_VIA_82C595 0x0595
-#define PCI_DEVICE_ID_VIA_82C596 0x0596
-#define PCI_DEVICE_ID_VIA_82C597_0 0x0597
-#define PCI_DEVICE_ID_VIA_82C598_0 0x0598
-#define PCI_DEVICE_ID_VIA_8601_0 0x0601
-#define PCI_DEVICE_ID_VIA_8605_0 0x0605
-#define PCI_DEVICE_ID_VIA_82C680 0x0680
-#define PCI_DEVICE_ID_VIA_82C686 0x0686
-#define PCI_DEVICE_ID_VIA_82C691 0x0691
-#define PCI_DEVICE_ID_VIA_82C693 0x0693
-#define PCI_DEVICE_ID_VIA_82C693_1 0x0698
-#define PCI_DEVICE_ID_VIA_82C926 0x0926
-#define PCI_DEVICE_ID_VIA_82C576_1 0x1571
-#define PCI_DEVICE_ID_VIA_82C595_97 0x1595
-#define PCI_DEVICE_ID_VIA_82C586_2 0x3038
-#define PCI_DEVICE_ID_VIA_82C586_3 0x3040
-#define PCI_DEVICE_ID_VIA_6305 0x3044
-#define PCI_DEVICE_ID_VIA_82C596_3 0x3050
-#define PCI_DEVICE_ID_VIA_82C596B_3 0x3051
-#define PCI_DEVICE_ID_VIA_82C686_4 0x3057
-#define PCI_DEVICE_ID_VIA_82C686_5 0x3058
-#define PCI_DEVICE_ID_VIA_8233_5 0x3059
-#define PCI_DEVICE_ID_VIA_8233_7 0x3065
-#define PCI_DEVICE_ID_VIA_82C686_6 0x3068
-#define PCI_DEVICE_ID_VIA_8233_0 0x3074
-#define PCI_DEVICE_ID_VIA_8633_0 0x3091
-#define PCI_DEVICE_ID_VIA_8367_0 0x3099
-#define PCI_DEVICE_ID_VIA_8622 0x3102
-#define PCI_DEVICE_ID_VIA_8233C_0 0x3109
-#define PCI_DEVICE_ID_VIA_8361 0x3112
-#define PCI_DEVICE_ID_VIA_8375 0x3116
-#define PCI_DEVICE_ID_VIA_CLE266 0x3123
-#define PCI_DEVICE_ID_VIA_8233A 0x3147
-#define PCI_DEVICE_ID_VIA_P4M266 0x3148
-#define PCI_DEVICE_ID_VIA_8237_SATA 0x3149
-#define PCI_DEVICE_ID_VIA_P4X333 0x3168
-#define PCI_DEVICE_ID_VIA_8235 0x3177
-#define PCI_DEVICE_ID_VIA_8377_0 0x3189
-#define PCI_DEVICE_ID_VIA_K8T400M_0 0x3188
-#define PCI_DEVICE_ID_VIA_8237 0x3227
-#define PCI_DEVICE_ID_VIA_86C100A 0x6100
-#define PCI_DEVICE_ID_VIA_8231 0x8231
-#define PCI_DEVICE_ID_VIA_8231_4 0x8235
-#define PCI_DEVICE_ID_VIA_8365_1 0x8305
-#define PCI_DEVICE_ID_VIA_8371_1 0x8391
-#define PCI_DEVICE_ID_VIA_8501_1 0x8501
-#define PCI_DEVICE_ID_VIA_82C597_1 0x8597
-#define PCI_DEVICE_ID_VIA_82C598_1 0x8598
-#define PCI_DEVICE_ID_VIA_8601_1 0x8601
-#define PCI_DEVICE_ID_VIA_8505_1 0x8605
-#define PCI_DEVICE_ID_VIA_8633_1 0xB091
-#define PCI_DEVICE_ID_VIA_8367_1 0xB099
-
-#define PCI_VENDOR_ID_SIEMENS 0x110A
-#define PCI_DEVICE_ID_SIEMENS_DSCC4 0x2102
-
-#define PCI_VENDOR_ID_SMC2 0x1113
-#define PCI_DEVICE_ID_SMC2_1211TX 0x1211
-
-#define PCI_VENDOR_ID_VORTEX 0x1119
-#define PCI_DEVICE_ID_VORTEX_GDT60x0 0x0000
-#define PCI_DEVICE_ID_VORTEX_GDT6000B 0x0001
-#define PCI_DEVICE_ID_VORTEX_GDT6x10 0x0002
-#define PCI_DEVICE_ID_VORTEX_GDT6x20 0x0003
-#define PCI_DEVICE_ID_VORTEX_GDT6530 0x0004
-#define PCI_DEVICE_ID_VORTEX_GDT6550 0x0005
-#define PCI_DEVICE_ID_VORTEX_GDT6x17 0x0006
-#define PCI_DEVICE_ID_VORTEX_GDT6x27 0x0007
-#define PCI_DEVICE_ID_VORTEX_GDT6537 0x0008
-#define PCI_DEVICE_ID_VORTEX_GDT6557 0x0009
-#define PCI_DEVICE_ID_VORTEX_GDT6x15 0x000a
-#define PCI_DEVICE_ID_VORTEX_GDT6x25 0x000b
-#define PCI_DEVICE_ID_VORTEX_GDT6535 0x000c
-#define PCI_DEVICE_ID_VORTEX_GDT6555 0x000d
-#define PCI_DEVICE_ID_VORTEX_GDT6x17RP 0x0100
-#define PCI_DEVICE_ID_VORTEX_GDT6x27RP 0x0101
-#define PCI_DEVICE_ID_VORTEX_GDT6537RP 0x0102
-#define PCI_DEVICE_ID_VORTEX_GDT6557RP 0x0103
-#define PCI_DEVICE_ID_VORTEX_GDT6x11RP 0x0104
-#define PCI_DEVICE_ID_VORTEX_GDT6x21RP 0x0105
-#define PCI_DEVICE_ID_VORTEX_GDT6x17RP1 0x0110
-#define PCI_DEVICE_ID_VORTEX_GDT6x27RP1 0x0111
-#define PCI_DEVICE_ID_VORTEX_GDT6537RP1 0x0112
-#define PCI_DEVICE_ID_VORTEX_GDT6557RP1 0x0113
-#define PCI_DEVICE_ID_VORTEX_GDT6x11RP1 0x0114
-#define PCI_DEVICE_ID_VORTEX_GDT6x21RP1 0x0115
-#define PCI_DEVICE_ID_VORTEX_GDT6x17RP2 0x0120
-#define PCI_DEVICE_ID_VORTEX_GDT6x27RP2 0x0121
-#define PCI_DEVICE_ID_VORTEX_GDT6537RP2 0x0122
-#define PCI_DEVICE_ID_VORTEX_GDT6557RP2 0x0123
-#define PCI_DEVICE_ID_VORTEX_GDT6x11RP2 0x0124
-#define PCI_DEVICE_ID_VORTEX_GDT6x21RP2 0x0125
-
-#define PCI_VENDOR_ID_EF 0x111a
-#define PCI_DEVICE_ID_EF_ATM_FPGA 0x0000
-#define PCI_DEVICE_ID_EF_ATM_ASIC 0x0002
-
-#define PCI_VENDOR_ID_IDT 0x111d
-#define PCI_DEVICE_ID_IDT_IDT77201 0x0001
-
-#define PCI_VENDOR_ID_FORE 0x1127
-#define PCI_DEVICE_ID_FORE_PCA200PC 0x0210
-#define PCI_DEVICE_ID_FORE_PCA200E 0x0300
-
-#define PCI_VENDOR_ID_IMAGINGTECH 0x112f
-#define PCI_DEVICE_ID_IMAGINGTECH_ICPCI 0x0000
-
-#define PCI_VENDOR_ID_PHILIPS 0x1131
-#define PCI_DEVICE_ID_PHILIPS_SAA7145 0x7145
-#define PCI_DEVICE_ID_PHILIPS_SAA7146 0x7146
-#define PCI_DEVICE_ID_PHILIPS_SAA9730 0x9730
-
-#define PCI_VENDOR_ID_EICON 0x1133
-#define PCI_DEVICE_ID_EICON_DIVA20PRO 0xe001
-#define PCI_DEVICE_ID_EICON_DIVA20 0xe002
-#define PCI_DEVICE_ID_EICON_DIVA20PRO_U 0xe003
-#define PCI_DEVICE_ID_EICON_DIVA20_U 0xe004
-#define PCI_DEVICE_ID_EICON_DIVA201 0xe005
-#define PCI_DEVICE_ID_EICON_DIVA202 0xe00b
-#define PCI_DEVICE_ID_EICON_MAESTRA 0xe010
-#define PCI_DEVICE_ID_EICON_MAESTRAQ 0xe012
-#define PCI_DEVICE_ID_EICON_MAESTRAQ_U 0xe013
-#define PCI_DEVICE_ID_EICON_MAESTRAP 0xe014
-
-#define PCI_VENDOR_ID_CYCLONE 0x113c
-#define PCI_DEVICE_ID_CYCLONE_SDK 0x0001
-
-#define PCI_VENDOR_ID_ALLIANCE 0x1142
-#define PCI_DEVICE_ID_ALLIANCE_PROMOTIO 0x3210
-#define PCI_DEVICE_ID_ALLIANCE_PROVIDEO 0x6422
-#define PCI_DEVICE_ID_ALLIANCE_AT24 0x6424
-#define PCI_DEVICE_ID_ALLIANCE_AT3D 0x643d
-
-#define PCI_VENDOR_ID_SYSKONNECT 0x1148
-#define PCI_DEVICE_ID_SYSKONNECT_FP 0x4000
-#define PCI_DEVICE_ID_SYSKONNECT_TR 0x4200
-#define PCI_DEVICE_ID_SYSKONNECT_GE 0x4300
-#define PCI_DEVICE_ID_SYSKONNECT_YU 0x4320
-#define PCI_DEVICE_ID_SYSKONNECT_9DXX 0x4400
-#define PCI_DEVICE_ID_SYSKONNECT_9MXX 0x4500
-
-#define PCI_VENDOR_ID_VMIC 0x114a
-#define PCI_DEVICE_ID_VMIC_VME 0x7587
-
-#define PCI_VENDOR_ID_DIGI 0x114f
-#define PCI_DEVICE_ID_DIGI_EPC 0x0002
-#define PCI_DEVICE_ID_DIGI_RIGHTSWITCH 0x0003
-#define PCI_DEVICE_ID_DIGI_XEM 0x0004
-#define PCI_DEVICE_ID_DIGI_XR 0x0005
-#define PCI_DEVICE_ID_DIGI_CX 0x0006
-#define PCI_DEVICE_ID_DIGI_XRJ 0x0009
-#define PCI_DEVICE_ID_DIGI_EPCJ 0x000a
-#define PCI_DEVICE_ID_DIGI_XR_920 0x0027
-#define PCI_DEVICE_ID_DIGI_DF_M_IOM2_E 0x0070
-#define PCI_DEVICE_ID_DIGI_DF_M_E 0x0071
-#define PCI_DEVICE_ID_DIGI_DF_M_IOM2_A 0x0072
-#define PCI_DEVICE_ID_DIGI_DF_M_A 0x0073
-
-#define PCI_VENDOR_ID_MUTECH 0x1159
-#define PCI_DEVICE_ID_MUTECH_MV1000 0x0001
-
-#define PCI_VENDOR_ID_XIRCOM 0x115d
-#define PCI_DEVICE_ID_XIRCOM_X3201_ETH 0x0003
-#define PCI_DEVICE_ID_XIRCOM_X3201_MDM 0x0103
-
-#define PCI_VENDOR_ID_RENDITION 0x1163
-#define PCI_DEVICE_ID_RENDITION_VERITE 0x0001
-#define PCI_DEVICE_ID_RENDITION_VERITE2100 0x2000
-
-#define PCI_VENDOR_ID_SERVERWORKS 0x1166
-#define PCI_DEVICE_ID_SERVERWORKS_HE 0x0008
-#define PCI_DEVICE_ID_SERVERWORKS_LE 0x0009
-#define PCI_DEVICE_ID_SERVERWORKS_CIOB30 0x0010
-#define PCI_DEVICE_ID_SERVERWORKS_CMIC_HE 0x0011
-#define PCI_DEVICE_ID_SERVERWORKS_GCNB_LE 0x0017
-#define PCI_DEVICE_ID_SERVERWORKS_OSB4 0x0200
-#define PCI_DEVICE_ID_SERVERWORKS_CSB5 0x0201
-#define PCI_DEVICE_ID_SERVERWORKS_CSB6 0x0203
-#define PCI_DEVICE_ID_SERVERWORKS_OSB4IDE 0x0211
-#define PCI_DEVICE_ID_SERVERWORKS_CSB5IDE 0x0212
-#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE 0x0213
-#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2 0x0217
-#define PCI_DEVICE_ID_SERVERWORKS_OSB4USB 0x0220
-#define PCI_DEVICE_ID_SERVERWORKS_CSB5USB PCI_DEVICE_ID_SERVERWORKS_OSB4USB
-#define PCI_DEVICE_ID_SERVERWORKS_CSB6USB 0x0221
-#define PCI_DEVICE_ID_SERVERWORKS_GCLE 0x0225
-#define PCI_DEVICE_ID_SERVERWORKS_GCLE2 0x0227
-#define PCI_DEVICE_ID_SERVERWORKS_CSB5ISA 0x0230
-
-#define PCI_VENDOR_ID_SBE 0x1176
-#define PCI_DEVICE_ID_SBE_WANXL100 0x0301
-#define PCI_DEVICE_ID_SBE_WANXL200 0x0302
-#define PCI_DEVICE_ID_SBE_WANXL400 0x0104
-
-#define PCI_VENDOR_ID_TOSHIBA 0x1179
-#define PCI_DEVICE_ID_TOSHIBA_PICCOLO 0x0102
-#define PCI_DEVICE_ID_TOSHIBA_601 0x0601
-#define PCI_DEVICE_ID_TOSHIBA_TOPIC95 0x060a
-#define PCI_DEVICE_ID_TOSHIBA_TOPIC97 0x060f
-
-#define PCI_VENDOR_ID_TOSHIBA_2 0x102f
-#define PCI_DEVICE_ID_TOSHIBA_TX3927 0x000a
-#define PCI_DEVICE_ID_TOSHIBA_TC35815CF 0x0030
-#define PCI_DEVICE_ID_TOSHIBA_TX4927 0x0180
-
-#define PCI_VENDOR_ID_RICOH 0x1180
-#define PCI_DEVICE_ID_RICOH_RL5C465 0x0465
-#define PCI_DEVICE_ID_RICOH_RL5C466 0x0466
-#define PCI_DEVICE_ID_RICOH_RL5C475 0x0475
-#define PCI_DEVICE_ID_RICOH_RL5C476 0x0476
-#define PCI_DEVICE_ID_RICOH_RL5C478 0x0478
-
-#define PCI_VENDOR_ID_ARTOP 0x1191
-#define PCI_DEVICE_ID_ARTOP_ATP8400 0x0004
-#define PCI_DEVICE_ID_ARTOP_ATP850UF 0x0005
-#define PCI_DEVICE_ID_ARTOP_ATP860 0x0006
-#define PCI_DEVICE_ID_ARTOP_ATP860R 0x0007
-#define PCI_DEVICE_ID_ARTOP_ATP865 0x0008
-#define PCI_DEVICE_ID_ARTOP_ATP865R 0x0009
-#define PCI_DEVICE_ID_ARTOP_AEC7610 0x8002
-#define PCI_DEVICE_ID_ARTOP_AEC7612UW 0x8010
-#define PCI_DEVICE_ID_ARTOP_AEC7612U 0x8020
-#define PCI_DEVICE_ID_ARTOP_AEC7612S 0x8030
-#define PCI_DEVICE_ID_ARTOP_AEC7612D 0x8040
-#define PCI_DEVICE_ID_ARTOP_AEC7612SUW 0x8050
-#define PCI_DEVICE_ID_ARTOP_8060 0x8060
-
-#define PCI_VENDOR_ID_ZEITNET 0x1193
-#define PCI_DEVICE_ID_ZEITNET_1221 0x0001
-#define PCI_DEVICE_ID_ZEITNET_1225 0x0002
-
-#define PCI_VENDOR_ID_OMEGA 0x119b
-#define PCI_DEVICE_ID_OMEGA_82C092G 0x1221
-
-#define PCI_VENDOR_ID_FUJITSU_ME 0x119e
-#define PCI_DEVICE_ID_FUJITSU_FS155 0x0001
-#define PCI_DEVICE_ID_FUJITSU_FS50 0x0003
-
-#define PCI_SUBVENDOR_ID_KEYSPAN 0x11a9
-#define PCI_SUBDEVICE_ID_KEYSPAN_SX2 0x5334
-
-#define PCI_VENDOR_ID_GALILEO 0x11ab
-#define PCI_DEVICE_ID_GALILEO_GT64011 0x4146
-#define PCI_DEVICE_ID_GALILEO_GT64111 0x4146
-#define PCI_DEVICE_ID_GALILEO_GT96100 0x9652
-#define PCI_DEVICE_ID_GALILEO_GT96100A 0x9653
-
-#define PCI_VENDOR_ID_LITEON 0x11ad
-#define PCI_DEVICE_ID_LITEON_LNE100TX 0x0002
-
-#define PCI_VENDOR_ID_V3 0x11b0
-#define PCI_DEVICE_ID_V3_V960 0x0001
-#define PCI_DEVICE_ID_V3_V350 0x0001
-#define PCI_DEVICE_ID_V3_V961 0x0002
-#define PCI_DEVICE_ID_V3_V351 0x0002
-
-#define PCI_VENDOR_ID_NP 0x11bc
-#define PCI_DEVICE_ID_NP_PCI_FDDI 0x0001
-
-#define PCI_VENDOR_ID_ATT 0x11c1
-#define PCI_DEVICE_ID_ATT_L56XMF 0x0440
-#define PCI_DEVICE_ID_ATT_VENUS_MODEM 0x480
-
-#define PCI_VENDOR_ID_SPECIALIX 0x11cb
-#define PCI_DEVICE_ID_SPECIALIX_IO8 0x2000
-#define PCI_DEVICE_ID_SPECIALIX_XIO 0x4000
-#define PCI_DEVICE_ID_SPECIALIX_RIO 0x8000
-#define PCI_SUBDEVICE_ID_SPECIALIX_SPEED4 0xa004
-
-#define PCI_VENDOR_ID_AURAVISION 0x11d1
-#define PCI_DEVICE_ID_AURAVISION_VXP524 0x01f7
-
-#define PCI_VENDOR_ID_ANALOG_DEVICES 0x11d4
-#define PCI_DEVICE_ID_AD1889JS 0x1889
-
-#define PCI_VENDOR_ID_IKON 0x11d5
-#define PCI_DEVICE_ID_IKON_10115 0x0115
-#define PCI_DEVICE_ID_IKON_10117 0x0117
-
-#define PCI_VENDOR_ID_ZORAN 0x11de
-#define PCI_DEVICE_ID_ZORAN_36057 0x6057
-#define PCI_DEVICE_ID_ZORAN_36120 0x6120
-
-#define PCI_VENDOR_ID_KINETIC 0x11f4
-#define PCI_DEVICE_ID_KINETIC_2915 0x2915
-
-#define PCI_VENDOR_ID_COMPEX 0x11f6
-#define PCI_DEVICE_ID_COMPEX_ENET100VG4 0x0112
-#define PCI_DEVICE_ID_COMPEX_RL2000 0x1401
-
-#define PCI_VENDOR_ID_RP 0x11fe
-#define PCI_DEVICE_ID_RP32INTF 0x0001
-#define PCI_DEVICE_ID_RP8INTF 0x0002
-#define PCI_DEVICE_ID_RP16INTF 0x0003
-#define PCI_DEVICE_ID_RP4QUAD 0x0004
-#define PCI_DEVICE_ID_RP8OCTA 0x0005
-#define PCI_DEVICE_ID_RP8J 0x0006
-#define PCI_DEVICE_ID_RPP4 0x000A
-#define PCI_DEVICE_ID_RPP8 0x000B
-#define PCI_DEVICE_ID_RP8M 0x000C
-
-#define PCI_VENDOR_ID_CYCLADES 0x120e
-#define PCI_DEVICE_ID_CYCLOM_Y_Lo 0x0100
-#define PCI_DEVICE_ID_CYCLOM_Y_Hi 0x0101
-#define PCI_DEVICE_ID_CYCLOM_4Y_Lo 0x0102
-#define PCI_DEVICE_ID_CYCLOM_4Y_Hi 0x0103
-#define PCI_DEVICE_ID_CYCLOM_8Y_Lo 0x0104
-#define PCI_DEVICE_ID_CYCLOM_8Y_Hi 0x0105
-#define PCI_DEVICE_ID_CYCLOM_Z_Lo 0x0200
-#define PCI_DEVICE_ID_CYCLOM_Z_Hi 0x0201
-#define PCI_DEVICE_ID_PC300_RX_2 0x0300
-#define PCI_DEVICE_ID_PC300_RX_1 0x0301
-#define PCI_DEVICE_ID_PC300_TE_2 0x0310
-#define PCI_DEVICE_ID_PC300_TE_1 0x0311
-
-#define PCI_VENDOR_ID_ESSENTIAL 0x120f
-#define PCI_DEVICE_ID_ESSENTIAL_ROADRUNNER 0x0001
-
-#define PCI_VENDOR_ID_O2 0x1217
-#define PCI_DEVICE_ID_O2_6729 0x6729
-#define PCI_DEVICE_ID_O2_6730 0x673a
-#define PCI_DEVICE_ID_O2_6832 0x6832
-#define PCI_DEVICE_ID_O2_6836 0x6836
-
-#define PCI_VENDOR_ID_3DFX 0x121a
-#define PCI_DEVICE_ID_3DFX_VOODOO 0x0001
-#define PCI_DEVICE_ID_3DFX_VOODOO2 0x0002
-#define PCI_DEVICE_ID_3DFX_BANSHEE 0x0003
-#define PCI_DEVICE_ID_3DFX_VOODOO3 0x0005
-
-#define PCI_VENDOR_ID_SIGMADES 0x1236
-#define PCI_DEVICE_ID_SIGMADES_6425 0x6401
-
-#define PCI_VENDOR_ID_CCUBE 0x123f
-
-#define PCI_VENDOR_ID_AVM 0x1244
-#define PCI_DEVICE_ID_AVM_B1 0x0700
-#define PCI_DEVICE_ID_AVM_C4 0x0800
-#define PCI_DEVICE_ID_AVM_A1 0x0a00
-#define PCI_DEVICE_ID_AVM_A1_V2 0x0e00
-#define PCI_DEVICE_ID_AVM_C2 0x1100
-#define PCI_DEVICE_ID_AVM_T1 0x1200
-
-#define PCI_VENDOR_ID_DIPIX 0x1246
-
-#define PCI_VENDOR_ID_STALLION 0x124d
-#define PCI_DEVICE_ID_STALLION_ECHPCI832 0x0000
-#define PCI_DEVICE_ID_STALLION_ECHPCI864 0x0002
-#define PCI_DEVICE_ID_STALLION_EIOPCI 0x0003
-
-#define PCI_VENDOR_ID_OPTIBASE 0x1255
-#define PCI_DEVICE_ID_OPTIBASE_FORGE 0x1110
-#define PCI_DEVICE_ID_OPTIBASE_FUSION 0x1210
-#define PCI_DEVICE_ID_OPTIBASE_VPLEX 0x2110
-#define PCI_DEVICE_ID_OPTIBASE_VPLEXCC 0x2120
-#define PCI_DEVICE_ID_OPTIBASE_VQUEST 0x2130
-
-#define PCI_VENDOR_ID_ESS 0x125d
-#define PCI_DEVICE_ID_ESS_ESS1968 0x1968
-#define PCI_DEVICE_ID_ESS_AUDIOPCI 0x1969
-#define PCI_DEVICE_ID_ESS_ESS1978 0x1978
-
-#define PCI_VENDOR_ID_SATSAGEM 0x1267
-#define PCI_DEVICE_ID_SATSAGEM_NICCY 0x1016
-#define PCI_DEVICE_ID_SATSAGEM_PCR2101 0x5352
-#define PCI_DEVICE_ID_SATSAGEM_TELSATTURBO 0x5a4b
-
-#define PCI_VENDOR_ID_SMI 0x126f
-#define PCI_DEVICE_ID_SMI_710 0x0710
-#define PCI_DEVICE_ID_SMI_712 0x0712
-#define PCI_DEVICE_ID_SMI_810 0x0810
-
-#define PCI_VENDOR_ID_HUGHES 0x1273
-#define PCI_DEVICE_ID_HUGHES_DIRECPC 0x0002
-
-#define PCI_VENDOR_ID_ENSONIQ 0x1274
-#define PCI_DEVICE_ID_ENSONIQ_CT5880 0x5880
-#define PCI_DEVICE_ID_ENSONIQ_ES1370 0x5000
-#define PCI_DEVICE_ID_ENSONIQ_ES1371 0x1371
-
-#define PCI_VENDOR_ID_ROCKWELL 0x127A
-
-#define PCI_VENDOR_ID_DAVICOM 0x1282
-#define PCI_DEVICE_ID_DAVICOM_DM9102A 0x9102
-
-#define PCI_VENDOR_ID_ITE 0x1283
-#define PCI_DEVICE_ID_ITE_IT8172G 0x8172
-#define PCI_DEVICE_ID_ITE_IT8172G_AUDIO 0x0801
-#define PCI_DEVICE_ID_ITE_IT8181 0x8181
-#define PCI_DEVICE_ID_ITE_8872 0x8872
-
-#define PCI_DEVICE_ID_ITE_IT8330G_0 0xe886
-
-/* formerly Platform Tech */
-#define PCI_VENDOR_ID_ESS_OLD 0x1285
-#define PCI_DEVICE_ID_ESS_ESS0100 0x0100
-
-#define PCI_VENDOR_ID_ALTEON 0x12ae
-#define PCI_DEVICE_ID_ALTEON_ACENIC 0x0001
-
-#define PCI_VENDOR_ID_USR 0x12B9
-
-#define PCI_SUBVENDOR_ID_CONNECT_TECH 0x12c4
-#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232 0x0001
-#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232 0x0002
-#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232 0x0003
-#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485 0x0004
-#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4 0x0005
-#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485 0x0006
-#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2 0x0007
-#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485 0x0008
-#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6 0x0009
-#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1 0x000A
-#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1 0x000B
-
-#define PCI_VENDOR_ID_PICTUREL 0x12c5
-#define PCI_DEVICE_ID_PICTUREL_PCIVST 0x0081
-
-#define PCI_VENDOR_ID_NVIDIA_SGS 0x12d2
-#define PCI_DEVICE_ID_NVIDIA_SGS_RIVA128 0x0018
-
-#define PCI_SUBVENDOR_ID_CHASE_PCIFAST 0x12E0
-#define PCI_SUBDEVICE_ID_CHASE_PCIFAST4 0x0031
-#define PCI_SUBDEVICE_ID_CHASE_PCIFAST8 0x0021
-#define PCI_SUBDEVICE_ID_CHASE_PCIFAST16 0x0011
-#define PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC 0x0041
-#define PCI_SUBVENDOR_ID_CHASE_PCIRAS 0x124D
-#define PCI_SUBDEVICE_ID_CHASE_PCIRAS4 0xF001
-#define PCI_SUBDEVICE_ID_CHASE_PCIRAS8 0xF010
-
-#define PCI_VENDOR_ID_AUREAL 0x12eb
-#define PCI_DEVICE_ID_AUREAL_VORTEX_1 0x0001
-#define PCI_DEVICE_ID_AUREAL_VORTEX_2 0x0002
-
-#define PCI_VENDOR_ID_CBOARDS 0x1307
-#define PCI_DEVICE_ID_CBOARDS_DAS1602_16 0x0001
-
-#define PCI_VENDOR_ID_SIIG 0x131f
-#define PCI_DEVICE_ID_SIIG_1S_10x_550 0x1000
-#define PCI_DEVICE_ID_SIIG_1S_10x_650 0x1001
-#define PCI_DEVICE_ID_SIIG_1S_10x_850 0x1002
-#define PCI_DEVICE_ID_SIIG_1S1P_10x_550 0x1010
-#define PCI_DEVICE_ID_SIIG_1S1P_10x_650 0x1011
-#define PCI_DEVICE_ID_SIIG_1S1P_10x_850 0x1012
-#define PCI_DEVICE_ID_SIIG_1P_10x 0x1020
-#define PCI_DEVICE_ID_SIIG_2P_10x 0x1021
-#define PCI_DEVICE_ID_SIIG_2S_10x_550 0x1030
-#define PCI_DEVICE_ID_SIIG_2S_10x_650 0x1031
-#define PCI_DEVICE_ID_SIIG_2S_10x_850 0x1032
-#define PCI_DEVICE_ID_SIIG_2S1P_10x_550 0x1034
-#define PCI_DEVICE_ID_SIIG_2S1P_10x_650 0x1035
-#define PCI_DEVICE_ID_SIIG_2S1P_10x_850 0x1036
-#define PCI_DEVICE_ID_SIIG_4S_10x_550 0x1050
-#define PCI_DEVICE_ID_SIIG_4S_10x_650 0x1051
-#define PCI_DEVICE_ID_SIIG_4S_10x_850 0x1052
-#define PCI_DEVICE_ID_SIIG_1S_20x_550 0x2000
-#define PCI_DEVICE_ID_SIIG_1S_20x_650 0x2001
-#define PCI_DEVICE_ID_SIIG_1S_20x_850 0x2002
-#define PCI_DEVICE_ID_SIIG_1P_20x 0x2020
-#define PCI_DEVICE_ID_SIIG_2P_20x 0x2021
-#define PCI_DEVICE_ID_SIIG_2S_20x_550 0x2030
-#define PCI_DEVICE_ID_SIIG_2S_20x_650 0x2031
-#define PCI_DEVICE_ID_SIIG_2S_20x_850 0x2032
-#define PCI_DEVICE_ID_SIIG_2P1S_20x_550 0x2040
-#define PCI_DEVICE_ID_SIIG_2P1S_20x_650 0x2041
-#define PCI_DEVICE_ID_SIIG_2P1S_20x_850 0x2042
-#define PCI_DEVICE_ID_SIIG_1S1P_20x_550 0x2010
-#define PCI_DEVICE_ID_SIIG_1S1P_20x_650 0x2011
-#define PCI_DEVICE_ID_SIIG_1S1P_20x_850 0x2012
-#define PCI_DEVICE_ID_SIIG_4S_20x_550 0x2050
-#define PCI_DEVICE_ID_SIIG_4S_20x_650 0x2051
-#define PCI_DEVICE_ID_SIIG_4S_20x_850 0x2052
-#define PCI_DEVICE_ID_SIIG_2S1P_20x_550 0x2060
-#define PCI_DEVICE_ID_SIIG_2S1P_20x_650 0x2061
-#define PCI_DEVICE_ID_SIIG_2S1P_20x_850 0x2062
-
-#define PCI_VENDOR_ID_DOMEX 0x134a
-#define PCI_DEVICE_ID_DOMEX_DMX3191D 0x0001
-
-#define PCI_VENDOR_ID_QUATECH 0x135C
-#define PCI_DEVICE_ID_QUATECH_QSC100 0x0010
-#define PCI_DEVICE_ID_QUATECH_DSC100 0x0020
-#define PCI_DEVICE_ID_QUATECH_DSC200 0x0030
-#define PCI_DEVICE_ID_QUATECH_QSC200 0x0040
-#define PCI_DEVICE_ID_QUATECH_ESC100D 0x0050
-#define PCI_DEVICE_ID_QUATECH_ESC100M 0x0060
-
-#define PCI_VENDOR_ID_SEALEVEL 0x135e
-#define PCI_DEVICE_ID_SEALEVEL_U530 0x7101
-#define PCI_DEVICE_ID_SEALEVEL_UCOMM2 0x7201
-#define PCI_DEVICE_ID_SEALEVEL_UCOMM422 0x7402
-#define PCI_DEVICE_ID_SEALEVEL_UCOMM232 0x7202
-#define PCI_DEVICE_ID_SEALEVEL_COMM4 0x7401
-#define PCI_DEVICE_ID_SEALEVEL_COMM8 0x7801
-
-#define PCI_VENDOR_ID_HYPERCOPE 0x1365
-#define PCI_DEVICE_ID_HYPERCOPE_PLX 0x9050
-#define PCI_SUBDEVICE_ID_HYPERCOPE_OLD_ERGO 0x0104
-#define PCI_SUBDEVICE_ID_HYPERCOPE_ERGO 0x0106
-#define PCI_SUBDEVICE_ID_HYPERCOPE_METRO 0x0107
-#define PCI_SUBDEVICE_ID_HYPERCOPE_CHAMP2 0x0108
-#define PCI_SUBDEVICE_ID_HYPERCOPE_PLEXUS 0x0109
-
-#define PCI_VENDOR_ID_KAWASAKI 0x136b
-#define PCI_DEVICE_ID_MCHIP_KL5A72002 0xff01
-
-#define PCI_VENDOR_ID_LMC 0x1376
-#define PCI_DEVICE_ID_LMC_HSSI 0x0003
-#define PCI_DEVICE_ID_LMC_DS3 0x0004
-#define PCI_DEVICE_ID_LMC_SSI 0x0005
-#define PCI_DEVICE_ID_LMC_T1 0x0006
-
-#define PCI_VENDOR_ID_NETGEAR 0x1385
-#define PCI_DEVICE_ID_NETGEAR_GA620 0x620a
-#define PCI_DEVICE_ID_NETGEAR_GA622 0x622a
-
-#define PCI_VENDOR_ID_APPLICOM 0x1389
-#define PCI_DEVICE_ID_APPLICOM_PCIGENERIC 0x0001
-#define PCI_DEVICE_ID_APPLICOM_PCI2000IBS_CAN 0x0002
-#define PCI_DEVICE_ID_APPLICOM_PCI2000PFB 0x0003
-
-#define PCI_VENDOR_ID_MOXA 0x1393
-#define PCI_DEVICE_ID_MOXA_C104 0x1040
-#define PCI_DEVICE_ID_MOXA_C168 0x1680
-#define PCI_DEVICE_ID_MOXA_CP204J 0x2040
-#define PCI_DEVICE_ID_MOXA_C218 0x2180
-#define PCI_DEVICE_ID_MOXA_C320 0x3200
-
-#define PCI_VENDOR_ID_CCD 0x1397
-#define PCI_DEVICE_ID_CCD_2BD0 0x2bd0
-#define PCI_DEVICE_ID_CCD_B000 0xb000
-#define PCI_DEVICE_ID_CCD_B006 0xb006
-#define PCI_DEVICE_ID_CCD_B007 0xb007
-#define PCI_DEVICE_ID_CCD_B008 0xb008
-#define PCI_DEVICE_ID_CCD_B009 0xb009
-#define PCI_DEVICE_ID_CCD_B00A 0xb00a
-#define PCI_DEVICE_ID_CCD_B00B 0xb00b
-#define PCI_DEVICE_ID_CCD_B00C 0xb00c
-#define PCI_DEVICE_ID_CCD_B100 0xb100
-
-#define PCI_VENDOR_ID_3WARE 0x13C1
-#define PCI_DEVICE_ID_3WARE_1000 0x1000
-
-#define PCI_VENDOR_ID_ABOCOM 0x13D1
-#define PCI_DEVICE_ID_ABOCOM_2BD1 0x2BD1
-
-#define PCI_VENDOR_ID_CMEDIA 0x13f6
-#define PCI_DEVICE_ID_CMEDIA_CM8338A 0x0100
-#define PCI_DEVICE_ID_CMEDIA_CM8338B 0x0101
-#define PCI_DEVICE_ID_CMEDIA_CM8738 0x0111
-#define PCI_DEVICE_ID_CMEDIA_CM8738B 0x0112
-
-#define PCI_VENDOR_ID_LAVA 0x1407
-#define PCI_DEVICE_ID_LAVA_DSERIAL 0x0100 /* 2x 16550 */
-#define PCI_DEVICE_ID_LAVA_QUATRO_A 0x0101 /* 2x 16550, half of 4 port */
-#define PCI_DEVICE_ID_LAVA_QUATRO_B 0x0102 /* 2x 16550, half of 4 port */
-#define PCI_DEVICE_ID_LAVA_OCTO_A 0x0180 /* 4x 16550A, half of 8 port */
-#define PCI_DEVICE_ID_LAVA_OCTO_B 0x0181 /* 4x 16550A, half of 8 port */
-#define PCI_DEVICE_ID_LAVA_PORT_PLUS 0x0200 /* 2x 16650 */
-#define PCI_DEVICE_ID_LAVA_QUAD_A 0x0201 /* 2x 16650, half of 4 port */
-#define PCI_DEVICE_ID_LAVA_QUAD_B 0x0202 /* 2x 16650, half of 4 port */
-#define PCI_DEVICE_ID_LAVA_SSERIAL 0x0500 /* 1x 16550 */
-#define PCI_DEVICE_ID_LAVA_PORT_650 0x0600 /* 1x 16650 */
-#define PCI_DEVICE_ID_LAVA_PARALLEL 0x8000
-#define PCI_DEVICE_ID_LAVA_DUAL_PAR_A 0x8002 /* The Lava Dual Parallel is */
-#define PCI_DEVICE_ID_LAVA_DUAL_PAR_B 0x8003 /* two PCI devices on a card */
-#define PCI_DEVICE_ID_LAVA_BOCA_IOPPAR 0x8800
-
-#define PCI_VENDOR_ID_TIMEDIA 0x1409
-#define PCI_DEVICE_ID_TIMEDIA_1889 0x7168
-
-#define PCI_VENDOR_ID_OXSEMI 0x1415
-#define PCI_DEVICE_ID_OXSEMI_12PCI840 0x8403
-#define PCI_DEVICE_ID_OXSEMI_16PCI954 0x9501
-#define PCI_DEVICE_ID_OXSEMI_16PCI95N 0x9511
-#define PCI_DEVICE_ID_OXSEMI_16PCI954PP 0x9513
-#define PCI_DEVICE_ID_OXSEMI_16PCI952 0x9521
-
-#define PCI_VENDOR_ID_AIRONET 0x14b9
-#define PCI_DEVICE_ID_AIRONET_4800_1 0x0001
-#define PCI_DEVICE_ID_AIRONET_4800 0x4500 /* values switched? see */
-#define PCI_DEVICE_ID_AIRONET_4500 0x4800 /* drivers/net/aironet4500_card.c */
-
-#define PCI_VENDOR_ID_TITAN 0x14D2
-#define PCI_DEVICE_ID_TITAN_010L 0x8001
-#define PCI_DEVICE_ID_TITAN_100L 0x8010
-#define PCI_DEVICE_ID_TITAN_110L 0x8011
-#define PCI_DEVICE_ID_TITAN_200L 0x8020
-#define PCI_DEVICE_ID_TITAN_210L 0x8021
-#define PCI_DEVICE_ID_TITAN_400L 0x8040
-#define PCI_DEVICE_ID_TITAN_800L 0x8080
-#define PCI_DEVICE_ID_TITAN_100 0xA001
-#define PCI_DEVICE_ID_TITAN_200 0xA005
-#define PCI_DEVICE_ID_TITAN_400 0xA003
-#define PCI_DEVICE_ID_TITAN_800B 0xA004
-
-#define PCI_VENDOR_ID_PANACOM 0x14d4
-#define PCI_DEVICE_ID_PANACOM_QUADMODEM 0x0400
-#define PCI_DEVICE_ID_PANACOM_DUALMODEM 0x0402
-
-#define PCI_VENDOR_ID_AFAVLAB 0x14db
-#define PCI_DEVICE_ID_AFAVLAB_P028 0x2180
-
-#define PCI_VENDOR_ID_BROADCOM 0x14e4
-#define PCI_DEVICE_ID_TIGON3_5700 0x1644
-#define PCI_DEVICE_ID_TIGON3_5701 0x1645
-#define PCI_DEVICE_ID_TIGON3_5702 0x1646
-#define PCI_DEVICE_ID_TIGON3_5703 0x1647
-#define PCI_DEVICE_ID_TIGON3_5704 0x1648
-#define PCI_DEVICE_ID_TIGON3_5704S_2 0x1649
-#define PCI_DEVICE_ID_TIGON3_5702FE 0x164d
-#define PCI_DEVICE_ID_TIGON3_5705 0x1653
-#define PCI_DEVICE_ID_TIGON3_5705_2 0x1654
-#define PCI_DEVICE_ID_TIGON3_5705M 0x165d
-#define PCI_DEVICE_ID_TIGON3_5705M_2 0x165e
-#define PCI_DEVICE_ID_TIGON3_5705F 0x166e
-#define PCI_DEVICE_ID_TIGON3_5782 0x1696
-#define PCI_DEVICE_ID_TIGON3_5788 0x169c
-#define PCI_DEVICE_ID_TIGON3_5702X 0x16a6
-#define PCI_DEVICE_ID_TIGON3_5703X 0x16a7
-#define PCI_DEVICE_ID_TIGON3_5704S 0x16a8
-#define PCI_DEVICE_ID_TIGON3_5702A3 0x16c6
-#define PCI_DEVICE_ID_TIGON3_5703A3 0x16c7
-#define PCI_DEVICE_ID_TIGON3_5901 0x170d
-#define PCI_DEVICE_ID_TIGON3_5901_2 0x170e
-#define PCI_DEVICE_ID_BCM4401 0x4401
-
-#define PCI_VENDOR_ID_ENE 0x1524
-#define PCI_DEVICE_ID_ENE_1211 0x1211
-#define PCI_DEVICE_ID_ENE_1225 0x1225
-#define PCI_DEVICE_ID_ENE_1410 0x1410
-#define PCI_DEVICE_ID_ENE_1420 0x1420
-
-#define PCI_VENDOR_ID_SYBA 0x1592
-#define PCI_DEVICE_ID_SYBA_2P_EPP 0x0782
-#define PCI_DEVICE_ID_SYBA_1P_ECP 0x0783
-
-#define PCI_VENDOR_ID_MORETON 0x15aa
-#define PCI_DEVICE_ID_RASTEL_2PORT 0x2000
-
-#define PCI_VENDOR_ID_ZOLTRIX 0x15b0
-#define PCI_DEVICE_ID_ZOLTRIX_2BD0 0x2bd0
-
-#define PCI_VENDOR_ID_PDC 0x15e9
-#define PCI_DEVICE_ID_PDC_ADMA100 0x1841
-
-#define PCI_VENDOR_ID_ALTIMA 0x173b
-#define PCI_DEVICE_ID_ALTIMA_AC1000 0x03e8
-#define PCI_DEVICE_ID_ALTIMA_AC1001 0x03e9
-#define PCI_DEVICE_ID_ALTIMA_AC9100 0x03ea
-#define PCI_DEVICE_ID_ALTIMA_AC1003 0x03eb
-
-#define PCI_VENDOR_ID_SYMPHONY 0x1c1c
-#define PCI_DEVICE_ID_SYMPHONY_101 0x0001
-
-#define PCI_VENDOR_ID_TEKRAM 0x1de1
-#define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29
-
-#define PCI_VENDOR_ID_HINT 0x3388
-#define PCI_DEVICE_ID_HINT_VXPROII_IDE 0x8013
-
-#define PCI_VENDOR_ID_3DLABS 0x3d3d
-#define PCI_DEVICE_ID_3DLABS_300SX 0x0001
-#define PCI_DEVICE_ID_3DLABS_500TX 0x0002
-#define PCI_DEVICE_ID_3DLABS_DELTA 0x0003
-#define PCI_DEVICE_ID_3DLABS_PERMEDIA 0x0004
-#define PCI_DEVICE_ID_3DLABS_MX 0x0006
-#define PCI_DEVICE_ID_3DLABS_PERMEDIA2 0x0007
-#define PCI_DEVICE_ID_3DLABS_GAMMA 0x0008
-#define PCI_DEVICE_ID_3DLABS_PERMEDIA2V 0x0009
-
-#define PCI_VENDOR_ID_AVANCE 0x4005
-#define PCI_DEVICE_ID_AVANCE_ALG2064 0x2064
-#define PCI_DEVICE_ID_AVANCE_2302 0x2302
-
-#define PCI_VENDOR_ID_AKS 0x416c
-#define PCI_DEVICE_ID_AKS_ALADDINCARD 0x0100
-#define PCI_DEVICE_ID_AKS_CPC 0x0200
-
-#define PCI_VENDOR_ID_REDCREEK 0x4916
-#define PCI_DEVICE_ID_RC45 0x1960
-
-#define PCI_VENDOR_ID_NETVIN 0x4a14
-#define PCI_DEVICE_ID_NETVIN_NV5000SC 0x5000
-
-#define PCI_VENDOR_ID_S3 0x5333
-#define PCI_DEVICE_ID_S3_PLATO_PXS 0x0551
-#define PCI_DEVICE_ID_S3_ViRGE 0x5631
-#define PCI_DEVICE_ID_S3_TRIO 0x8811
-#define PCI_DEVICE_ID_S3_AURORA64VP 0x8812
-#define PCI_DEVICE_ID_S3_TRIO64UVP 0x8814
-#define PCI_DEVICE_ID_S3_ViRGE_VX 0x883d
-#define PCI_DEVICE_ID_S3_868 0x8880
-#define PCI_DEVICE_ID_S3_928 0x88b0
-#define PCI_DEVICE_ID_S3_864_1 0x88c0
-#define PCI_DEVICE_ID_S3_864_2 0x88c1
-#define PCI_DEVICE_ID_S3_964_1 0x88d0
-#define PCI_DEVICE_ID_S3_964_2 0x88d1
-#define PCI_DEVICE_ID_S3_968 0x88f0
-#define PCI_DEVICE_ID_S3_TRIO64V2 0x8901
-#define PCI_DEVICE_ID_S3_PLATO_PXG 0x8902
-#define PCI_DEVICE_ID_S3_ViRGE_DXGX 0x8a01
-#define PCI_DEVICE_ID_S3_ViRGE_GX2 0x8a10
-#define PCI_DEVICE_ID_S3_ViRGE_MX 0x8c01
-#define PCI_DEVICE_ID_S3_ViRGE_MXP 0x8c02
-#define PCI_DEVICE_ID_S3_ViRGE_MXPMV 0x8c03
-#define PCI_DEVICE_ID_S3_SONICVIBES 0xca00
-
-#define PCI_VENDOR_ID_DUNORD 0x5544
-#define PCI_DEVICE_ID_DUNORD_I3000 0x0001
-#define PCI_VENDOR_ID_GENROCO 0x5555
-#define PCI_DEVICE_ID_GENROCO_HFP832 0x0003
-
-#define PCI_VENDOR_ID_DCI 0x6666
-#define PCI_DEVICE_ID_DCI_PCCOM4 0x0001
-#define PCI_DEVICE_ID_DCI_PCCOM8 0x0002
-
-#define PCI_VENDOR_ID_INTEL 0x8086
-#define PCI_DEVICE_ID_INTEL_21145 0x0039
-#define PCI_DEVICE_ID_INTEL_21152BB 0xb152
-#define PCI_DEVICE_ID_INTEL_82375 0x0482
-#define PCI_DEVICE_ID_INTEL_82424 0x0483
-#define PCI_DEVICE_ID_INTEL_82378 0x0484
-#define PCI_DEVICE_ID_INTEL_82430 0x0486
-#define PCI_DEVICE_ID_INTEL_82434 0x04a3
-#define PCI_DEVICE_ID_INTEL_I960 0x0960
-#define PCI_DEVICE_ID_INTEL_I960RM 0x0962
-#define PCI_DEVICE_ID_INTEL_82542 0x1000
-#define PCI_DEVICE_ID_INTEL_82543GC_FIBER 0x1001
-#define PCI_DEVICE_ID_INTEL_82543GC_COPPER 0x1004
-#define PCI_DEVICE_ID_INTEL_82544EI_COPPER 0x1008
-#define PCI_DEVICE_ID_INTEL_82544EI_FIBER 0x1009
-#define PCI_DEVICE_ID_INTEL_82544GC_COPPER 0x100C
-#define PCI_DEVICE_ID_INTEL_82544GC_LOM 0x100D
-#define PCI_DEVICE_ID_INTEL_82540EM 0x100E
-#define PCI_DEVICE_ID_INTEL_82545EM_COPPER 0x100F
-#define PCI_DEVICE_ID_INTEL_82546EB_COPPER 0x1010
-#define PCI_DEVICE_ID_INTEL_82545EM_FIBER 0x1011
-#define PCI_DEVICE_ID_INTEL_82546EB_FIBER 0x1012
-#define PCI_DEVICE_ID_INTEL_82540EM_LOM 0x1015
-#define PCI_DEVICE_ID_INTEL_82559 0x1030
-
-#define PCI_DEVICE_ID_INTEL_82562ET 0x1031
-
-#define PCI_DEVICE_ID_INTEL_82815_MC 0x1130
-
-#define PCI_DEVICE_ID_INTEL_82559ER 0x1209
-#define PCI_DEVICE_ID_INTEL_82092AA_0 0x1221
-#define PCI_DEVICE_ID_INTEL_82092AA_1 0x1222
-#define PCI_DEVICE_ID_INTEL_7116 0x1223
-#define PCI_DEVICE_ID_INTEL_7205_0 0x255d
-#define PCI_DEVICE_ID_INTEL_82596 0x1226
-#define PCI_DEVICE_ID_INTEL_82865 0x1227
-#define PCI_DEVICE_ID_INTEL_82557 0x1229
-#define PCI_DEVICE_ID_INTEL_82437 0x122d
-#define PCI_DEVICE_ID_INTEL_82371FB_0 0x122e
-#define PCI_DEVICE_ID_INTEL_82371FB_1 0x1230
-#define PCI_DEVICE_ID_INTEL_82371MX 0x1234
-#define PCI_DEVICE_ID_INTEL_82437MX 0x1235
-#define PCI_DEVICE_ID_INTEL_82441 0x1237
-#define PCI_DEVICE_ID_INTEL_82380FB 0x124b
-#define PCI_DEVICE_ID_INTEL_82439 0x1250
-#define PCI_DEVICE_ID_INTEL_80960_RP 0x1960
-#define PCI_DEVICE_ID_INTEL_82845_HB 0x1a30
-#define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000
-#define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010
-#define PCI_DEVICE_ID_INTEL_82371SB_2 0x7020
-#define PCI_DEVICE_ID_INTEL_82437VX 0x7030
-#define PCI_DEVICE_ID_INTEL_82439TX 0x7100
-#define PCI_DEVICE_ID_INTEL_82371AB_0 0x7110
-#define PCI_DEVICE_ID_INTEL_82371AB 0x7111
-#define PCI_DEVICE_ID_INTEL_82371AB_2 0x7112
-#define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113
-#define PCI_DEVICE_ID_INTEL_82801AA_0 0x2410
-#define PCI_DEVICE_ID_INTEL_82801AA_1 0x2411
-#define PCI_DEVICE_ID_INTEL_82801AA_2 0x2412
-#define PCI_DEVICE_ID_INTEL_82801AA_3 0x2413
-#define PCI_DEVICE_ID_INTEL_82801AA_5 0x2415
-#define PCI_DEVICE_ID_INTEL_82801AA_6 0x2416
-#define PCI_DEVICE_ID_INTEL_82801AA_8 0x2418
-#define PCI_DEVICE_ID_INTEL_82801AB_0 0x2420
-#define PCI_DEVICE_ID_INTEL_82801AB_1 0x2421
-#define PCI_DEVICE_ID_INTEL_82801AB_2 0x2422
-#define PCI_DEVICE_ID_INTEL_82801AB_3 0x2423
-#define PCI_DEVICE_ID_INTEL_82801AB_5 0x2425
-#define PCI_DEVICE_ID_INTEL_82801AB_6 0x2426
-#define PCI_DEVICE_ID_INTEL_82801AB_8 0x2428
-#define PCI_DEVICE_ID_INTEL_82801BA_0 0x2440
-#define PCI_DEVICE_ID_INTEL_82801BA_1 0x2442
-#define PCI_DEVICE_ID_INTEL_82801BA_2 0x2443
-#define PCI_DEVICE_ID_INTEL_82801BA_3 0x2444
-#define PCI_DEVICE_ID_INTEL_82801BA_4 0x2445
-#define PCI_DEVICE_ID_INTEL_82801BA_5 0x2446
-#define PCI_DEVICE_ID_INTEL_82801BA_6 0x2448
-#define PCI_DEVICE_ID_INTEL_82801BA_7 0x2449
-#define PCI_DEVICE_ID_INTEL_82801BA_8 0x244a
-#define PCI_DEVICE_ID_INTEL_82801BA_9 0x244b
-#define PCI_DEVICE_ID_INTEL_82801BA_10 0x244c
-#define PCI_DEVICE_ID_INTEL_82801BA_11 0x244e
-#define PCI_DEVICE_ID_INTEL_82801E_0 0x2450
-#define PCI_DEVICE_ID_INTEL_82801E_2 0x2452
-#define PCI_DEVICE_ID_INTEL_82801E_3 0x2453
-#define PCI_DEVICE_ID_INTEL_82801E_9 0x2459
-#define PCI_DEVICE_ID_INTEL_82801E_11 0x245B
-#define PCI_DEVICE_ID_INTEL_82801E_14 0x245D
-#define PCI_DEVICE_ID_INTEL_82801E_15 0x245E
-#define PCI_DEVICE_ID_INTEL_82801CA_0 0x2480
-#define PCI_DEVICE_ID_INTEL_82801CA_2 0x2482
-#define PCI_DEVICE_ID_INTEL_82801CA_3 0x2483
-#define PCI_DEVICE_ID_INTEL_82801CA_4 0x2484
-#define PCI_DEVICE_ID_INTEL_82801CA_5 0x2485
-#define PCI_DEVICE_ID_INTEL_82801CA_6 0x2486
-#define PCI_DEVICE_ID_INTEL_82801CA_7 0x2487
-#define PCI_DEVICE_ID_INTEL_82801CA_10 0x248a
-#define PCI_DEVICE_ID_INTEL_82801CA_11 0x248b
-#define PCI_DEVICE_ID_INTEL_82801CA_12 0x248c
-#define PCI_DEVICE_ID_INTEL_82801DB_0 0x24c0
-#define PCI_DEVICE_ID_INTEL_82801DB_2 0x24c2
-#define PCI_DEVICE_ID_INTEL_82801DB_3 0x24c3
-#define PCI_DEVICE_ID_INTEL_82801DB_4 0x24c4
-#define PCI_DEVICE_ID_INTEL_82801DB_5 0x24c5
-#define PCI_DEVICE_ID_INTEL_82801DB_6 0x24c6
-#define PCI_DEVICE_ID_INTEL_82801DB_7 0x24c7
-#define PCI_DEVICE_ID_INTEL_82801DB_10 0x24ca
-#define PCI_DEVICE_ID_INTEL_82801DB_11 0x24cb
-#define PCI_DEVICE_ID_INTEL_82801DB_12 0x24cc
-#define PCI_DEVICE_ID_INTEL_82801DB_13 0x24cd
-#define PCI_DEVICE_ID_INTEL_82801EB_0 0x24d0
-#define PCI_DEVICE_ID_INTEL_82801EB_1 0x24d1
-#define PCI_DEVICE_ID_INTEL_82801EB_2 0x24d2
-#define PCI_DEVICE_ID_INTEL_82801EB_3 0x24d3
-#define PCI_DEVICE_ID_INTEL_82801EB_4 0x24d4
-#define PCI_DEVICE_ID_INTEL_82801EB_5 0x24d5
-#define PCI_DEVICE_ID_INTEL_82801EB_6 0x24d6
-#define PCI_DEVICE_ID_INTEL_82801EB_7 0x24d7
-#define PCI_DEVICE_ID_INTEL_82801DB_10 0x24ca
-#define PCI_DEVICE_ID_INTEL_82801EB_11 0x24db
-#define PCI_DEVICE_ID_INTEL_82801EB_13 0x24dd
-#define PCI_DEVICE_ID_INTEL_ESB_0 0x25a0
-#define PCI_DEVICE_ID_INTEL_ESB_1 0x25a1
-#define PCI_DEVICE_ID_INTEL_ESB_2 0x25a2
-#define PCI_DEVICE_ID_INTEL_ESB_3 0x25a3
-#define PCI_DEVICE_ID_INTEL_ESB_31 0x25b0
-#define PCI_DEVICE_ID_INTEL_ESB_4 0x25a4
-#define PCI_DEVICE_ID_INTEL_ESB_5 0x25a6
-#define PCI_DEVICE_ID_INTEL_ESB_6 0x25a7
-#define PCI_DEVICE_ID_INTEL_ESB_7 0x25a9
-#define PCI_DEVICE_ID_INTEL_ESB_8 0x25aa
-#define PCI_DEVICE_ID_INTEL_ESB_9 0x25ab
-#define PCI_DEVICE_ID_INTEL_ESB_11 0x25ac
-#define PCI_DEVICE_ID_INTEL_ESB_12 0x25ad
-#define PCI_DEVICE_ID_INTEL_ESB_13 0x25ae
-#define PCI_DEVICE_ID_INTEL_ICH6_0 0x2640
-#define PCI_DEVICE_ID_INTEL_ICH6_1 0x2641
-#define PCI_DEVICE_ID_INTEL_ICH6_2 0x266f
-#define PCI_DEVICE_ID_INTEL_ICH6_3 0x266e
-#define PCI_DEVICE_ID_INTEL_82850_HB 0x2530
-#define PCI_DEVICE_ID_INTEL_82845G_HB 0x2560
-#define PCI_DEVICE_ID_INTEL_80310 0x530d
-#define PCI_DEVICE_ID_INTEL_82810_MC1 0x7120
-#define PCI_DEVICE_ID_INTEL_82810_IG1 0x7121
-#define PCI_DEVICE_ID_INTEL_82810_MC3 0x7122
-#define PCI_DEVICE_ID_INTEL_82810_IG3 0x7123
-#define PCI_DEVICE_ID_INTEL_82443LX_0 0x7180
-#define PCI_DEVICE_ID_INTEL_82443LX_1 0x7181
-#define PCI_DEVICE_ID_INTEL_82443BX_0 0x7190
-#define PCI_DEVICE_ID_INTEL_82443BX_1 0x7191
-#define PCI_DEVICE_ID_INTEL_82443BX_2 0x7192
-#define PCI_DEVICE_ID_INTEL_82443MX_0 0x7198
-#define PCI_DEVICE_ID_INTEL_82443MX_1 0x7199
-#define PCI_DEVICE_ID_INTEL_82443MX_2 0x719a
-#define PCI_DEVICE_ID_INTEL_82443MX_3 0x719b
-#define PCI_DEVICE_ID_INTEL_82443GX_0 0x71a0
-#define PCI_DEVICE_ID_INTEL_82443GX_1 0x71a1
-#define PCI_DEVICE_ID_INTEL_82443GX_2 0x71a2
-#define PCI_DEVICE_ID_INTEL_82372FB_0 0x7600
-#define PCI_DEVICE_ID_INTEL_82372FB_1 0x7601
-#define PCI_DEVICE_ID_INTEL_82372FB_2 0x7602
-#define PCI_DEVICE_ID_INTEL_82372FB_3 0x7603
-#define PCI_DEVICE_ID_INTEL_82454GX 0x84c4
-#define PCI_DEVICE_ID_INTEL_82450GX 0x84c5
-#define PCI_DEVICE_ID_INTEL_82451NX 0x84ca
-#define PCI_DEVICE_ID_INTEL_82454NX 0x84cb
-
-#define PCI_VENDOR_ID_COMPUTONE 0x8e0e
-#define PCI_DEVICE_ID_COMPUTONE_IP2EX 0x0291
-#define PCI_DEVICE_ID_COMPUTONE_PG 0x0302
-#define PCI_SUBVENDOR_ID_COMPUTONE 0x8e0e
-#define PCI_SUBDEVICE_ID_COMPUTONE_PG4 0x0001
-#define PCI_SUBDEVICE_ID_COMPUTONE_PG8 0x0002
-#define PCI_SUBDEVICE_ID_COMPUTONE_PG6 0x0003
-
-#define PCI_VENDOR_ID_KTI 0x8e2e
-#define PCI_DEVICE_ID_KTI_ET32P2 0x3000
-
-#define PCI_VENDOR_ID_ADAPTEC 0x9004
-#define PCI_DEVICE_ID_ADAPTEC_7810 0x1078
-#define PCI_DEVICE_ID_ADAPTEC_7821 0x2178
-#define PCI_DEVICE_ID_ADAPTEC_38602 0x3860
-#define PCI_DEVICE_ID_ADAPTEC_7850 0x5078
-#define PCI_DEVICE_ID_ADAPTEC_7855 0x5578
-#define PCI_DEVICE_ID_ADAPTEC_5800 0x5800
-#define PCI_DEVICE_ID_ADAPTEC_3860 0x6038
-#define PCI_DEVICE_ID_ADAPTEC_1480A 0x6075
-#define PCI_DEVICE_ID_ADAPTEC_7860 0x6078
-#define PCI_DEVICE_ID_ADAPTEC_7861 0x6178
-#define PCI_DEVICE_ID_ADAPTEC_7870 0x7078
-#define PCI_DEVICE_ID_ADAPTEC_7871 0x7178
-#define PCI_DEVICE_ID_ADAPTEC_7872 0x7278
-#define PCI_DEVICE_ID_ADAPTEC_7873 0x7378
-#define PCI_DEVICE_ID_ADAPTEC_7874 0x7478
-#define PCI_DEVICE_ID_ADAPTEC_7895 0x7895
-#define PCI_DEVICE_ID_ADAPTEC_7880 0x8078
-#define PCI_DEVICE_ID_ADAPTEC_7881 0x8178
-#define PCI_DEVICE_ID_ADAPTEC_7882 0x8278
-#define PCI_DEVICE_ID_ADAPTEC_7883 0x8378
-#define PCI_DEVICE_ID_ADAPTEC_7884 0x8478
-#define PCI_DEVICE_ID_ADAPTEC_7885 0x8578
-#define PCI_DEVICE_ID_ADAPTEC_7886 0x8678
-#define PCI_DEVICE_ID_ADAPTEC_7887 0x8778
-#define PCI_DEVICE_ID_ADAPTEC_7888 0x8878
-#define PCI_DEVICE_ID_ADAPTEC_1030 0x8b78
-
-#define PCI_VENDOR_ID_ADAPTEC2 0x9005
-#define PCI_DEVICE_ID_ADAPTEC2_2940U2 0x0010
-#define PCI_DEVICE_ID_ADAPTEC2_2930U2 0x0011
-#define PCI_DEVICE_ID_ADAPTEC2_7890B 0x0013
-#define PCI_DEVICE_ID_ADAPTEC2_7890 0x001f
-#define PCI_DEVICE_ID_ADAPTEC2_3940U2 0x0050
-#define PCI_DEVICE_ID_ADAPTEC2_3950U2D 0x0051
-#define PCI_DEVICE_ID_ADAPTEC2_7896 0x005f
-#define PCI_DEVICE_ID_ADAPTEC2_7892A 0x0080
-#define PCI_DEVICE_ID_ADAPTEC2_7892B 0x0081
-#define PCI_DEVICE_ID_ADAPTEC2_7892D 0x0083
-#define PCI_DEVICE_ID_ADAPTEC2_7892P 0x008f
-#define PCI_DEVICE_ID_ADAPTEC2_7899A 0x00c0
-#define PCI_DEVICE_ID_ADAPTEC2_7899B 0x00c1
-#define PCI_DEVICE_ID_ADAPTEC2_7899D 0x00c3
-#define PCI_DEVICE_ID_ADAPTEC2_7899P 0x00cf
-
-#define PCI_VENDOR_ID_ATRONICS 0x907f
-#define PCI_DEVICE_ID_ATRONICS_2015 0x2015
-
-#define PCI_VENDOR_ID_HOLTEK 0x9412
-#define PCI_DEVICE_ID_HOLTEK_6565 0x6565
-
-#define PCI_VENDOR_ID_NETMOS 0x9710
-#define PCI_DEVICE_ID_NETMOS_9735 0x9735
-#define PCI_DEVICE_ID_NETMOS_9835 0x9835
-
-#define PCI_SUBVENDOR_ID_EXSYS 0xd84d
-#define PCI_SUBDEVICE_ID_EXSYS_4014 0x4014
-#define PCI_SUBDEVICE_ID_EXSYS_4055 0x4055
-
-#define PCI_VENDOR_ID_TIGERJET 0xe159
-#define PCI_DEVICE_ID_TIGERJET_300 0x0001
-#define PCI_DEVICE_ID_TIGERJET_100 0x0002
-
-#define PCI_VENDOR_ID_ARK 0xedd8
-#define PCI_DEVICE_ID_ARK_STING 0xa091
-#define PCI_DEVICE_ID_ARK_STINGARK 0xa099
-#define PCI_DEVICE_ID_ARK_2000MT 0xa0a1
-
-#define PCI_VENDOR_ID_MICROGATE 0x13c0
-#define PCI_DEVICE_ID_MICROGATE_USC 0x0010
-#define PCI_DEVICE_ID_MICROGATE_SCC 0x0020
-#define PCI_DEVICE_ID_MICROGATE_SCA 0x0030
diff --git a/include/post.h b/include/post.h
deleted file mode 100644
index cdefbddb6f..0000000000
--- a/include/post.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _POST_H
-#define _POST_H
-
-#ifndef __ASSEMBLY__
-#include <common.h>
-#endif
-
-#ifdef CONFIG_POST
-
-#define POST_POWERON 0x01 /* test runs on power-on booting */
-#define POST_NORMAL 0x02 /* test runs on normal booting */
-#define POST_SLOWTEST 0x04 /* test is slow, enabled by key press */
-#define POST_POWERTEST 0x08 /* test runs after watchdog reset */
-
-#define POST_COLDBOOT 0x80 /* first boot after power-on */
-
-#define POST_ROM 0x0100 /* test runs in ROM */
-#define POST_RAM 0x0200 /* test runs in RAM */
-#define POST_MANUAL 0x0400 /* test runs on diag command */
-#define POST_REBOOT 0x0800 /* test may cause rebooting */
-#define POST_PREREL 0x1000 /* test runs before relocation */
-
-#define POST_MEM (POST_RAM | POST_ROM)
-#define POST_ALWAYS (POST_NORMAL | \
- POST_SLOWTEST | \
- POST_MANUAL | \
- POST_POWERON )
-
-#ifndef __ASSEMBLY__
-
-struct post_test {
- char *name;
- char *cmd;
- char *desc;
- int flags;
- int (*test) (int flags);
- int (*init_f) (void);
- void (*reloc) (void);
- unsigned long testid;
-};
-int post_init_f (void);
-void post_bootmode_init (void);
-int post_bootmode_get (unsigned int * last_test);
-void post_bootmode_clear (void);
-void post_output_backlog ( void );
-int post_run (char *name, int flags);
-int post_info (char *name);
-int post_log (char *format, ...);
-void post_reloc (void);
-unsigned long post_time_ms (unsigned long base);
-
-extern struct post_test post_list[];
-extern unsigned int post_list_size;
-extern int post_hotkeys_pressed(void);
-
-#endif /* __ASSEMBLY__ */
-
-#define CFG_POST_RTC 0x00000001
-#define CFG_POST_WATCHDOG 0x00000002
-#define CFG_POST_MEMORY 0x00000004
-#define CFG_POST_CPU 0x00000008
-#define CFG_POST_I2C 0x00000010
-#define CFG_POST_CACHE 0x00000020
-#define CFG_POST_UART 0x00000040
-#define CFG_POST_ETHER 0x00000080
-#define CFG_POST_SPI 0x00000100
-#define CFG_POST_USB 0x00000200
-#define CFG_POST_SPR 0x00000400
-#define CFG_POST_SYSMON 0x00000800
-#define CFG_POST_DSP 0x00001000
-#define CFG_POST_CODEC 0x00002000
-
-#endif /* CONFIG_POST */
-
-#endif /* _POST_H */
diff --git a/include/scsi.h b/include/scsi.h
deleted file mode 100644
index 2be4d4014a..0000000000
--- a/include/scsi.h
+++ /dev/null
@@ -1,208 +0,0 @@
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
- #ifndef _SCSI_H
- #define _SCSI_H
-
-typedef struct SCSI_cmd_block{
- unsigned char cmd[16]; /* command */
- unsigned char sense_buf[64]; /* for request sense */
- unsigned char status; /* SCSI Status */
- unsigned char target; /* Target ID */
- unsigned char lun; /* Target LUN */
- unsigned char cmdlen; /* command len */
- unsigned long datalen; /* Total data length */
- unsigned char * pdata; /* pointer to data */
- unsigned char msgout[12]; /* Messge out buffer (NOT USED) */
- unsigned char msgin[12]; /* Message in buffer */
- unsigned char sensecmdlen; /* Sense command len */
- unsigned long sensedatalen; /* Sense data len */
- unsigned char sensecmd[6]; /* Sense command */
- unsigned long contr_stat; /* Controller Status */
- unsigned long trans_bytes; /* tranfered bytes */
-
- unsigned int priv;
-}ccb;
-
-/*-----------------------------------------------------------
-**
-** SCSI constants.
-**
-**-----------------------------------------------------------
-*/
-
-/*
-** Messages
-*/
-
-#define M_COMPLETE (0x00)
-#define M_EXTENDED (0x01)
-#define M_SAVE_DP (0x02)
-#define M_RESTORE_DP (0x03)
-#define M_DISCONNECT (0x04)
-#define M_ID_ERROR (0x05)
-#define M_ABORT (0x06)
-#define M_REJECT (0x07)
-#define M_NOOP (0x08)
-#define M_PARITY (0x09)
-#define M_LCOMPLETE (0x0a)
-#define M_FCOMPLETE (0x0b)
-#define M_RESET (0x0c)
-#define M_ABORT_TAG (0x0d)
-#define M_CLEAR_QUEUE (0x0e)
-#define M_INIT_REC (0x0f)
-#define M_REL_REC (0x10)
-#define M_TERMINATE (0x11)
-#define M_SIMPLE_TAG (0x20)
-#define M_HEAD_TAG (0x21)
-#define M_ORDERED_TAG (0x22)
-#define M_IGN_RESIDUE (0x23)
-#define M_IDENTIFY (0x80)
-
-#define M_X_MODIFY_DP (0x00)
-#define M_X_SYNC_REQ (0x01)
-#define M_X_WIDE_REQ (0x03)
-#define M_X_PPR_REQ (0x04)
-
-
-/*
-** Status
-*/
-
-#define S_GOOD (0x00)
-#define S_CHECK_COND (0x02)
-#define S_COND_MET (0x04)
-#define S_BUSY (0x08)
-#define S_INT (0x10)
-#define S_INT_COND_MET (0x14)
-#define S_CONFLICT (0x18)
-#define S_TERMINATED (0x20)
-#define S_QUEUE_FULL (0x28)
-#define S_ILLEGAL (0xff)
-#define S_SENSE (0x80)
-
-/*
- * Sense_keys
- */
-
-#define SENSE_NO_SENSE 0x0
-#define SENSE_RECOVERED_ERROR 0x1
-#define SENSE_NOT_READY 0x2
-#define SENSE_MEDIUM_ERROR 0x3
-#define SENSE_HARDWARE_ERROR 0x4
-#define SENSE_ILLEGAL_REQUEST 0x5
-#define SENSE_UNIT_ATTENTION 0x6
-#define SENSE_DATA_PROTECT 0x7
-#define SENSE_BLANK_CHECK 0x8
-#define SENSE_VENDOR_SPECIFIC 0x9
-#define SENSE_COPY_ABORTED 0xA
-#define SENSE_ABORTED_COMMAND 0xB
-#define SENSE_VOLUME_OVERFLOW 0xD
-#define SENSE_MISCOMPARE 0xE
-
-
-#define SCSI_CHANGE_DEF 0x40 /* Change Definition (Optional) */
-#define SCSI_COMPARE 0x39 /* Compare (O) */
-#define SCSI_COPY 0x18 /* Copy (O) */
-#define SCSI_COP_VERIFY 0x3A /* Copy and Verify (O) */
-#define SCSI_INQUIRY 0x12 /* Inquiry (MANDATORY) */
-#define SCSI_LOG_SELECT 0x4C /* Log Select (O) */
-#define SCSI_LOG_SENSE 0x4D /* Log Sense (O) */
-#define SCSI_MODE_SEL6 0x15 /* Mode Select 6-byte (Device Specific) */
-#define SCSI_MODE_SEL10 0x55 /* Mode Select 10-byte (Device Specific) */
-#define SCSI_MODE_SEN6 0x1A /* Mode Sense 6-byte (Device Specific) */
-#define SCSI_MODE_SEN10 0x5A /* Mode Sense 10-byte (Device Specific) */
-#define SCSI_READ_BUFF 0x3C /* Read Buffer (O) */
-#define SCSI_REQ_SENSE 0x03 /* Request Sense (MANDATORY) */
-#define SCSI_SEND_DIAG 0x1D /* Send Diagnostic (O) */
-#define SCSI_TST_U_RDY 0x00 /* Test Unit Ready (MANDATORY) */
-#define SCSI_WRITE_BUFF 0x3B /* Write Buffer (O) */
-/***************************************************************************
- * %%% Commands Unique to Direct Access Devices %%%
- ***************************************************************************/
-#define SCSI_COMPARE 0x39 /* Compare (O) */
-#define SCSI_FORMAT 0x04 /* Format Unit (MANDATORY) */
-#define SCSI_LCK_UN_CAC 0x36 /* Lock Unlock Cache (O) */
-#define SCSI_PREFETCH 0x34 /* Prefetch (O) */
-#define SCSI_MED_REMOVL 0x1E /* Prevent/Allow medium Removal (O) */
-#define SCSI_READ6 0x08 /* Read 6-byte (MANDATORY) */
-#define SCSI_READ10 0x28 /* Read 10-byte (MANDATORY) */
-#define SCSI_RD_CAPAC 0x25 /* Read Capacity (MANDATORY) */
-#define SCSI_RD_DEFECT 0x37 /* Read Defect Data (O) */
-#define SCSI_READ_LONG 0x3E /* Read Long (O) */
-#define SCSI_REASS_BLK 0x07 /* Reassign Blocks (O) */
-#define SCSI_RCV_DIAG 0x1C /* Receive Diagnostic Results (O) */
-#define SCSI_RELEASE 0x17 /* Release Unit (MANDATORY) */
-#define SCSI_REZERO 0x01 /* Rezero Unit (O) */
-#define SCSI_SRCH_DAT_E 0x31 /* Search Data Equal (O) */
-#define SCSI_SRCH_DAT_H 0x30 /* Search Data High (O) */
-#define SCSI_SRCH_DAT_L 0x32 /* Search Data Low (O) */
-#define SCSI_SEEK6 0x0B /* Seek 6-Byte (O) */
-#define SCSI_SEEK10 0x2B /* Seek 10-Byte (O) */
-#define SCSI_SEND_DIAG 0x1D /* Send Diagnostics (MANDATORY) */
-#define SCSI_SET_LIMIT 0x33 /* Set Limits (O) */
-#define SCSI_START_STP 0x1B /* Start/Stop Unit (O) */
-#define SCSI_SYNC_CACHE 0x35 /* Synchronize Cache (O) */
-#define SCSI_VERIFY 0x2F /* Verify (O) */
-#define SCSI_WRITE6 0x0A /* Write 6-Byte (MANDATORY) */
-#define SCSI_WRITE10 0x2A /* Write 10-Byte (MANDATORY) */
-#define SCSI_WRT_VERIFY 0x2E /* Write and Verify (O) */
-#define SCSI_WRITE_LONG 0x3F /* Write Long (O) */
-#define SCSI_WRITE_SAME 0x41 /* Write Same (O) */
-
-
-/****************************************************************************
- * decleration of functions which have to reside in the LowLevel Part Driver
- */
-
-void scsi_print_error(ccb *pccb);
-int scsi_exec(ccb *pccb);
-void scsi_bus_reset(void);
-void scsi_low_level_init(int busdevfunc);
-
-
-/***************************************************************************
- * functions residing inside cmd_scsi.c
- */
-void scsi_init(void);
-
-
-#define SCSI_IDENTIFY 0xC0 /* not used */
-
-/* Hardware errors */
-#define SCSI_SEL_TIME_OUT 0x00000101 /* Selection time out */
-#define SCSI_HNS_TIME_OUT 0x00000102 /* Handshake */
-#define SCSI_MA_TIME_OUT 0x00000103 /* Phase error */
-#define SCSI_UNEXP_DIS 0x00000104 /* unexpected disconnect */
-
-#define SCSI_INT_STATE 0x00010000 /* unknown Interrupt number is stored in 16 LSB */
-
-
-#ifndef TRUE
-#define TRUE 1
-#endif
-#ifndef FALSE
-#define FALSE 0
-#endif
-
-#endif /* _SCSI_H */
diff --git a/include/status_led.h b/include/status_led.h
deleted file mode 100644
index db4c60fe3f..0000000000
--- a/include/status_led.h
+++ /dev/null
@@ -1,369 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * The purpose of this code is to signal the operational status of a
- * target which usually boots over the network; while running in
- * PCBoot, a status LED is blinking. As soon as a valid BOOTP reply
- * message has been received, the LED is turned off. The Linux
- * kernel, once it is running, will start blinking the LED again,
- * with another frequency.
- */
-
-#ifndef _STATUS_LED_H_
-#define _STATUS_LED_H_
-
-#ifdef CONFIG_STATUS_LED
-
-#define STATUS_LED_OFF 0
-#define STATUS_LED_BLINKING 1
-#define STATUS_LED_ON 2
-
-void status_led_tick (unsigned long timestamp);
-void status_led_set (int led, int state);
-
-/***** TQM8xxL ********************************************************/
-#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_HMI10)
-# define STATUS_LED_PAR im_cpm.cp_pbpar
-# define STATUS_LED_DIR im_cpm.cp_pbdir
-# define STATUS_LED_ODR im_cpm.cp_pbodr
-# define STATUS_LED_DAT im_cpm.cp_pbdat
-
-# define STATUS_LED_BIT 0x00000001
-# define STATUS_LED_PERIOD (CFG_HZ / 2)
-# define STATUS_LED_STATE STATUS_LED_BLINKING
-
-# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
-
-# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
-
-/***** MVS v1 **********************************************************/
-#elif (defined(CONFIG_MVS) && CONFIG_MVS < 2)
-# define STATUS_LED_PAR im_ioport.iop_pdpar
-# define STATUS_LED_DIR im_ioport.iop_pddir
-# undef STATUS_LED_ODR
-# define STATUS_LED_DAT im_ioport.iop_pddat
-
-# define STATUS_LED_BIT 0x00000001
-# define STATUS_LED_PERIOD (CFG_HZ / 2)
-# define STATUS_LED_STATE STATUS_LED_BLINKING
-
-# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
-
-# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
-
-/***** ETX_094 ********************************************************/
-#elif defined(CONFIG_ETX094)
-
-# define STATUS_LED_PAR im_ioport.iop_pdpar
-# define STATUS_LED_DIR im_ioport.iop_pddir
-# undef STATUS_LED_ODR
-# define STATUS_LED_DAT im_ioport.iop_pddat
-
-# define STATUS_LED_BIT 0x00000001
-# define STATUS_LED_PERIOD (CFG_HZ / 2)
-# define STATUS_LED_STATE STATUS_LED_BLINKING
-
-# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
-
-# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
-
-/***** GEN860T *********************************************************/
-#elif defined(CONFIG_GEN860T)
-
-# define STATUS_LED_PAR im_ioport.iop_papar
-# define STATUS_LED_DIR im_ioport.iop_padir
-# define STATUS_LED_ODR im_ioport.iop_paodr
-# define STATUS_LED_DAT im_ioport.iop_padat
-
-# define STATUS_LED_BIT 0x0800 /* Red LED 0 is on PA.4 */
-# define STATUS_LED_PERIOD (CFG_HZ / 4)
-# define STATUS_LED_STATE STATUS_LED_OFF
-# define STATUS_LED_BIT1 0x0400 /* Grn LED 1 is on PA.5 */
-# define STATUS_LED_PERIOD1 (CFG_HZ / 8)
-# define STATUS_LED_STATE1 STATUS_LED_BLINKING
-# define STATUS_LED_BIT2 0x0080 /* Red LED 2 is on PA.8 */
-# define STATUS_LED_PERIOD2 (CFG_HZ / 4)
-# define STATUS_LED_STATE2 STATUS_LED_OFF
-# define STATUS_LED_BIT3 0x0040 /* Grn LED 3 is on PA.9 */
-# define STATUS_LED_PERIOD3 (CFG_HZ / 4)
-# define STATUS_LED_STATE3 STATUS_LED_OFF
-
-# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
-# define STATUS_LED_BOOT 1 /* Boot status on LED 1 */
-
-/***** IVMS8 **********************************************************/
-#elif defined(CONFIG_IVMS8)
-
-# define STATUS_LED_PAR im_cpm.cp_pbpar
-# define STATUS_LED_DIR im_cpm.cp_pbdir
-# define STATUS_LED_ODR im_cpm.cp_pbodr
-# define STATUS_LED_DAT im_cpm.cp_pbdat
-
-# define STATUS_LED_BIT 0x00000010 /* LED 0 is on PB.27 */
-# define STATUS_LED_PERIOD (1 * CFG_HZ)
-# define STATUS_LED_STATE STATUS_LED_OFF
-# define STATUS_LED_BIT1 0x00000020 /* LED 1 is on PB.26 */
-# define STATUS_LED_PERIOD1 (1 * CFG_HZ)
-# define STATUS_LED_STATE1 STATUS_LED_OFF
-/* IDE LED usable for other purposes, too */
-# define STATUS_LED_BIT2 0x00000008 /* LED 2 is on PB.28 */
-# define STATUS_LED_PERIOD2 (1 * CFG_HZ)
-# define STATUS_LED_STATE2 STATUS_LED_OFF
-
-# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
-
-# define STATUS_ILOCK_SWITCH 0x00800000 /* ILOCK switch in IRQ4 */
-
-# define STATUS_ILOCK_PERIOD (CFG_HZ / 10) /* about every 100 ms */
-
-# define STATUS_LED_YELLOW 0
-# define STATUS_LED_GREEN 1
-# define STATUS_LED_BOOT 2 /* IDE LED used for boot status */
-
-/***** IVML24 *********************************************************/
-#elif defined(CONFIG_IVML24)
-
-# define STATUS_LED_PAR im_cpm.cp_pbpar
-# define STATUS_LED_DIR im_cpm.cp_pbdir
-# define STATUS_LED_ODR im_cpm.cp_pbodr
-# define STATUS_LED_DAT im_cpm.cp_pbdat
-
-# define STATUS_LED_BIT 0x00000010 /* LED 0 is on PB.27 */
-# define STATUS_LED_PERIOD (1 * CFG_HZ)
-# define STATUS_LED_STATE STATUS_LED_OFF
-# define STATUS_LED_BIT1 0x00000020 /* LED 1 is on PB.26 */
-# define STATUS_LED_PERIOD1 (1 * CFG_HZ)
-# define STATUS_LED_STATE1 STATUS_LED_OFF
-/* IDE LED usable for other purposes, too */
-# define STATUS_LED_BIT2 0x00000008 /* LED 2 is on PB.28 */
-# define STATUS_LED_PERIOD2 (1 * CFG_HZ)
-# define STATUS_LED_STATE2 STATUS_LED_OFF
-
-# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
-
-# define STATUS_ILOCK_SWITCH 0x00004000 /* ILOCK is on PB.17 */
-
-# define STATUS_ILOCK_PERIOD (CFG_HZ / 10) /* about every 100 ms */
-
-# define STATUS_LED_YELLOW 0
-# define STATUS_LED_GREEN 1
-# define STATUS_LED_BOOT 2 /* IDE LED used for boot status */
-
-/***** LANTEC *********************************************************/
-#elif defined(CONFIG_LANTEC)
-
-# define STATUS_LED_PAR im_ioport.iop_pdpar
-# define STATUS_LED_DIR im_ioport.iop_pddir
-# undef STATUS_LED_ODR
-# define STATUS_LED_DAT im_ioport.iop_pddat
-
-# if CONFIG_LATEC < 2
-# define STATUS_LED_BIT 0x1000
-# else
-# define STATUS_LED_BIT 0x0800
-# endif
-# define STATUS_LED_PERIOD (CFG_HZ / 2)
-# define STATUS_LED_STATE STATUS_LED_BLINKING
-
-# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
-
-# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
-
-/***** PCU E and CCM ************************************************/
-#elif (defined(CONFIG_PCU_E) || defined(CONFIG_CCM))
-
-# define STATUS_LED_PAR im_cpm.cp_pbpar
-# define STATUS_LED_DIR im_cpm.cp_pbdir
-# define STATUS_LED_ODR im_cpm.cp_pbodr
-# define STATUS_LED_DAT im_cpm.cp_pbdat
-
-# define STATUS_LED_BIT 0x00010000 /* green LED is on PB.15 */
-# define STATUS_LED_PERIOD (CFG_HZ / 2)
-# define STATUS_LED_STATE STATUS_LED_BLINKING
-
-# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
-
-# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
-
-/***** ICU862 ********************************************************/
-#elif defined(CONFIG_ICU862)
-
-# define STATUS_LED_PAR im_ioport.iop_papar
-# define STATUS_LED_DIR im_ioport.iop_padir
-# define STATUS_LED_ODR im_ioport.iop_paodr
-# define STATUS_LED_DAT im_ioport.iop_padat
-
-# define STATUS_LED_BIT 0x4000 /* LED 0 is on PA.1 */
-# define STATUS_LED_PERIOD (CFG_HZ / 2)
-# define STATUS_LED_STATE STATUS_LED_BLINKING
-# define STATUS_LED_BIT1 0x1000 /* LED 1 is on PA.3 */
-# define STATUS_LED_PERIOD1 (CFG_HZ)
-# define STATUS_LED_STATE1 STATUS_LED_OFF
-
-# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
-
-# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
-
-/***** Someone else defines these *************************************/
-#elif defined(STATUS_LED_PAR)
-
- /*
- * ADVICE: Define in your board configuration file rather than
- * filling this file up with lots of custom board stuff.
- */
-
-/***** NetVia ********************************************************/
-#elif defined(CONFIG_NETVIA)
-
-#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
-
-#define STATUS_LED_PAR im_ioport.iop_pdpar
-#define STATUS_LED_DIR im_ioport.iop_pddir
-#undef STATUS_LED_ODR
-#define STATUS_LED_DAT im_ioport.iop_pddat
-
-# define STATUS_LED_BIT 0x0080 /* PD.8 */
-# define STATUS_LED_PERIOD (CFG_HZ / 2)
-# define STATUS_LED_STATE STATUS_LED_BLINKING
-
-# define STATUS_LED_BIT1 0x0040 /* PD.9 */
-# define STATUS_LED_PERIOD1 (CFG_HZ / 2)
-# define STATUS_LED_STATE1 STATUS_LED_OFF
-
-# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
-# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
-
-#endif
-
-/***** CMI ********************************************************/
-#elif defined(CONFIG_CMI)
-# define STATUS_LED_DIR im_mios.mios_mpiosm32ddr
-# define STATUS_LED_DAT im_mios.mios_mpiosm32dr
-
-# define STATUS_LED_BIT 0x2000 /* Select one of the 16 possible*/
- /* MIOS outputs */
-# define STATUS_LED_PERIOD (CFG_HZ / 2) /* Blinking periode is 500 ms */
-# define STATUS_LED_STATE STATUS_LED_BLINKING
-
-# define STATUS_LED_ACTIVE 1 /* LED on for bit == 0 */
-# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
-
-/***** KUP4K, KUP4X ****************************************************/
-#elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X) || defined(CONFIG_CCM)
-
-# define STATUS_LED_PAR im_ioport.iop_papar
-# define STATUS_LED_DIR im_ioport.iop_padir
-# define STATUS_LED_ODR im_ioport.iop_paodr
-# define STATUS_LED_DAT im_ioport.iop_padat
-
-# define STATUS_LED_BIT 0x00000300 /* green + red PA[8]=yellow, PA[7]=red, PA[6]=green */
-# define STATUS_LED_PERIOD (CFG_HZ / 2)
-# define STATUS_LED_STATE STATUS_LED_BLINKING
-
-# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
-
-# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
-
-#elif defined(CONFIG_SVM_SC8xx)
-# define STATUS_LED_PAR im_cpm.cp_pbpar
-# define STATUS_LED_DIR im_cpm.cp_pbdir
-# define STATUS_LED_ODR im_cpm.cp_pbodr
-# define STATUS_LED_DAT im_cpm.cp_pbdat
-
-# define STATUS_LED_BIT 0x00000001
-# define STATUS_LED_PERIOD (CFG_HZ / 2)
-# define STATUS_LED_STATE STATUS_LED_BLINKING
-
-# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
-
-# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
-
-/***** RBC823 ********************************************************/
-#elif defined(CONFIG_RBC823)
-
-# define STATUS_LED_PAR im_ioport.iop_pcpar
-# define STATUS_LED_DIR im_ioport.iop_pcdir
-# undef STATUS_LED_ODR
-# define STATUS_LED_DAT im_ioport.iop_pcdat
-
-# define STATUS_LED_BIT 0x0002 /* LED 0 is on PC.14 */
-# define STATUS_LED_PERIOD (CFG_HZ / 2)
-# define STATUS_LED_STATE STATUS_LED_BLINKING
-# define STATUS_LED_BIT1 0x0004 /* LED 1 is on PC.13 */
-# define STATUS_LED_PERIOD1 (CFG_HZ)
-# define STATUS_LED_STATE1 STATUS_LED_OFF
-
-# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
-
-# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
-
-/***** HMI10 **********************************************************/
-#elif defined(CONFIG_HMI10)
-# define STATUS_LED_PAR im_ioport.iop_papar
-# define STATUS_LED_DIR im_ioport.iop_padir
-# define STATUS_LED_ODR im_ioport.iop_paodr
-# define STATUS_LED_DAT im_ioport.iop_padat
-
-# define STATUS_LED_BIT 0x00000001 /* LED is on PA15 */
-# define STATUS_LED_PERIOD (CFG_HZ / 2)
-# define STATUS_LED_STATE STATUS_LED_BLINKING
-
-# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
-
-# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
-
-/***** NetPhone ********************************************************/
-#elif defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2)
-/* XXX empty just to avoid the error */
-/***** STx XTc ********************************************************/
-#elif defined(CONFIG_STXXTC)
-/* XXX empty just to avoid the error */
-/***** sbc8240 ********************************************************/
-#elif defined(CONFIG_WRSBC8240)
-/* XXX empty just to avoid the error */
-/************************************************************************/
-#elif defined(CONFIG_NIOS2)
-/* XXX empty just to avoid the error */
-/************************************************************************/
-#elif defined(CONFIG_V38B)
-
-# define STATUS_LED_BIT 0x0010 /* Timer7 GPIO */
-# define STATUS_LED_PERIOD (CFG_HZ / 2)
-# define STATUS_LED_STATE STATUS_LED_BLINKING
-
-# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
-# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
-
-#else
-# error Status LED configuration missing
-#endif
-/************************************************************************/
-
-#ifndef CONFIG_BOARD_SPECIFIC_LED
-# include <asm/status_led.h>
-#endif
-
-#endif /* CONFIG_STATUS_LED */
-
-#endif /* _STATUS_LED_H_ */
diff --git a/include/systemace.h b/include/systemace.h
deleted file mode 100644
index be43d468d2..0000000000
--- a/include/systemace.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef __SYSTEMACE_H
-#define __SYSTEMACE_H
-/*
- * Copyright (c) 2004 Picture Elements, Inc.
- * Stephen Williams (steve@picturel.com)
- *
- * This source code is free software; you can redistribute it
- * and/or modify it in source code form under the terms of the GNU
- * General Public License as published by the Free Software
- * Foundation; either version 2 of the License, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
- */
-#ident "$Id:$"
-
-#ifdef CONFIG_SYSTEMACE
-
-# include <part.h>
-
-block_dev_desc_t * systemace_get_dev(int dev);
-
-#endif /* CONFIG_SYSTEMACE */
-#endif /* __SYSTEMACE_H */
diff --git a/include/universe.h b/include/universe.h
deleted file mode 100644
index 2892d31b4b..0000000000
--- a/include/universe.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * (C) Copyright 2003 Stefan Roese, stefan.roese@esd-electronics.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _universe_h
-#define _universe_h
-
-typedef struct _UNIVERSE UNIVERSE;
-typedef struct _SLAVE_IMAGE SLAVE_IMAGE;
-typedef struct _TDMA_CMD_PACKET TDMA_CMD_PACKET;
-
-struct _SLAVE_IMAGE {
- unsigned int ctl; /* Control */
- unsigned int bs; /* Base */
- unsigned int bd; /* Bound */
- unsigned int to; /* Translation */
- unsigned int reserved;
-};
-
-struct _UNIVERSE {
- unsigned int pci_id;
- unsigned int pci_csr;
- unsigned int pci_class;
- unsigned int pci_misc0;
- unsigned int pci_bs;
- unsigned int spare0[10];
- unsigned int pci_misc1;
- unsigned int spare1[48];
- SLAVE_IMAGE lsi[4];
- unsigned int spare2[8];
- unsigned int scyc_ctl;
- unsigned int scyc_addr;
- unsigned int scyc_en;
- unsigned int scyc_cmp;
- unsigned int scyc_swp;
- unsigned int lmisc;
- unsigned int slsi;
- unsigned int l_cmderr;
- unsigned int laerr;
- unsigned int spare3[27];
- unsigned int dctl;
- unsigned int dtbc;
- unsigned int dla;
- unsigned int spare4[1];
- unsigned int dva;
- unsigned int spare5[1];
- unsigned int dcpp;
- unsigned int spare6[1];
- unsigned int dgcs;
- unsigned int d_llue;
- unsigned int spare7[54];
- unsigned int lint_en;
- unsigned int lint_stat;
- unsigned int lint_map0;
- unsigned int lint_map1;
- unsigned int vint_en;
- unsigned int vint_stat;
- unsigned int vint_map0;
- unsigned int vint_map1;
- unsigned int statid;
- unsigned int vx_statid[7];
- unsigned int spare8[48];
- unsigned int mast_ctl;
- unsigned int misc_ctl;
- unsigned int misc_stat;
- unsigned int user_am;
- unsigned int spare9[700];
- SLAVE_IMAGE vsi[4];
- unsigned int spare10[8];
- unsigned int vrai_ctl;
- unsigned int vrai_bs;
- unsigned int spare11[2];
- unsigned int vcsr_ctl;
- unsigned int vcsr_to;
- unsigned int v_amerr;
- unsigned int vaerr;
- unsigned int spare12[25];
- unsigned int vcsr_clr;
- unsigned int vcsr_set;
- unsigned int vcsr_bs;
-};
-
-#define IRQ_VOWN 0x0001
-#define IRQ_VIRQ1 0x0002
-#define IRQ_VIRQ2 0x0004
-#define IRQ_VIRQ3 0x0008
-#define IRQ_VIRQ4 0x0010
-#define IRQ_VIRQ5 0x0020
-#define IRQ_VIRQ6 0x0040
-#define IRQ_VIRQ7 0x0080
-#define IRQ_DMA 0x0100
-#define IRQ_LERR 0x0200
-#define IRQ_VERR 0x0400
-#define IRQ_res 0x0800
-#define IRQ_IACK 0x1000
-#define IRQ_SWINT 0x2000
-#define IRQ_SYSFAIL 0x4000
-#define IRQ_ACFAIL 0x8000
-
-struct _TDMA_CMD_PACKET {
- unsigned int dctl; /* DMA Control */
- unsigned int dtbc; /* Transfer Byte Count */
- unsigned int dlv; /* PCI Address */
- unsigned int res1; /* Reserved */
- unsigned int dva; /* Vme Address */
- unsigned int res2; /* Reserved */
- unsigned int dcpp; /* Pointer to Numed Cmd Packet with rPN */
- unsigned int res3; /* Reserved */
-};
-
-#define VME_AM_A16 0x01
-#define VME_AM_A24 0x02
-#define VME_AM_A32 0x03
-#define VME_AM_Axx 0x03
-#define VME_AM_SUP 0x04
-#define VME_AM_DATA 0x10
-#define VME_AM_PROG 0x20
-#define VME_AM_Mxx 0x30
-
-#define VME_FLAG_D8 0x01
-#define VME_FLAG_D16 0x02
-#define VME_FLAG_D32 0x03
-#define VME_FLAG_Dxx 0x03
-
-#define PCI_MS_MEM 0x01
-#define PCI_MS_IO 0x02
-#define PCI_MS_CONFIG 0x03
-#define PCI_MS_Mxx 0x03
-
-#endif
diff --git a/include/video.h b/include/video.h
deleted file mode 100644
index efcc682a29..0000000000
--- a/include/video.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
-** MPC823 Video Controller
-** =======================
-** (C) 2000 by Paolo Scaffardi (arsenio@tin.it)
-** AIRVENT SAM s.p.a - RIMINI(ITALY)
-**
-*/
-
-#ifndef _VIDEO_H_
-#define _VIDEO_H_
-
-/* Video functions */
-
-int video_init (void *videobase);
-void video_putc (const char c);
-void video_puts (const char *s);
-void video_printf (const char *fmt, ...);
-
-#endif
diff --git a/include/video_ad7179.h b/include/video_ad7179.h
deleted file mode 100644
index 6a1ec86024..0000000000
--- a/include/video_ad7179.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * (C) Copyright 2003 Wolfgang Grandegger <wg@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _VIDEO_AD7179_H_
-#define _VIDEO_AD7179_H_
-
-/*
- * The video encoder data are board specific now!
- */
-
-#if defined(CONFIG_RRVISION)
-#include "../board/RRvision/video_ad7179.h"
-#else
-#error "Please provide a board-specific video_ad7179.h"
-#endif
-
-#endif /* _VIDEO_AD7179_H_ */
diff --git a/include/video_easylogo.h b/include/video_easylogo.h
deleted file mode 100644
index ae56601188..0000000000
--- a/include/video_easylogo.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
-** video easylogo
-** ==============
-** (C) 2000 by Paolo Scaffardi (arsenio@tin.it)
-** AIRVENT SAM s.p.a - RIMINI(ITALY)
-**
-** This utility is still under construction!
-*/
-
-#ifndef _EASYLOGO_H_
-#define _EASYLOGO_H_
-
-
-typedef struct {
- unsigned char *data;
- int width;
- int height;
- int bpp;
- int pixel_size;
- int size;
-} fastimage_t ;
-
-#endif /* _EASYLOGO_H_ */
diff --git a/include/video_logo.h b/include/video_logo.h
deleted file mode 100644
index c12e8f84ed..0000000000
--- a/include/video_logo.h
+++ /dev/null
@@ -1,1951 +0,0 @@
-/* */
-/* Generated by EasyLogo, (C) 2000 by Paolo Scaffardi */
-/* */
-/* To use this, include it and call: easylogo_plot(screen,&u_boot_logo, width,x,y) */
-/* */
-/* Where: 'screen' is the pointer to the frame buffer */
-/* 'width' is the screen width */
-/* 'x' is the horizontal position */
-/* 'y' is the vertical position */
-/* */
-
-#include <video_easylogo.h>
-
-#define DEF_U_BOOT_LOGO_WIDTH 160
-#define DEF_U_BOOT_LOGO_HEIGHT 96
-#define DEF_U_BOOT_LOGO_PIXELS 15360
-#define DEF_U_BOOT_LOGO_BPP 16
-#define DEF_U_BOOT_LOGO_PIXEL_SIZE 2
-#define DEF_U_BOOT_LOGO_SIZE 30720
-
-unsigned char DEF_U_BOOT_LOGO_DATA[DEF_U_BOOT_LOGO_SIZE] = {
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xb6,
- 0x80, 0xb6, 0x80, 0xb6, 0x80, 0xb6, 0x80, 0xb6, 0x80, 0xb6, 0x80, 0xb6, 0x80, 0xb6, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
- 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
- 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
- 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
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- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7c, 0x4b, 0x7c, 0x69,
- 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
- 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7d, 0x80, 0x7a, 0x3f, 0x7a, 0x3f,
- 0x7a, 0x3f, 0x7c, 0x69, 0x7b, 0x60, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1
-};
-
-fastimage_t u_boot_logo = {
- DEF_U_BOOT_LOGO_DATA,
- DEF_U_BOOT_LOGO_WIDTH,
- DEF_U_BOOT_LOGO_HEIGHT,
- DEF_U_BOOT_LOGO_BPP,
- DEF_U_BOOT_LOGO_PIXEL_SIZE,
- DEF_U_BOOT_LOGO_SIZE
-};
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-27 18:24:46 +0000