Merge branch 'for-next/imx'

51 files changed, 1256 insertions, 302 deletions

diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index 30f4c299f1..b2fea4a40f 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -1,4 +1,5 @@
 # keep sorted by CONFIG_* macro name.
+obj-$(CONFIG_MACH_ADVANTECH_ROM_742X)		+= advantech-mx6/
 obj-$(CONFIG_MACH_AFI_GF)			+= afi-gf/
 obj-$(CONFIG_MACH_ANIMEO_IP)			+= animeo_ip/
 obj-$(CONFIG_MACH_ARCHOSG9)			+= archosg9/
diff --git a/arch/arm/boards/advantech-mx6/Makefile b/arch/arm/boards/advantech-mx6/Makefile
new file mode 100644
index 0000000000..01c7a259e9
--- /dev/null
+++ b/arch/arm/boards/advantech-mx6/Makefile
@@ -0,0 +1,2 @@
+obj-y += board.o
+lwl-y += lowlevel.o
diff --git a/arch/arm/boards/advantech-mx6/board.c b/arch/arm/boards/advantech-mx6/board.c
new file mode 100644
index 0000000000..4a30a845f1
--- /dev/null
+++ b/arch/arm/boards/advantech-mx6/board.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2018 Christoph Fritz <chf.fritz@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <init.h>
+#include <platform_data/eth-fec.h>
+#include <bootsource.h>
+#include <mach/bbu.h>
+
+static int ar8035_phy_fixup(struct phy_device *dev)
+{
+	u16 val;
+
+	/* Ar803x phy SmartEEE feature cause link status generates glitch,
+	 * which cause ethernet link down/up issue, so disable SmartEEE
+	 */
+	phy_write(dev, 0xd, 0x3);
+	phy_write(dev, 0xe, 0x805d);
+	phy_write(dev, 0xd, 0x4003);
+
+	val = phy_read(dev, 0xe);
+	phy_write(dev, 0xe, val & ~BIT(8));
+
+	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+	phy_write(dev, 0xd, 0x7);
+	phy_write(dev, 0xe, 0x8016);
+	phy_write(dev, 0xd, 0x4007);
+
+	val = phy_read(dev, 0xe);
+	val &= 0xffe3;
+	val |= 0x18;
+	phy_write(dev, 0xe, val);
+
+	/* introduce tx clock delay */
+	phy_write(dev, 0x1d, 0x5);
+	val = phy_read(dev, 0x1e);
+	val |= 0x0100;
+	phy_write(dev, 0x1e, val);
+
+	return 0;
+}
+
+static int advantech_mx6_devices_init(void)
+{
+	int ret;
+	char *environment_path, *envdev;
+
+	if (!of_machine_is_compatible("advantech,imx6dl-rom-7421"))
+		return 0;
+
+	phy_register_fixup_for_uid(0x004dd072, 0xffffffef, ar8035_phy_fixup);
+
+	switch (bootsource_get()) {
+	case BOOTSOURCE_MMC:
+		environment_path = basprintf("/chosen/environment-sd%d",
+					     bootsource_get_instance() + 1);
+		if (bootsource_get_instance() + 1 == 4)
+			envdev = "eMMC";
+		else if (bootsource_get_instance() + 1 == 2)
+			envdev = "microSD";
+		else
+			envdev = "MMC";
+		break;
+	case BOOTSOURCE_SPI:
+		envdev = "SPI";
+		environment_path = basprintf("/chosen/environment-spi");
+		break;
+	default:
+		environment_path = basprintf("/chosen/environment-sd4");
+		envdev = "MMC";
+		break;
+	}
+
+	if (environment_path) {
+		ret = of_device_enable_path(environment_path);
+		if (ret < 0)
+			pr_warn("Failed to enable env partition '%s' (%d)\n",
+				environment_path, ret);
+		free(environment_path);
+	}
+
+	pr_notice("Using environment in %s\n", envdev);
+
+	imx6_bbu_internal_mmc_register_handler("mmc3", "/dev/mmc3",
+						BBU_HANDLER_FLAG_DEFAULT);
+
+	return 0;
+}
+device_initcall(advantech_mx6_devices_init);
diff --git a/arch/arm/boards/advantech-mx6/flash-header-advantech-rom-7421.imxcfg b/arch/arm/boards/advantech-mx6/flash-header-advantech-rom-7421.imxcfg
new file mode 100644
index 0000000000..996ecc708d
--- /dev/null
+++ b/arch/arm/boards/advantech-mx6/flash-header-advantech-rom-7421.imxcfg
@@ -0,0 +1,66 @@
+soc imx6
+loadaddr 0x10000000
+dcdofs 0x400
+
+wm 32 0x020e0774 0x000C0000
+wm 32 0x020e0754 0x00000000
+wm 32 0x020e04ac 0x00000030
+wm 32 0x020e04b0 0x00000030
+wm 32 0x020e0464 0x00000030
+wm 32 0x020e0490 0x00000030
+wm 32 0x020e074c 0x00000030
+wm 32 0x020e0494 0x00000030
+wm 32 0x020e04a0 0x00000000
+wm 32 0x020e04b4 0x00000030
+wm 32 0x020e04b8 0x00000030
+wm 32 0x020e076c 0x00000030
+wm 32 0x020e0750 0x00020000
+wm 32 0x020e04bc 0x00000030
+wm 32 0x020e04c0 0x00000030
+wm 32 0x020e04c4 0x00000030
+wm 32 0x020e04c8 0x00000030
+wm 32 0x020e0760 0x00020000
+wm 32 0x020e0764 0x00000030
+wm 32 0x020e0770 0x00000030
+wm 32 0x020e0778 0x00000030
+wm 32 0x020e077c 0x00000030
+wm 32 0x020e0470 0x00000030
+wm 32 0x020e0474 0x00000030
+wm 32 0x020e0478 0x00000030
+wm 32 0x020e047c 0x00000030
+wm 32 0x021b0800 0xa1390003
+wm 32 0x021b080c 0x001F001F
+wm 32 0x021b0810 0x001F001F
+wm 32 0x021b083c 0x42480248
+wm 32 0x021b0840 0x022C0234
+wm 32 0x021b0848 0x3E404244
+wm 32 0x021b0850 0x30302C30
+wm 32 0x021b081c 0x33333333
+wm 32 0x021b0820 0x33333333
+wm 32 0x021b0824 0x33333333
+wm 32 0x021b0828 0x33333333
+wm 32 0x021b08b8 0x00000800
+wm 32 0x021b0004 0x0002002D
+wm 32 0x021b0008 0x00333030
+wm 32 0x021b000c 0x3F435333
+wm 32 0x021b0010 0xB68E8B63
+wm 32 0x021b0014 0x01FF00DB
+wm 32 0x021b0018 0x00001740
+wm 32 0x021b001c 0x00008000
+wm 32 0x021b002c 0x000026d2
+wm 32 0x021b0030 0x00431023
+wm 32 0x021b0040 0x00000017
+wm 32 0x021b0000 0x83190000
+wm 32 0x021b001c 0x04008032
+wm 32 0x021b001c 0x00008033
+wm 32 0x021b001c 0x00048031
+wm 32 0x021b001c 0x05208030
+wm 32 0x021b001c 0x04008040
+wm 32 0x021b0020 0x00005800
+wm 32 0x021b0818 0x00011117
+wm 32 0x021b0004 0x0002556D
+wm 32 0x021b0404 0x00011006
+wm 32 0x021b001c 0x00000000
+wm 32 0x020e0010 0xF00000CF
+wm 32 0x020e0018 0x007F007F
+wm 32 0x020e001c 0x007F007F
diff --git a/arch/arm/boards/advantech-mx6/lowlevel.c b/arch/arm/boards/advantech-mx6/lowlevel.c
new file mode 100644
index 0000000000..8921cd4dd8
--- /dev/null
+++ b/arch/arm/boards/advantech-mx6/lowlevel.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2018 Christoph Fritz <chf.fritz@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <debug_ll.h>
+#include <common.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+#include <image-metadata.h>
+#include <mach/generic.h>
+#include <mach/esdctl.h>
+#include <mach/iomux-mx6.h>
+#include <linux/sizes.h>
+
+#include <linux/sizes.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+static inline void setup_uart(void)
+{
+	void __iomem *iomuxbase = (void *)MX6_IOMUXC_BASE_ADDR;
+
+	imx6_ungate_all_peripherals();
+
+	imx_setup_pad(iomuxbase, MX6Q_PAD_CSI0_DAT10__UART1_TXD);
+
+	imx6_uart_setup_ll();
+
+	putc_ll('>');
+}
+
+extern char __dtb_imx6dl_advantech_rom_7421_start[];
+
+ENTRY_FUNCTION(start_advantech_imx6dl_rom_7421, r0, r1, r2)
+{
+	imx6_cpu_lowlevel_init();
+
+	relocate_to_current_adr();
+	setup_c();
+	barrier();
+
+	if (IS_ENABLED(CONFIG_DEBUG_LL))
+		setup_uart();
+
+	imx6q_barebox_entry(__dtb_imx6dl_advantech_rom_7421_start);
+}
diff --git a/arch/arm/boards/freescale-vf610-twr/lowlevel.c b/arch/arm/boards/freescale-vf610-twr/lowlevel.c
index deabe4e371..8fec9f4b91 100644
--- a/arch/arm/boards/freescale-vf610-twr/lowlevel.c
+++ b/arch/arm/boards/freescale-vf610-twr/lowlevel.c
@@ -3,6 +3,7 @@
 #include <mach/generic.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
+#include <mach/esdctl.h>
 #include <mach/vf610-regs.h>
 #include <mach/clock-vf610.h>
 #include <mach/iomux-vf610.h>
@@ -13,27 +14,21 @@ static inline void setup_uart(void)
 	void __iomem *iomuxbase = IOMEM(VF610_IOMUXC_BASE_ADDR);
 
 	vf610_ungate_all_peripherals();
-
-	/*
-	 * VF610_PAD_PTB4__UART1_TX
-	 */
-	writel(VF610_UART_PAD_CTRL | (2 << 20), iomuxbase + 0x0068);
-	writel(0, iomuxbase + 0x0380);
-
+	vf610_setup_pad(iomuxbase, VF610_PAD_PTB4__UART1_TX);
 	vf610_uart_setup_ll();
+
+	putc_ll('>');
 }
 
 extern char __dtb_vf610_twr_start[];
 
 ENTRY_FUNCTION(start_vf610_twr, r0, r1, r2)
 {
-	void *fdt;
 
 	vf610_cpu_lowlevel_init();
 
 	if (IS_ENABLED(CONFIG_DEBUG_LL))
 		setup_uart();
 
-	fdt = __dtb_vf610_twr_start + get_runtime_offset();
-	barebox_arm_entry(0x80000000, SZ_128M, fdt);
+	vf610_barebox_entry(__dtb_vf610_twr_start + get_runtime_offset());
 }
diff --git a/arch/arm/boards/phytec-som-imx6/board.c b/arch/arm/boards/phytec-som-imx6/board.c
index 717a22963a..1a2d45ec92 100644
--- a/arch/arm/boards/phytec-som-imx6/board.c
+++ b/arch/arm/boards/phytec-som-imx6/board.c
@@ -28,6 +28,7 @@
 #include <gpio.h>
 #include <init.h>
 #include <of.h>
+#include <i2c/i2c.h>
 #include <mach/bbu.h>
 #include <platform_data/eth-fec.h>
 #include <mfd/imx6q-iomuxc-gpr.h>
@@ -51,6 +52,14 @@
 
 #define MX6_PHYFLEX_ERR006282	IMX_GPIO_NR(2, 11)
 
+#define DA9062_I2C_ADDRESS		0x58
+
+#define DA9062_BUCK1_CFG		0x9e
+#define DA9062_BUCK2_CFG		0x9d
+#define DA9062_BUCK3_CFG		0xa0
+#define DA9062_BUCK4_CFG		0x9f
+#define DA9062_BUCKx_MODE_SYNCHRONOUS	(2 << 6)
+
 static void phyflex_err006282_workaround(void)
 {
 	/*
@@ -66,7 +75,7 @@ static void phyflex_err006282_workaround(void)
 	mdelay(2);
 	gpio_set_value(MX6_PHYFLEX_ERR006282, 0);
 
-	if (cpu_is_mx6q() || cpu_is_mx6d())
+	if (cpu_is_mx6q() || cpu_is_mx6d() || cpu_is_mx6qp() || cpu_is_mx6dp())
 		mxc_iomux_v3_setup_pad(MX6Q_PAD_SD4_DAT3__GPIO_2_11_PD);
 	else if (cpu_is_mx6dl() || cpu_is_mx6s())
 		mxc_iomux_v3_setup_pad(MX6DL_PAD_SD4_DAT3__GPIO_2_11);
@@ -96,6 +105,45 @@ int ksz8081_phy_fixup(struct phy_device *phydev)
 	return 0;
 }
 
+static int phycore_da9062_setup_buck_mode(void)
+{
+	struct i2c_adapter *adapter = NULL;
+	struct i2c_client client;
+	unsigned char value;
+	int bus = 0;
+	int ret;
+
+	adapter = i2c_get_adapter(bus);
+	if (!adapter)
+		return -ENODEV;
+
+	client.adapter = adapter;
+	client.addr = DA9062_I2C_ADDRESS;
+
+	value = DA9062_BUCKx_MODE_SYNCHRONOUS;
+
+	ret = i2c_write_reg(&client, DA9062_BUCK1_CFG, &value, 1);
+	if (ret != 1)
+		goto err_out;
+
+	ret = i2c_write_reg(&client, DA9062_BUCK2_CFG, &value, 1);
+	if (ret != 1)
+		goto err_out;
+
+	ret = i2c_write_reg(&client, DA9062_BUCK3_CFG, &value, 1);
+	if (ret != 1)
+		goto err_out;
+
+	ret = i2c_write_reg(&client, DA9062_BUCK4_CFG, &value, 1);
+	if (ret != 1)
+		goto err_out;
+
+	return 0;
+
+err_out:
+	return ret;
+}
+
 static int physom_imx6_devices_init(void)
 {
 	int ret;
@@ -125,8 +173,12 @@ static int physom_imx6_devices_init(void)
 	} else if (of_machine_is_compatible("phytec,imx6q-pcm058-nand")
 		|| of_machine_is_compatible("phytec,imx6q-pcm058-emmc")
 		|| of_machine_is_compatible("phytec,imx6dl-pcm058-nand")
+		|| of_machine_is_compatible("phytec,imx6qp-pcm058-nand")
 		|| of_machine_is_compatible("phytec,imx6dl-pcm058-emmc")) {
 
+		if (phycore_da9062_setup_buck_mode())
+			pr_err("Setting PMIC BUCK mode failed\n");
+
 		barebox_set_hostname("phyCORE-i.MX6");
 		default_environment_path = "/chosen/environment-spinor";
 		default_envdev = "SPI NOR flash";
@@ -184,7 +236,8 @@ static int physom_imx6_devices_init(void)
 	defaultenv_append_directory(defaultenv_physom_imx6);
 
 	/* Overwrite file /env/init/automount */
-	if (of_machine_is_compatible("phytec,imx6q-pcm058-nand")
+	if (of_machine_is_compatible("phytec,imx6qp-pcm058-nand")
+		|| of_machine_is_compatible("phytec,imx6q-pcm058-nand")
 		|| of_machine_is_compatible("phytec,imx6q-pcm058-emmc")
 		|| of_machine_is_compatible("phytec,imx6dl-pcm058-nand")
 		|| of_machine_is_compatible("phytec,imx6dl-pcm058-emmc")) {
diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6-phycore/boot/emmc b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6-phycore/boot/emmc
new file mode 100644
index 0000000000..7ba1d0d0cf
--- /dev/null
+++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6-phycore/boot/emmc
@@ -0,0 +1,5 @@
+#!/bin/sh
+
+global.bootm.image="/mnt/emmc/zImage"
+global.bootm.oftree="/mnt/emmc/oftree"
+global.linux.bootargs.dyn.root="root=/dev/mmcblk1p2 rootwait rw"
diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/emmc b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/emmc
new file mode 100644
index 0000000000..f0d019c3ee
--- /dev/null
+++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/emmc
@@ -0,0 +1,10 @@
+#!/bin/sh
+
+if [ -f /mnt/mmc3/android ]; then
+	# configure here the android specific stuff
+	global linux.bootargs.sec="selinux=0 enforcing=0"
+fi
+
+global.bootm.image="/mnt/mmc3/zImage"
+global.bootm.oftree="/mnt/mmc3/oftree"
+global.linux.bootargs.dyn.root="root=/dev/mmcblk3p2 rootwait rw"
diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/mmc b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/mmc
index 332fc26ad0..3e175122dd 100644
--- a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/mmc
+++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/mmc
@@ -1,5 +1,10 @@
 #!/bin/sh
 
-global.bootm.image="/mnt/mmc/linuximage"
+if [ -f /mnt/mmc/android ]; then
+	# configure here the android specific stuff
+	global linux.bootargs.sec="selinux=0 enforcing=0"
+fi
+
+global.bootm.image="/mnt/mmc/zImage"
 global.bootm.oftree="/mnt/mmc/oftree"
 global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rootwait rw"
diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/nand b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/nand
index a23aa21cc7..0c2b1cbe4c 100644
--- a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/nand
+++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/nand
@@ -1,5 +1,12 @@
 #!/bin/sh
 
-global.bootm.image="/dev/nand0.kernel.bb"
-global.bootm.oftree="/dev/nand0.oftree.bb"
+[ ! -e /dev/nand0.root.ubi ] && ubiattach /dev/nand0.root
+
+if [ -e /dev/nand0.root.ubi.system ]; then
+	# configure here the android specific stuff
+	global linux.bootargs.sec="selinux=0 enforcing=0"
+fi
+
+global.bootm.image="/dev/nand0.root.ubi.kernel"
+global.bootm.oftree="/dev/nand0.root.ubi.oftree"
 global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=root rootfstype=ubifs rw"
diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/automount b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/automount
index 4b223d8037..fea64d627e 100644
--- a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/automount
+++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/automount
@@ -7,3 +7,8 @@ automount /mnt/tftp 'ifup eth0 && mount -t tftp $eth0.serverip /mnt/tftp'
 
 mkdir -p /mnt/mmc
 automount -d /mnt/mmc 'mmc2.probe=1 && [ -e /dev/mmc2.0 ] && mount /dev/mmc2.0 /mnt/mmc'
+
+if [ -e /dev/mmc3 ]; then
+  mkdir -p /mnt/mmc3
+  automount -d /mnt/mmc3 'mmc3.probe=1 && [ -e /dev/mmc3.0 ] && mount /dev/mmc3.0 /mnt/mmc3'
+fi
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-1gib-32bit.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-1gib-32bit.imxcfg
new file mode 100644
index 0000000000..bf95d0f6ae
--- /dev/null
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-1gib-32bit.imxcfg
@@ -0,0 +1,8 @@
+#define SETUP_MDCFG0			\
+	wm 32 0x021b000c 0x8c929b85
+
+#define SETUP_MDASP_MDCTL		\
+	wm 32 0x021b0040 0x00000027;	\
+	wm 32 0x021b0000 0x84190000
+
+#include "flash-header-phytec-pcm058dl.h"
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp-1gib.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp-1gib.imxcfg
new file mode 100644
index 0000000000..bf85f0a19c
--- /dev/null
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp-1gib.imxcfg
@@ -0,0 +1,8 @@
+#define SETUP_MDCFG0			\
+	wm 32 0x021b000c 0x555A7955
+
+#define SETUP_MDASP_MDCTL		\
+	wm 32 0x021b0040 0x00000027;	\
+	wm 32 0x021b0000 0x831A0000
+
+#include "flash-header-phytec-pcm058qp.h"
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp.h
new file mode 100644
index 0000000000..6e7b740a6f
--- /dev/null
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp.h
@@ -0,0 +1,112 @@
+soc imx6
+loadaddr 0x10000000
+dcdofs 0x400
+
+/* NOC setup */
+wm 32 0x00bb0008 0x00000000
+wm 32 0x00bb000c 0x2891E41A
+wm 32 0x00bb0038 0x00000564
+wm 32 0x00bb0014 0x00000040
+wm 32 0x00bb0028 0x00000020
+wm 32 0x00bb002c 0x00000020
+
+wm 32 0x020e0798 0x000C0000
+wm 32 0x020e0758 0x00000000
+wm 32 0x020e0588 0x00000030
+wm 32 0x020e0594 0x00000030
+wm 32 0x020e056c 0x00000030
+wm 32 0x020e0578 0x00000030
+wm 32 0x020e074c 0x00000030
+wm 32 0x020e057c 0x00000030
+wm 32 0x020e058c 0x00000000
+wm 32 0x020e059c 0x00000030
+wm 32 0x020e05a0 0x00000030
+wm 32 0x020e0590 0x00003000
+wm 32 0x020e0598 0x00003000
+wm 32 0x020e078c 0x00000030
+wm 32 0x020e0750 0x00020000
+wm 32 0x020e05a8 0x00000028
+wm 32 0x020e05b0 0x00000028
+wm 32 0x020e0524 0x00000028
+wm 32 0x020e051c 0x00000028
+wm 32 0x020e0518 0x00000028
+wm 32 0x020e050c 0x00000028
+wm 32 0x020e05b8 0x00000028
+wm 32 0x020e05c0 0x00000028
+wm 32 0x020e0774 0x00020000
+wm 32 0x020e0784 0x00000028
+wm 32 0x020e0788 0x00000028
+wm 32 0x020e0794 0x00000028
+wm 32 0x020e079c 0x00000028
+wm 32 0x020e07a0 0x00000028
+wm 32 0x020e07a4 0x00000028
+wm 32 0x020e07a8 0x00000028
+wm 32 0x020e0748 0x00000028
+wm 32 0x020e05ac 0x00000028
+wm 32 0x020e05b4 0x00000028
+wm 32 0x020e0528 0x00000028
+wm 32 0x020e0520 0x00000028
+wm 32 0x020e0514 0x00000028
+wm 32 0x020e0510 0x00000028
+wm 32 0x020e05bc 0x00000028
+wm 32 0x020e05c4 0x00000028
+wm 32 0x021b0800 0xa1390003
+wm 32 0x021b4800 0xa1380003
+wm 32 0x021b080c 0x00140014
+wm 32 0x021b0810 0x00230018
+wm 32 0x021b480c 0x000A001E
+wm 32 0x021b4810 0x000A0015
+wm 32 0x021b083c 0x43080314
+wm 32 0x021b0840 0x02680300
+wm 32 0x021b483c 0x430C0318
+wm 32 0x021b4840 0x03000254
+wm 32 0x021b0848 0x3A323234
+wm 32 0x021b4848 0x3E3C3242
+wm 32 0x021b0850 0x2A2E3632
+wm 32 0x021b4850 0x3C323E34
+wm 32 0x021b081c 0x33333333
+wm 32 0x021b0820 0x33333333
+wm 32 0x021b0824 0x33333333
+wm 32 0x021b0828 0x33333333
+wm 32 0x021b481c 0x33333333
+wm 32 0x021b4820 0x33333333
+wm 32 0x021b4824 0x33333333
+wm 32 0x021b4828 0x33333333
+wm 32 0x021b08b8 0x00000800
+wm 32 0x021b48b8 0x00000800
+wm 32 0x021b0004 0x00020036
+wm 32 0x021b0008 0x09444040
+
+SETUP_MDCFG0
+
+wm 32 0x021b0010 0xFF328F64
+wm 32 0x021b0014 0x01FF00DB
+wm 32 0x021b0018 0x00011740
+wm 32 0x021b001c 0x00008000
+wm 32 0x021b002c 0x000026d2
+wm 32 0x021b0030 0x003F1023
+
+SETUP_MDASP_MDCTL
+
+wm 32 0x021b001c 0x04088032
+wm 32 0x021b001c 0x0408803a
+wm 32 0x021b001c 0x00008033
+wm 32 0x021b001c 0x0000803b
+wm 32 0x021b001c 0x00048031
+wm 32 0x021b001c 0x00048039
+wm 32 0x021b001c 0x09408030
+wm 32 0x021b001c 0x09408038
+wm 32 0x021b001c 0x04008040
+wm 32 0x021b001c 0x04008048
+wm 32 0x021b0020 0x00007800
+wm 32 0x021b0818 0x00011117
+wm 32 0x021b4818 0x00011117
+wm 32 0x021b0890 0x00400c58
+wm 32 0x021b0400 0x14420000
+wm 32 0x021b0004 0x00025576
+wm 32 0x021b0404 0x00011006
+wm 32 0x021b001c 0x00000000
+wm 32 0x020e0010 0xf00000ff
+wm 32 0x020e0018 0x007F007F
+wm 32 0x020e001c 0x007F007F
+wm 32 0x020c8000 0x80002021
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib-1bank.imxcfg
index 156eea971e..7b64e5d2fd 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib-1bank.imxcfg
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib-1bank.imxcfg
@@ -1,5 +1,5 @@
 #define SETUP_MDCFG0                    \
-	wm 32 0x021b000c 0x565c9b85
+	wm 32 0x021b000c 0x41447525
 
 #define SETUP_MDASP_MDCTL		\
 	wm 32 0x021b0040 0x00000027;	\
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg
index e76867004a..04c489d7e8 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg
@@ -1,5 +1,5 @@
 #define SETUP_MDCFG0			\
-	wm 32 0x021b000c 0x8c929b85
+	wm 32 0x021b000c 0x2d307525
 
 #define SETUP_MDASP_MDCTL		\
 	wm 32 0x021b0040 0x00000017;	\
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h
index 405529ddf8..b0f3faa0b7 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h
@@ -74,7 +74,7 @@ wm 32 MX6_MMDC_P0_MDOTC 0x09444040
 
 SETUP_MDCFG0
 
-wm 32 MX6_MMDC_P0_MDCFG1 0xff538f64
+wm 32 MX6_MMDC_P0_MDCFG1 0xb66e8b64
 wm 32 MX6_MMDC_P0_MDCFG2 0x01ff0124
 wm 32 MX6_MMDC_P0_MDMISC 0x00091740
 wm 32 MX6_MMDC_P0_MDSCR 0x00008000
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-128mb-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-128mb-1bank.imxcfg
index 26fe2b2f7d..ebe5a968b1 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-128mb-1bank.imxcfg
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-128mb-1bank.imxcfg
@@ -1,5 +1,5 @@
 #define SETUP_MDCFG0                    \
-        wm 32 0x021b000c 0x3c409b85
+        wm 32 0x021b000c 0x2D307525
 
 #define SETUP_MDASP_MDCTL		\
         wm 32 0x021b0040 0x0000000B;    \
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-256mb-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-256mb-1bank.imxcfg
index babb0dfe24..5f1585a40b 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-256mb-1bank.imxcfg
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-256mb-1bank.imxcfg
@@ -1,5 +1,5 @@
 #define SETUP_MDCFG0                    \
-        wm 32 0x021b000c 0x3c409b85
+        wm 32 0x021b000c 0x2D307525
 
 #define SETUP_MDASP_MDCTL		\
         wm 32 0x021b0040 0x0000000F;    \
diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-512mb-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-512mb-1bank.imxcfg
index 6a46cd958f..5ff3ec69d7 100644
--- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-512mb-1bank.imxcfg
+++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-512mb-1bank.imxcfg
@@ -1,5 +1,5 @@
 #define SETUP_MDCFG0			\
-	wm 32 0x021b000c 0x565c9b85
+	wm 32 0x021b000c 0x41447525
 
 #define SETUP_MDASP_MDCTL		\
 	wm 32 0x021b0040 0x00000017;	\
diff --git a/arch/arm/boards/phytec-som-imx6/lowlevel.c b/arch/arm/boards/phytec-som-imx6/lowlevel.c
index 12c3cfa642..f9d70c7450 100644
--- a/arch/arm/boards/phytec-som-imx6/lowlevel.c
+++ b/arch/arm/boards/phytec-som-imx6/lowlevel.c
@@ -107,8 +107,10 @@ PHYTEC_ENTRY(start_phytec_phyboard_subra_512mb_1bank, imx6dl_phytec_phyboard_sub
 PHYTEC_ENTRY(start_phytec_phyboard_subra_1gib_1bank, imx6q_phytec_phyboard_subra, SZ_1G, false);
 
 PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_nand_256mb, imx6dl_phytec_phycore_som_nand, SZ_256M, true);
+PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_nand_1gib, imx6dl_phytec_phycore_som_nand, SZ_1G, true);
 PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_emmc_1gib, imx6dl_phytec_phycore_som_emmc, SZ_1G, true);
 PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_nand_1gib, imx6q_phytec_phycore_som_nand, SZ_1G, true);
+PHYTEC_ENTRY(start_phytec_phycore_imx6qp_som_nand_1gib, imx6qp_phytec_phycore_som_nand, SZ_1G, true);
 PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_1gib, imx6q_phytec_phycore_som_emmc, SZ_1G, true);
 PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_2gib, imx6q_phytec_phycore_som_emmc, SZ_2G, true);
 
diff --git a/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c b/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c
index 22ffdf85ea..48d02ce645 100644
--- a/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c
+++ b/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c
@@ -284,7 +284,7 @@ static noinline void rdu2_sram_setup(void)
 	relocate_to_current_adr();
 	setup_c();
 
-	if (__imx6_cpu_revision() == IMX_CHIP_REV_2_0)
+	if (__imx6_cpu_type() == IMX6_CPUTYPE_IMX6QP)
 		write_regs(imx6qp_dcd, ARRAY_SIZE(imx6qp_dcd));
 	else
 		write_regs(imx6q_dcd, ARRAY_SIZE(imx6q_dcd));
@@ -304,10 +304,10 @@ ENTRY_FUNCTION(start_imx6_zii_rdu2, r0, r1, r2)
 	 * When still running in SRAM, we need to setup the DRAM now and load
 	 * the remaining image.
 	 */
-	if (get_pc() < MX6_MMDC_PORT0_BASE_ADDR)
+	if (get_pc() < MX6_MMDC_PORT01_BASE_ADDR)
 		rdu2_sram_setup();
 
-	if (__imx6_cpu_revision() == IMX_CHIP_REV_2_0)
+	if (__imx6_cpu_type() == IMX6_CPUTYPE_IMX6QP)
 		imx6q_barebox_entry(__dtb_imx6qp_zii_rdu2_start +
 				    get_runtime_offset());
 	else
diff --git a/arch/arm/boards/zii-vf610-dev/lowlevel.c b/arch/arm/boards/zii-vf610-dev/lowlevel.c
index c6663c1415..f3d67501ab 100644
--- a/arch/arm/boards/zii-vf610-dev/lowlevel.c
+++ b/arch/arm/boards/zii-vf610-dev/lowlevel.c
@@ -18,6 +18,7 @@
 #include <mach/generic.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
+#include <mach/esdctl.h>
 #include <mach/vf610-regs.h>
 #include <mach/clock-vf610.h>
 #include <mach/iomux-vf610.h>
@@ -133,5 +134,5 @@ ENTRY_FUNCTION(start_zii_vf610_dev, r0, r1, r2)
 		break;
 	}
 
-	barebox_arm_entry(0x80000000, SZ_512M, fdt + get_runtime_offset());
+	vf610_barebox_entry(fdt + get_runtime_offset());
 }
diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig
index 426bc04651..8aef9d6ef6 100644
--- a/arch/arm/configs/imx_v7_defconfig
+++ b/arch/arm/configs/imx_v7_defconfig
@@ -32,16 +32,21 @@ CONFIG_MACH_UDOO=y
 CONFIG_MACH_VARISCITE_MX6=y
 CONFIG_MACH_GW_VENTANA=y
 CONFIG_MACH_CM_FX6=y
+CONFIG_MACH_ADVANTECH_ROM_742X=y
+CONFIG_MACH_WARP7=y
+CONFIG_MACH_VF610_TWR=y
+CONFIG_MACH_ZII_RDU2=y
+CONFIG_MACH_ZII_VF610_DEV=y
 CONFIG_MACH_PHYTEC_PHYCORE_IMX7=y
+CONFIG_MACH_FREESCALE_MX7_SABRESD=y
+CONFIG_MACH_NXP_IMX6ULL_EVK=y
 CONFIG_IMX_IIM=y
 CONFIG_IMX_IIM_FUSE_BLOW=y
-CONFIG_IMX_OCOTP=y
 CONFIG_THUMB2_BAREBOX=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
 CONFIG_ARM_UNWIND=y
 CONFIG_ARM_PSCI=y
 CONFIG_MMU=y
-CONFIG_TEXT_BASE=0x0
 CONFIG_MALLOC_SIZE=0x0
 CONFIG_MALLOC_TLSF=y
 CONFIG_KALLSYMS=y
@@ -164,6 +169,7 @@ CONFIG_DRIVER_VIDEO_EDID=y
 CONFIG_MCI=y
 CONFIG_MCI_MMC_BOOT_PARTITIONS=y
 CONFIG_MCI_IMX_ESDHC=y
+CONFIG_MFD_DA9063=y
 CONFIG_MFD_MC34704=y
 CONFIG_MFD_MC9SDZ60=y
 CONFIG_MFD_STMPE=y
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index e60e0ea0c6..b69592e64e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -7,6 +7,7 @@ endif
 # created.
 obj- += dummy.o
 
+pbl-dtb-$(CONFIG_MACH_ADVANTECH_ROM_742X) += imx6dl-advantech-rom-7421.dtb.o
 pbl-dtb-$(CONFIG_MACH_AFI_GF) += am335x-afi-gf.dtb.o
 pbl-dtb-$(CONFIG_MACH_BEAGLEBONE) += am335x-bone.dtb.o am335x-boneblack.dtb.o am335x-bone-common.dtb.o
 pbl-dtb-$(CONFIG_MACH_CM_FX6) += imx6dl-cm-fx6.dtb.o imx6q-cm-fx6.dtb.o imx6q-utilite.dtb.o
@@ -57,6 +58,7 @@ pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-pbaa03.dtb.o \
 				imx6dl-phytec-phyboard-subra.dtb.o \
 				imx6q-phytec-phycore-som-nand.dtb.o \
 				imx6q-phytec-phycore-som-emmc.dtb.o \
+				imx6qp-phytec-phycore-som-nand.dtb.o \
 				imx6dl-phytec-phycore-som-nand.dtb.o \
 				imx6dl-phytec-phycore-som-emmc.dtb.o \
 				imx6ul-phytec-phycore-som.dtb.o \
diff --git a/arch/arm/dts/imx6dl-advantech-rom-7421.dts b/arch/arm/dts/imx6dl-advantech-rom-7421.dts
new file mode 100755
index 0000000000..1d5fd89264
--- /dev/null
+++ b/arch/arm/dts/imx6dl-advantech-rom-7421.dts
@@ -0,0 +1,225 @@
+/*
+ * Copyright(c) 2018 Christoph Fritz <chf.fritz@googlemail.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <arm/imx6dl.dtsi>
+#include "imx6dl.dtsi"
+
+/ {
+	model = "Advantech i.MX6 ROM-7421";
+	compatible = "advantech,imx6dl-rom-7421", "fsl,imx6dl";
+
+	chosen {
+		stdout-path = &uart1;
+
+		environment-sd2 {			/* Micro SD */
+			compatible = "barebox,environment";
+			device-path = &usdhc2, "partname:barebox-environment";
+			status = "disabled";
+		};
+
+		environment-sd4 {			/* eMMC */
+			compatible = "barebox,environment";
+			device-path = &usdhc4, "partname:barebox-environment";
+			status = "disabled";
+		};
+
+		environment-spi {			/* spi nor */
+			compatible = "barebox,environment";
+			device-path = &ecspi1, "partname:barebox-environment";
+			status = "disabled";
+		};
+	};
+};
+
+&ecspi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi1>;
+	fsl,spi-num-chipselects = <1>;
+	cs-gpios = <&gpio3 19 0>;
+	status = "okay";
+
+	flash: m25p80@0 {
+		compatible = "m25p80";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+		status = "okay";
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "barebox";
+			reg = <0x0 0xe0000>;
+		};
+
+		partition@e0000 {
+			label = "barebox-environment";
+			reg = <0xe0000 0x20000>;
+		};
+	};
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet1>;
+	phy-mode = "rgmii";
+	phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
+	fsl,magic-packet;
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&usbh1 {
+	status = "okay";
+};
+
+&usdhc2 {					/* Micro SD */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	bus-width = <8>;
+	cd-gpios = <&gpio2 0 0>;
+	status = "okay";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	partition@0 {
+		label = "barebox";
+		reg = <0x0 0xe0000>;
+	};
+
+	partition@e0000 {
+		label = "barebox-environment";
+		reg = <0xe0000 0x20000>;
+	};
+};
+
+&usdhc3 {					/* SD Card */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	bus-width = <4>;
+	cd-gpios = <&gpio2 1 0>;
+	en-gpios = <&gpio2 2 0>;
+	wp-gpios = <&gpio2 3 0>;
+	status = "okay";
+};
+
+&usdhc4 {					/* eMMC */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc4>;
+	bus-width = <8>;
+	non-removable;
+	no-1-8-v;
+	status = "okay";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	partition@0 {
+		label = "barebox";
+		reg = <0x0 0xe0000>;
+	};
+
+	partition@e0000 {
+		label = "barebox-environment";
+		reg = <0xe0000 0x20000>;
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+
+	pinctrl_ecspi1: ecspi1grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D16__ECSPI1_SCLK		0x100b1
+			MX6QDL_PAD_EIM_D17__ECSPI1_MISO		0x100b1
+			MX6QDL_PAD_EIM_D18__ECSPI1_MOSI		0x100b1
+			MX6QDL_PAD_EIM_D19__GPIO3_IO19		0x80000000
+		>;
+	};
+
+	pinctrl_enet1: enet1grp {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
+			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
+			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x0A0B1
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
+			MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25	0x80000000
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1
+			MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
+			MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
+			MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
+			MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
+			MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
+			MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
+			MX6QDL_PAD_NANDF_D0__GPIO2_IO00		0x1b0b0
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
+			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
+			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
+			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
+			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
+			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
+			MX6QDL_PAD_NANDF_D1__GPIO2_IO01		0x1b0b0
+			MX6QDL_PAD_NANDF_D2__GPIO2_IO02		0x1b0b0
+			MX6QDL_PAD_NANDF_D3__GPIO2_IO03		0x1b0b0
+		>;
+	};
+
+	pinctrl_usdhc4: usdhc4grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_CMD__SD4_CMD		0x17059
+			MX6QDL_PAD_SD4_CLK__SD4_CLK		0x10059
+			MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x17059
+			MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x17059
+			MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x17059
+			MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x17059
+			MX6QDL_PAD_SD4_DAT4__SD4_DATA4		0x17059
+			MX6QDL_PAD_SD4_DAT5__SD4_DATA5		0x17059
+			MX6QDL_PAD_SD4_DAT6__SD4_DATA6		0x17059
+			MX6QDL_PAD_SD4_DAT7__SD4_DATA7		0x17059
+		>;
+	};
+};
diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts b/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
index bffee5f154..7e4a5aba2a 100644
--- a/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
+++ b/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
@@ -41,6 +41,14 @@
 	status = "okay";
 };
 
+&usbh1 {
+	status = "okay";
+};
+
+&usbotg {
+	status = "okay";
+};
+
 &usdhc1 {
 	status = "okay";
 
diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts b/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts
index 1b66fdabc6..ffcbdc2134 100644
--- a/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts
+++ b/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts
@@ -36,6 +36,14 @@
 	status = "okay";
 };
 
+&usbh1 {
+	status = "okay";
+};
+
+&usbotg {
+	status = "okay";
+};
+
 &usdhc1 {
 	status = "okay";
 
diff --git a/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi b/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi
index a6ea7b5cce..63dd966b87 100644
--- a/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi
+++ b/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi
@@ -145,18 +145,8 @@
 	};
 
 	partition@420000 {
-		label = "oftree";
-		reg = <0x420000 0x20000>;
-	};
-
-	partition@440000 {
-		label = "kernel";
-		reg = <0x440000 0x800000>;
-	};
-
-	partition@C40000 {
 		label = "root";
-		reg = <0xC40000 0x0>;
+		reg = <0x420000 0x0>;
 	};
 };
 
diff --git a/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts b/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts
index ecc5aa38e1..6e12b26d38 100644
--- a/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts
+++ b/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts
@@ -40,6 +40,14 @@
 	status = "okay";
 };
 
+&usbh1 {
+	status = "okay";
+};
+
+&usbotg {
+	status = "okay";
+};
+
 &usdhc1 {
 	status = "okay";
 
diff --git a/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts b/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts
index 9ad7eda740..d9e37b7fca 100644
--- a/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts
+++ b/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts
@@ -45,6 +45,14 @@
 	status = "okay";
 };
 
+&usbh1 {
+	status = "okay";
+};
+
+&usbotg {
+	status = "okay";
+};
+
 &usdhc1 {
 	status = "okay";
 
diff --git a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
index 9a8c7024a3..862d856d00 100644
--- a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
@@ -115,18 +115,8 @@
 	};
 
 	partition@500000 {
-		label = "oftree";
-		reg = <0x500000 0x100000>;
-	};
-
-	partition@600000 {
-		label = "kernel";
-		reg = <0x600000 0x800000>;
-	};
-
-	partition@e00000 {
 		label = "root";
-		reg = <0xe00000 0x0>;
+		reg = <0x500000 0x0>;
 	};
 };
 
diff --git a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
index b10530cbcf..15fed812b0 100644
--- a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
@@ -32,6 +32,34 @@
 			device-path = &gpmi, "partname:barebox-environment";
 			status = "disabled";
 		};
+
+		environment-spinor {
+			compatible = "barebox,environment";
+			device-path = &flash, "partname:barebox-environment";
+			status = "disabled";
+		};
+	};
+
+	reg_usbh1_vbus: regulator-usbh1 {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usbh1_vbus>;
+		regulator-name = "usbh1_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio2 18 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	reg_usbotg_vbus: regulator-usbotg {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usbotg_vbus>;
+		regulator-name = "usbotg_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
 	};
 };
 
@@ -42,8 +70,8 @@
 	cs-gpios = <&gpio3 19 0>;
 	status = "disabled";
 
-	flash: m25p80@0 {
-		compatible = "m25p80";
+	flash: flash@0 {
+		compatible = "jedec,spi-nor";
 		spi-max-frequency = <20000000>;
 		reg = <0>;
 		status = "disabled";
@@ -112,18 +140,8 @@
 	};
 
 	partition@500000 {
-		label = "oftree";
-		reg = <0x500000 0x100000>;
-	};
-
-	partition@600000 {
-		label = "kernel";
-		reg = <0x600000 0x800000>;
-	};
-
-	partition@e00000 {
 		label = "root";
-		reg = <0xe00000 0x0>;
+		reg = <0x500000 0x0>;
 	};
 };
 
@@ -141,104 +159,118 @@
 };
 
 &iomuxc {
-	pinctrl-names = "default";
+	pinctrl_ecspi1: ecspi1grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D16__ECSPI1_SCLK		0x100b1
+			MX6QDL_PAD_EIM_D17__ECSPI1_MISO		0x100b1
+			MX6QDL_PAD_EIM_D18__ECSPI1_MOSI		0x100b1
+			MX6QDL_PAD_EIM_D19__GPIO3_IO19		0x80000000
+		>;
+	};
 
-	imx6qdl-phytec-phycore-som {
-		pinctrl_ecspi1: ecspi1grp {
-			fsl,pins = <
-				MX6QDL_PAD_EIM_D16__ECSPI1_SCLK		0x100b1
-				MX6QDL_PAD_EIM_D17__ECSPI1_MISO		0x100b1
-				MX6QDL_PAD_EIM_D18__ECSPI1_MOSI		0x100b1
-				MX6QDL_PAD_EIM_D19__GPIO3_IO19		0x80000000
-			>;
-		};
+	pinctrl_enet: enetgrp {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
+			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0
+			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
+			MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN	0x1b0b0
+			MX6QDL_PAD_SD2_DAT1__GPIO1_IO14		0x80000000
+		>;
+	};
 
-		pinctrl_enet: enetgrp {
-			fsl,pins = <
-				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
-				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
-				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0
-				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0
-				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0
-				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0
-				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0
-				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0
-				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
-				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
-				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
-				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
-				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
-				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
-				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
-				MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN	0x1b0b0
-				MX6QDL_PAD_SD2_DAT1__GPIO1_IO14		0x80000000
-			>;
-		};
+	pinctrl_gpmi_nand: gpmigrp {
+		fsl,pins = <
+			MX6QDL_PAD_NANDF_CLE__NAND_CLE		0xb0b1
+			MX6QDL_PAD_NANDF_ALE__NAND_ALE		0xb0b1
+			MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
+			MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
+			MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
+			MX6QDL_PAD_NANDF_CS1__NAND_CE1_B	0xb0b1
+			MX6QDL_PAD_NANDF_CS2__NAND_CE2_B	0xb0b1
+			MX6QDL_PAD_NANDF_CS3__NAND_CE3_B	0xb0b1
+			MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
+			MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
+			MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
+			MX6QDL_PAD_NANDF_D1__NAND_DATA01	0xb0b1
+			MX6QDL_PAD_NANDF_D2__NAND_DATA02	0xb0b1
+			MX6QDL_PAD_NANDF_D3__NAND_DATA03	0xb0b1
+			MX6QDL_PAD_NANDF_D4__NAND_DATA04	0xb0b1
+			MX6QDL_PAD_NANDF_D5__NAND_DATA05	0xb0b1
+			MX6QDL_PAD_NANDF_D6__NAND_DATA06	0xb0b1
+			MX6QDL_PAD_NANDF_D7__NAND_DATA07	0xb0b1
+			MX6QDL_PAD_SD4_DAT0__NAND_DQS		0x00b1
+		>;
+	};
 
-		pinctrl_gpmi_nand: gpmigrp {
-			fsl,pins = <
-				MX6QDL_PAD_NANDF_CLE__NAND_CLE		0xb0b1
-				MX6QDL_PAD_NANDF_ALE__NAND_ALE		0xb0b1
-				MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
-				MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
-				MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
-				MX6QDL_PAD_NANDF_CS1__NAND_CE1_B	0xb0b1
-				MX6QDL_PAD_NANDF_CS2__NAND_CE2_B	0xb0b1
-				MX6QDL_PAD_NANDF_CS3__NAND_CE3_B	0xb0b1
-				MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
-				MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
-				MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
-				MX6QDL_PAD_NANDF_D1__NAND_DATA01	0xb0b1
-				MX6QDL_PAD_NANDF_D2__NAND_DATA02	0xb0b1
-				MX6QDL_PAD_NANDF_D3__NAND_DATA03	0xb0b1
-				MX6QDL_PAD_NANDF_D4__NAND_DATA04	0xb0b1
-				MX6QDL_PAD_NANDF_D5__NAND_DATA05	0xb0b1
-				MX6QDL_PAD_NANDF_D6__NAND_DATA06	0xb0b1
-				MX6QDL_PAD_NANDF_D7__NAND_DATA07	0xb0b1
-				MX6QDL_PAD_SD4_DAT0__NAND_DQS		0x00b1
-			>;
-		};
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
+			MX6QDL_PAD_GPIO_5__I2C3_SCL		0x4001b8b1
+		>;
+	};
 
-		pinctrl_i2c3: i2c3grp {
-			fsl,pins = <
-				MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
-				MX6QDL_PAD_GPIO_5__I2C3_SCL		0x4001b8b1
-			>;
-		};
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D26__UART2_TX_DATA	0x1b0b1
+			MX6QDL_PAD_EIM_D27__UART2_RX_DATA	0x1b0b1
+		>;
+	};
 
-		pinctrl_uart2: uart2grp {
-			fsl,pins = <
-				MX6QDL_PAD_EIM_D26__UART2_TX_DATA	0x1b0b1
-				MX6QDL_PAD_EIM_D27__UART2_RX_DATA	0x1b0b1
-			>;
-		};
+	pinctrl_usbh1_vbus: usbh1vbusgrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_A20__GPIO2_IO18		0xb0b1
+		>;
+	};
 
-		pinctrl_usdhc1: usdhc1grp {
-			fsl,pins = <
-				MX6QDL_PAD_SD1_CMD__SD1_CMD		0x17059
-				MX6QDL_PAD_SD1_CLK__SD1_CLK		0x10059
-				MX6QDL_PAD_SD1_DAT0__SD1_DATA0		0x17059
-				MX6QDL_PAD_SD1_DAT1__SD1_DATA1		0x17059
-				MX6QDL_PAD_SD1_DAT2__SD1_DATA2		0x17059
-				MX6QDL_PAD_SD1_DAT3__SD1_DATA3		0x17059
-				MX6QDL_PAD_EIM_BCLK__GPIO6_IO31		0x80000000 /* CD */
-			>;
-		};
+	pinctrl_usbotg: usbotggrp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
+		>;
+	};
 
-		pinctrl_usdhc4: usdhc4grp {
-			fsl,pins = <
-				MX6QDL_PAD_SD4_CMD__SD4_CMD		0x17059
-				MX6QDL_PAD_SD4_CLK__SD4_CLK		0x10059
-				MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x17059
-				MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x17059
-				MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x17059
-				MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x17059
-				MX6QDL_PAD_SD4_DAT4__SD4_DATA4		0x17059
-				MX6QDL_PAD_SD4_DAT5__SD4_DATA5		0x17059
-				MX6QDL_PAD_SD4_DAT6__SD4_DATA6		0x17059
-				MX6QDL_PAD_SD4_DAT7__SD4_DATA7		0x17059
+	pinctrl_usbotg_vbus: usbotgvbusgrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_A19__GPIO2_IO19		0xb0b1
 			>;
-		};
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD1_CMD__SD1_CMD		0x170f9
+			MX6QDL_PAD_SD1_CLK__SD1_CLK		0x100f9
+			MX6QDL_PAD_SD1_DAT0__SD1_DATA0		0x170f9
+			MX6QDL_PAD_SD1_DAT1__SD1_DATA1		0x170f9
+			MX6QDL_PAD_SD1_DAT2__SD1_DATA2		0x170f9
+			MX6QDL_PAD_SD1_DAT3__SD1_DATA3		0x170f9
+			MX6QDL_PAD_EIM_BCLK__GPIO6_IO31		0x80000000 /* CD */
+		>;
+	};
+
+	pinctrl_usdhc4: usdhc4grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_CMD__SD4_CMD		0x17059
+			MX6QDL_PAD_SD4_CLK__SD4_CLK		0x10059
+			MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x17059
+			MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x17059
+			MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x17059
+			MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x17059
+			MX6QDL_PAD_SD4_DAT4__SD4_DATA4		0x17059
+			MX6QDL_PAD_SD4_DAT5__SD4_DATA5		0x17059
+			MX6QDL_PAD_SD4_DAT6__SD4_DATA6		0x17059
+			MX6QDL_PAD_SD4_DAT7__SD4_DATA7		0x17059
+		>;
 	};
 };
 
@@ -252,6 +284,20 @@
 	status = "okay";
 };
 
+&usbh1 {
+	vbus-supply = <&reg_usbh1_vbus>;
+	disable-over-current;
+	status = "disabled";
+};
+
+&usbotg {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg>;
+	vbus-supply = <&reg_usbotg_vbus>;
+	disable-over-current;
+	status = "disabled";
+};
+
 &usdhc1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usdhc1>;
diff --git a/arch/arm/dts/imx6qp-phytec-phycore-som-nand.dts b/arch/arm/dts/imx6qp-phytec-phycore-som-nand.dts
new file mode 100644
index 0000000000..c2756142b5
--- /dev/null
+++ b/arch/arm/dts/imx6qp-phytec-phycore-som-nand.dts
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2016 Phytec Messtechnik GmbH
+ * Author: Christian Hemp <c.hemp@phytec.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include <arm/imx6qp.dtsi>
+#include "imx6qdl-phytec-phycore-som.dtsi"
+
+/ {
+	model = "Phytec phyCORE-i.MX6 Quad with NAND";
+	compatible = "phytec,imx6qp-pcm058-nand", "fsl,imx6qp";
+};
+
+&ecspi1 {
+	status = "okay";
+};
+
+&eeprom {
+	status = "okay";
+};
+
+&ethphy {
+	max-speed = <1000>;
+};
+
+&fec {
+	status = "okay";
+};
+
+&flash {
+	status = "okay";
+};
+
+&gpmi {
+	status = "okay";
+};
+
+&usbh1 {
+	status = "okay";
+};
+
+&usbotg {
+	status = "okay";
+};
+
+&usdhc1 {
+	status = "okay";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	partition@0 {
+		label = "barebox";
+		reg = <0x0 0xe0000>;
+	};
+
+	partition@e0000 {
+		label = "barebox-environment";
+		reg = <0xe0000 0x20000>;
+	};
+};
diff --git a/arch/arm/dts/vf610-ddrmc.dtsi b/arch/arm/dts/vf610-ddrmc.dtsi
new file mode 100644
index 0000000000..772131ec28
--- /dev/null
+++ b/arch/arm/dts/vf610-ddrmc.dtsi
@@ -0,0 +1,15 @@
+/*
+ * Include file to switch board DTS form using hardcoded memory node
+ * to dynamic memory size detection based on DDR controller settings
+ */
+
+/ {
+	/delete-node/ memory;
+};
+
+&aips1 {
+	ddrmc@400ae000 {
+		compatible = "fsl,vf610-ddrmc";
+		reg = <0x400ae000 0x1000>;
+	};
+};
diff --git a/arch/arm/dts/vf610-twr.dts b/arch/arm/dts/vf610-twr.dts
index 5947fdbdaa..2456ade5f5 100644
--- a/arch/arm/dts/vf610-twr.dts
+++ b/arch/arm/dts/vf610-twr.dts
@@ -8,6 +8,7 @@
  */
 
 #include <arm/vf610-twr.dts>
+#include "vf610-ddrmc.dtsi"
 
 &usbdev0 {
 	status = "disabled";
diff --git a/arch/arm/dts/vf610-zii-dev.dtsi b/arch/arm/dts/vf610-zii-dev.dtsi
index 4bf81451a6..dc16280bc3 100644
--- a/arch/arm/dts/vf610-zii-dev.dtsi
+++ b/arch/arm/dts/vf610-zii-dev.dtsi
@@ -40,7 +40,9 @@ n *     copy, modify, merge, publish, distribute, sublicense, and/or
  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  *     OTHER DEALINGS IN THE SOFTWARE.
- */
+*/
+
+#include "vf610-ddrmc.dtsi"
 
 / {
 	audio_ext: mclk_osc {
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 9052a94ea0..e6956acbdb 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -393,6 +393,11 @@ config MACH_CM_FX6
 	bool "CM FX6"
 	select ARCH_IMX6
 
+config MACH_ADVANTECH_ROM_742X
+	bool "Advantech ROM 742X"
+	select ARCH_IMX6
+	select ARM_USE_COMPRESSED_DTB
+
 config MACH_WARP7
 	bool "NXP i.MX7: element 14 WaRP7 Board"
 	select ARCH_IMX7
diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c
index 1eebc77b63..c1680d5ff8 100644
--- a/arch/arm/mach-imx/esdctl.c
+++ b/arch/arm/mach-imx/esdctl.c
@@ -37,6 +37,7 @@
 #include <mach/imx51-regs.h>
 #include <mach/imx53-regs.h>
 #include <mach/imx6-regs.h>
+#include <mach/vf610-ddrmc.h>
 
 struct imx_esdctl_data {
 	unsigned long base0;
@@ -75,12 +76,9 @@ static inline unsigned long imx_v1_sdram_size(void __iomem *esdctlbase, int num)
 	if (ctlval & (1 << 17))
 		width = 4;
 
-	size = (1 << cols) * (1 << rows) * banks * width;
+	size = memory_sdram_size(cols, rows, banks, width);
 
-	if (size > SZ_64M)
-		size = SZ_64M;
-
-	return size;
+	return min_t(unsigned long, size, SZ_64M);
 }
 
 /*
@@ -103,12 +101,9 @@ static inline unsigned long imx_v2_sdram_size(void __iomem *esdctlbase, int num)
 	if ((ctlval & ESDCTL0_DSIZ_MASK) == ESDCTL0_DSIZ_31_0)
 		width = 4;
 
-	size = (1 << cols) * (1 << rows) * banks * width;
-
-	if (size > SZ_256M)
-		size = SZ_256M;
+	size = memory_sdram_size(cols, rows, banks, width);
 
-	return size;
+	return min_t(unsigned long, size, SZ_256M);
 }
 
 /*
@@ -120,13 +115,10 @@ static inline unsigned long imx_v3_sdram_size(void __iomem *esdctlbase, int num)
 
 	size = imx_v2_sdram_size(esdctlbase, num);
 
-	if (readl(esdctlbase + IMX_ESDMISC) & (1 << 6))
+	if (readl(esdctlbase + IMX_ESDMISC) & ESDMISC_DDR2_8_BANK)
 		size *= 2;
 
-	if (size > SZ_256M)
-		size = SZ_256M;
-
-	return size;
+	return min_t(unsigned long, size, SZ_256M);
 }
 
 /*
@@ -136,7 +128,6 @@ static inline unsigned long imx_v4_sdram_size(void __iomem *esdctlbase, int cs)
 {
 	u32 ctlval = readl(esdctlbase + ESDCTL_V4_ESDCTL0);
 	u32 esdmisc = readl(esdctlbase + ESDCTL_V4_ESDMISC);
-	unsigned long size;
 	int rows, cols, width = 2, banks = 8;
 
 	if (cs == 0 && !(ctlval & ESDCTL_V4_ESDCTLx_SDE0))
@@ -162,20 +153,17 @@ static inline unsigned long imx_v4_sdram_size(void __iomem *esdctlbase, int cs)
 	if (esdmisc & ESDCTL_V4_ESDMISC_BANKS_4)
 		banks = 4;
 
-	size = (1 << cols) * (1 << rows) * banks * width;
-
-	return size;
+	return memory_sdram_size(cols, rows, banks, width);
 }
 
 /*
  * MMDC - found on i.MX6
  */
 
-static inline u64 imx6_mmdc_sdram_size(void __iomem *mmdcbase, int cs)
+static inline u64 __imx6_mmdc_sdram_size(void __iomem *mmdcbase, int cs)
 {
 	u32 ctlval = readl(mmdcbase + MDCTL);
 	u32 mdmisc = readl(mmdcbase + MDMISC);
-	u64 size;
 	int rows, cols, width = 2, banks = 8;
 
 	if (cs == 0 && !(ctlval & MMDCx_MDCTL_SDE0))
@@ -201,9 +189,7 @@ static inline u64 imx6_mmdc_sdram_size(void __iomem *mmdcbase, int cs)
 	if (mdmisc & MMDCx_MDMISC_DDR_4_BANKS)
 		banks = 4;
 
-	size = (u64)(1 << cols) * (1 << rows) * banks * width;
-
-	return size;
+	return memory_sdram_size(cols, rows, banks, width);
 }
 
 static void add_mem(unsigned long base0, unsigned long size0,
@@ -286,7 +272,7 @@ static void imx_esdctl_v4_add_mem(void *esdctlbase, struct imx_esdctl_data *data
  */
 #define IMX6_MAX_SDRAM_SIZE 0xF0000000
 
-static void imx6_mmdc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
+static inline resource_size_t imx6_mmdc_sdram_size(void __iomem *mmdcbase)
 {
 	/*
 	 * It is possible to have a configuration in which both chip
@@ -296,14 +282,41 @@ static void imx6_mmdc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
 	 * IMX6_MAX_SDRAM_SIZE bytes of memory available.
 	 */
 
-	u64 size_cs0 = imx6_mmdc_sdram_size(mmdcbase, 0);
-	u64 size_cs1 = imx6_mmdc_sdram_size(mmdcbase, 1);
+	u64 size_cs0 = __imx6_mmdc_sdram_size(mmdcbase, 0);
+	u64 size_cs1 = __imx6_mmdc_sdram_size(mmdcbase, 1);
 	u64 total    = size_cs0 + size_cs1;
 
 	resource_size_t size = min(total, (u64)IMX6_MAX_SDRAM_SIZE);
 
+	return size;
+}
+
+static void imx6_mmdc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
+{
+	arm_add_mem_device("ram0", data->base0,
+			   imx6_mmdc_sdram_size(mmdcbase));
+}
+
+static inline resource_size_t vf610_ddrmc_sdram_size(void __iomem *ddrmc)
+{
+	const u32 cr01 = readl(ddrmc + DDRMC_CR(1));
+	const u32 cr73 = readl(ddrmc + DDRMC_CR(73));
+	const u32 cr78 = readl(ddrmc + DDRMC_CR(78));
+
+	unsigned int rows, cols, width, banks;
+
+	rows  = DDRMC_CR01_MAX_ROW_REG(cr01) - DDRMC_CR73_ROW_DIFF(cr73);
+	cols  = DDRMC_CR01_MAX_COL_REG(cr01) - DDRMC_CR73_COL_DIFF(cr73);
+	banks = 1 << (3 - DDRMC_CR73_BANK_DIFF(cr73));
+	width = (cr78 & DDRMC_CR78_REDUC) ? sizeof(u8) : sizeof(u16);
+
+	return memory_sdram_size(cols, rows, banks, width);
+}
+
+static void vf610_ddrmc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
+{
 	arm_add_mem_device("ram0", data->base0,
-			size);
+			   vf610_ddrmc_sdram_size(mmdcbase));
 }
 
 static int imx_esdctl_probe(struct device_d *dev)
@@ -373,15 +386,20 @@ static __maybe_unused struct imx_esdctl_data imx53_data = {
 };
 
 static __maybe_unused struct imx_esdctl_data imx6q_data = {
-	.base0 = MX6_MMDC_PORT0_BASE_ADDR,
+	.base0 = MX6_MMDC_PORT01_BASE_ADDR,
 	.add_mem = imx6_mmdc_add_mem,
 };
 
 static __maybe_unused struct imx_esdctl_data imx6ul_data = {
-	.base0 = 0x80000000,
+	.base0 = MX6_MMDC_PORT0_BASE_ADDR,
 	.add_mem = imx6_mmdc_add_mem,
 };
 
+static __maybe_unused struct imx_esdctl_data vf610_data = {
+	.base0 = VF610_RAM_BASE_ADDR,
+	.add_mem = vf610_ddrmc_add_mem,
+};
+
 static struct platform_device_id imx_esdctl_ids[] = {
 #ifdef CONFIG_ARCH_IMX1
 	{
@@ -441,6 +459,9 @@ static __maybe_unused struct of_device_id imx_esdctl_dt_ids[] = {
 		.compatible = "fsl,imx6q-mmdc",
 		.data = &imx6q_data
 	}, {
+		.compatible = "fsl,vf610-ddrmc",
+		.data = &vf610_data
+	}, {
 		/* sentinel */
 	}
 };
@@ -498,9 +519,9 @@ void __noreturn imx1_barebox_entry(void *boarddata)
 	unsigned long base, size;
 
 	upper_or_coalesced_range(MX1_CSD0_BASE_ADDR,
-			imx_v1_sdram_size((void *)MX1_SDRAMC_BASE_ADDR, 0),
+			imx_v1_sdram_size(IOMEM(MX1_SDRAMC_BASE_ADDR), 0),
 			MX1_CSD1_BASE_ADDR,
-			imx_v1_sdram_size((void *)MX1_SDRAMC_BASE_ADDR, 1),
+			imx_v1_sdram_size(IOMEM(MX1_SDRAMC_BASE_ADDR), 1),
 			&base, &size);
 
 	barebox_arm_entry(base, size, boarddata);
@@ -511,9 +532,9 @@ void __noreturn imx25_barebox_entry(void *boarddata)
 	unsigned long base, size;
 
 	upper_or_coalesced_range(MX25_CSD0_BASE_ADDR,
-			imx_v2_sdram_size((void *)MX25_ESDCTL_BASE_ADDR, 0),
+			imx_v2_sdram_size(IOMEM(MX25_ESDCTL_BASE_ADDR), 0),
 			MX25_CSD1_BASE_ADDR,
-			imx_v2_sdram_size((void *)MX25_ESDCTL_BASE_ADDR, 1),
+			imx_v2_sdram_size(IOMEM(MX25_ESDCTL_BASE_ADDR), 1),
 			&base, &size);
 
 	barebox_arm_entry(base, size, boarddata);
@@ -523,12 +544,12 @@ void __noreturn imx27_barebox_entry(void *boarddata)
 {
 	unsigned long base, size;
 
-	imx_esdctl_v2_disable_default((void *)MX27_ESDCTL_BASE_ADDR);
+	imx_esdctl_v2_disable_default(IOMEM(MX27_ESDCTL_BASE_ADDR));
 
 	upper_or_coalesced_range(MX27_CSD0_BASE_ADDR,
-			imx_v2_sdram_size((void *)MX27_ESDCTL_BASE_ADDR, 0),
+			imx_v2_sdram_size(IOMEM(MX27_ESDCTL_BASE_ADDR), 0),
 			MX27_CSD1_BASE_ADDR,
-			imx_v2_sdram_size((void *)MX27_ESDCTL_BASE_ADDR, 1),
+			imx_v2_sdram_size(IOMEM(MX27_ESDCTL_BASE_ADDR), 1),
 			&base, &size);
 
 	barebox_arm_entry(base, size, boarddata);
@@ -538,12 +559,12 @@ void __noreturn imx31_barebox_entry(void *boarddata)
 {
 	unsigned long base, size;
 
-	imx_esdctl_v2_disable_default((void *)MX31_ESDCTL_BASE_ADDR);
+	imx_esdctl_v2_disable_default(IOMEM(MX31_ESDCTL_BASE_ADDR));
 
 	upper_or_coalesced_range(MX31_CSD0_BASE_ADDR,
-			imx_v2_sdram_size((void *)MX31_ESDCTL_BASE_ADDR, 0),
+			imx_v2_sdram_size(IOMEM(MX31_ESDCTL_BASE_ADDR), 0),
 			MX31_CSD1_BASE_ADDR,
-			imx_v2_sdram_size((void *)MX31_ESDCTL_BASE_ADDR, 1),
+			imx_v2_sdram_size(IOMEM(MX31_ESDCTL_BASE_ADDR), 1),
 			&base, &size);
 
 	barebox_arm_entry(base, size, boarddata);
@@ -553,12 +574,12 @@ void __noreturn imx35_barebox_entry(void *boarddata)
 {
 	unsigned long base, size;
 
-	imx_esdctl_v2_disable_default((void *)MX35_ESDCTL_BASE_ADDR);
+	imx_esdctl_v2_disable_default(IOMEM(MX35_ESDCTL_BASE_ADDR));
 
 	upper_or_coalesced_range(MX35_CSD0_BASE_ADDR,
-			imx_v2_sdram_size((void *)MX35_ESDCTL_BASE_ADDR, 0),
+			imx_v2_sdram_size(IOMEM(MX35_ESDCTL_BASE_ADDR), 0),
 			MX35_CSD1_BASE_ADDR,
-			imx_v2_sdram_size((void *)MX35_ESDCTL_BASE_ADDR, 1),
+			imx_v2_sdram_size(IOMEM(MX35_ESDCTL_BASE_ADDR), 1),
 			&base, &size);
 
 	barebox_arm_entry(base, size, boarddata);
@@ -569,9 +590,9 @@ void __noreturn imx51_barebox_entry(void *boarddata)
 	unsigned long base, size;
 
 	upper_or_coalesced_range(MX51_CSD0_BASE_ADDR,
-			imx_v3_sdram_size((void *)MX51_ESDCTL_BASE_ADDR, 0),
+			imx_v3_sdram_size(IOMEM(MX51_ESDCTL_BASE_ADDR), 0),
 			MX51_CSD1_BASE_ADDR,
-			imx_v3_sdram_size((void *)MX51_ESDCTL_BASE_ADDR, 1),
+			imx_v3_sdram_size(IOMEM(MX51_ESDCTL_BASE_ADDR), 1),
 			&base, &size);
 
 	barebox_arm_entry(base, size, boarddata);
@@ -582,32 +603,35 @@ void __noreturn imx53_barebox_entry(void *boarddata)
 	unsigned long base, size;
 
 	upper_or_coalesced_range(MX53_CSD0_BASE_ADDR,
-			imx_v4_sdram_size((void *)MX53_ESDCTL_BASE_ADDR, 0),
+			imx_v4_sdram_size(IOMEM(MX53_ESDCTL_BASE_ADDR), 0),
 			MX53_CSD1_BASE_ADDR,
-			imx_v4_sdram_size((void *)MX53_ESDCTL_BASE_ADDR, 1),
+			imx_v4_sdram_size(IOMEM(MX53_ESDCTL_BASE_ADDR), 1),
 			&base, &size);
 
 	barebox_arm_entry(base, size, boarddata);
 }
 
-void __noreturn imx6q_barebox_entry(void *boarddata)
+static void __noreturn
+imx6_barebox_entry(unsigned long membase, void *boarddata)
 {
-	u64 size_cs0 = imx6_mmdc_sdram_size((void *)MX6_MMDC_P0_BASE_ADDR, 0);
-	u64 size_cs1 = imx6_mmdc_sdram_size((void *)MX6_MMDC_P0_BASE_ADDR, 1);
-	u64 total    = size_cs0 + size_cs1;
-
-	resource_size_t size = min(total, (u64)IMX6_MAX_SDRAM_SIZE);
+	barebox_arm_entry(membase,
+			  imx6_mmdc_sdram_size(IOMEM(MX6_MMDC_P0_BASE_ADDR)),
+			  boarddata);
+}
 
-	barebox_arm_entry(0x10000000, size, boarddata);
+void __noreturn imx6q_barebox_entry(void *boarddata)
+{
+	imx6_barebox_entry(MX6_MMDC_PORT01_BASE_ADDR, boarddata);
 }
 
 void __noreturn imx6ul_barebox_entry(void *boarddata)
 {
-	u64 size_cs0 = imx6_mmdc_sdram_size((void *)MX6_MMDC_P0_BASE_ADDR, 0);
-	u64 size_cs1 = imx6_mmdc_sdram_size((void *)MX6_MMDC_P0_BASE_ADDR, 1);
-	u64 total    = size_cs0 + size_cs1;
-
-	resource_size_t size = min(total, (u64)IMX6_MAX_SDRAM_SIZE);
+	imx6_barebox_entry(MX6_MMDC_PORT0_BASE_ADDR, boarddata);
+}
 
-	barebox_arm_entry(0x80000000, size, boarddata);
+void __noreturn vf610_barebox_entry(void *boarddata)
+{
+	barebox_arm_entry(VF610_RAM_BASE_ADDR,
+			  vf610_ddrmc_sdram_size(IOMEM(VF610_DDR_BASE_ADDR)),
+			  boarddata);
 }
diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index 14a1cba5a4..6c69c3604a 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -16,6 +16,7 @@
 #include <io.h>
 #include <linux/sizes.h>
 #include <mfd/imx6q-iomuxc-gpr.h>
+#include <mach/clock-imx6.h>
 #include <mach/imx6.h>
 #include <mach/generic.h>
 #include <mach/revision.h>
@@ -44,6 +45,11 @@ static void imx6_init_lowlevel(void)
 	void __iomem *aips2 = (void *)MX6_AIPS2_ON_BASE_ADDR;
 	bool is_imx6q = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6Q;
 	bool is_imx6d = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6D;
+	uint32_t val_480;
+	uint32_t val_528;
+	uint32_t periph_sel_1;
+	uint32_t periph_sel_2;
+	uint32_t reg;
 
 	/*
 	 * Set all MPROTx to be non-bufferable, trusted for R/W,
@@ -68,32 +74,38 @@ static void imx6_init_lowlevel(void)
 	/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
 	 * to make sure PFD is working right, otherwise, PFDs may
 	 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
-	 * workaround in ROM code, as bus clock need it
+	 * workaround in ROM code, as bus clock need it.
+	 * Don't reset PLL2 PFD0 / PLL2 PFD2 if is's used by periph_clk.
 	 */
 	if (is_imx6q || is_imx6d) {
-		writel(BM_ANADIG_PFD_480_PFD3_CLKGATE |
-		       BM_ANADIG_PFD_480_PFD2_CLKGATE |
-		       BM_ANADIG_PFD_480_PFD1_CLKGATE |
-		       BM_ANADIG_PFD_480_PFD0_CLKGATE,
-		       MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_SET);
-		writel(BM_ANADIG_PFD_528_PFD3_CLKGATE |
-		       BM_ANADIG_PFD_528_PFD2_CLKGATE |
-		       BM_ANADIG_PFD_528_PFD1_CLKGATE |
-		       BM_ANADIG_PFD_528_PFD0_CLKGATE,
-		       MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_SET);
-
-		writel(BM_ANADIG_PFD_480_PFD3_CLKGATE |
-		       BM_ANADIG_PFD_480_PFD2_CLKGATE |
-		       BM_ANADIG_PFD_480_PFD1_CLKGATE |
-		       BM_ANADIG_PFD_480_PFD0_CLKGATE,
-		       MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_CLR);
-		writel(BM_ANADIG_PFD_528_PFD3_CLKGATE |
-		       BM_ANADIG_PFD_528_PFD2_CLKGATE |
-		       BM_ANADIG_PFD_528_PFD1_CLKGATE |
-		       BM_ANADIG_PFD_528_PFD0_CLKGATE,
-		       MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_CLR);
-	}
+		val_480 = BM_ANADIG_PFD_480_PFD3_CLKGATE |
+			   BM_ANADIG_PFD_480_PFD2_CLKGATE |
+			   BM_ANADIG_PFD_480_PFD1_CLKGATE |
+			   BM_ANADIG_PFD_480_PFD0_CLKGATE;
+
+		val_528 = BM_ANADIG_PFD_528_PFD3_CLKGATE |
+			   BM_ANADIG_PFD_528_PFD1_CLKGATE;
+
+		reg = readl(MXC_CCM_CBCMR);
+		periph_sel_1 = (reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
+			>> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
+
+		periph_sel_2 = (reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
+			>> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET;
+
+		if ((periph_sel_1 != 0x2) && (periph_sel_2 != 0x2))
+			val_528 |= BM_ANADIG_PFD_528_PFD0_CLKGATE;
+
+		if ((periph_sel_1 != 0x1) && (periph_sel_2 != 0x1)
+		    && (periph_sel_1 != 0x3) && (periph_sel_2 != 0x3))
+			val_528 |= BM_ANADIG_PFD_528_PFD2_CLKGATE;
+
+		writel(val_480, MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_SET);
+		writel(val_528, MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_SET);
 
+		writel(val_480, MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_CLR);
+		writel(val_528, MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_CLR);
+	}
 }
 
 static void imx6_setup_ipu_qos(void)
@@ -147,6 +159,32 @@ static void imx6ul_enet_clk_init(void)
 	writel(val, gprbase + IOMUXC_GPR1);
 }
 
+int imx6_cpu_type(void)
+{
+	static int cpu_type = -1;
+
+	if (!cpu_is_mx6())
+		return 0;
+
+	if (cpu_type < 0)
+		cpu_type = __imx6_cpu_type();
+
+	return cpu_type;
+}
+
+int imx6_cpu_revision(void)
+{
+	static int soc_revision = -1;
+
+	if (!cpu_is_mx6())
+		return 0;
+
+	if (soc_revision < 0)
+		soc_revision = __imx6_cpu_revision();
+
+	return soc_revision;
+}
+
 int imx6_init(void)
 {
 	const char *cputypestr;
@@ -160,16 +198,16 @@ int imx6_init(void)
 
 	switch (imx6_cpu_type()) {
 	case IMX6_CPUTYPE_IMX6Q:
-		if (mx6_silicon_revision >= IMX_CHIP_REV_2_0)
-			cputypestr = "i.MX6 Quad Plus";
-		else
-			cputypestr = "i.MX6 Quad";
+		cputypestr = "i.MX6 Quad";
+		break;
+	case IMX6_CPUTYPE_IMX6QP:
+		cputypestr = "i.MX6 Quad Plus";
 		break;
 	case IMX6_CPUTYPE_IMX6D:
-		if (mx6_silicon_revision >= IMX_CHIP_REV_2_0)
-			cputypestr = "i.MX6 Dual Plus";
-		else
-			cputypestr = "i.MX6 Dual";
+		cputypestr = "i.MX6 Dual";
+		break;
+	case IMX6_CPUTYPE_IMX6DP:
+		cputypestr = "i.MX6 Dual Plus";
 		break;
 	case IMX6_CPUTYPE_IMX6DL:
 		cputypestr = "i.MX6 DualLite";
diff --git a/arch/arm/mach-imx/include/mach/esdctl.h b/arch/arm/mach-imx/include/mach/esdctl.h
index 66dcc8974c..117e2bbad5 100644
--- a/arch/arm/mach-imx/include/mach/esdctl.h
+++ b/arch/arm/mach-imx/include/mach/esdctl.h
@@ -48,6 +48,7 @@
 #define ESDMISC_MDDR_MDIS		0x00000010
 #define ESDMISC_LHD			0x00000020
 #define ESDMISC_SDRAMRDY		0x80000000
+#define ESDMISC_DDR2_8_BANK		BIT(6)
 
 #define	ESDCFGx_tXP_MASK 		0x00600000
 #define ESDCFGx_tXP_1			0x00000000
@@ -137,6 +138,7 @@ void __noreturn imx51_barebox_entry(void *boarddata);
 void __noreturn imx53_barebox_entry(void *boarddata);
 void __noreturn imx6q_barebox_entry(void *boarddata);
 void __noreturn imx6ul_barebox_entry(void *boarddata);
+void __noreturn vf610_barebox_entry(void *boarddata);
 void imx_esdctl_disable(void);
 #endif
 
diff --git a/arch/arm/mach-imx/include/mach/imx6-regs.h b/arch/arm/mach-imx/include/mach/imx6-regs.h
index ac2aa2109f..1ba22b5bc6 100644
--- a/arch/arm/mach-imx/include/mach/imx6-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx6-regs.h
@@ -117,6 +117,8 @@
 
 #define MX6_SATA_BASE_ADDR		0x02200000
 
-#define MX6_MMDC_PORT0_BASE_ADDR	0x10000000
+#define MX6_MMDC_PORT01_BASE_ADDR	0x10000000
+#define MX6_MMDC_PORT0_BASE_ADDR	0x80000000
+
 
 #endif /* __MACH_IMX6_REGS_H */
diff --git a/arch/arm/mach-imx/include/mach/imx6.h b/arch/arm/mach-imx/include/mach/imx6.h
index 6b08e6a521..5701bd480c 100644
--- a/arch/arm/mach-imx/include/mach/imx6.h
+++ b/arch/arm/mach-imx/include/mach/imx6.h
@@ -16,7 +16,9 @@ void __noreturn imx6_pm_stby_poweroff(void);
 #define IMX6_CPUTYPE_IMX6DL	0x261
 #define IMX6_CPUTYPE_IMX6SX	0x462
 #define IMX6_CPUTYPE_IMX6D	0x263
+#define IMX6_CPUTYPE_IMX6DP	0x1263
 #define IMX6_CPUTYPE_IMX6Q	0x463
+#define IMX6_CPUTYPE_IMX6QP	0x1463
 #define IMX6_CPUTYPE_IMX6UL	0x164
 #define IMX6_CPUTYPE_IMX6ULL	0x165
 
@@ -33,36 +35,51 @@ static inline int scu_get_core_count(void)
 	return (ncores & 0x03) + 1;
 }
 
-static inline int __imx6_cpu_type(void)
+#define SI_REV_CPUTYPE(s)	(((s) >> 16) & 0xff)
+#define SI_REV_MAJOR(s)		(((s) >> 8) & 0xf)
+#define SI_REV_MINOR(s)		((s) & 0xf)
+
+static inline uint32_t __imx6_read_si_rev(void)
 {
-	uint32_t val;
-
-	val = readl(MX6_ANATOP_BASE_ADDR + IMX6_ANATOP_SI_REV);
-	val = (val >> 16) & 0xff;
-	/* non-MX6-standard SI_REV reg offset for MX6SL */
-	if (IS_ENABLED(CONFIG_ARCH_IMX6SL) &&
-	    val < (IMX6_CPUTYPE_IMX6S & 0xff)) {
-		uint32_t tmp;
-		tmp = readl(MX6_ANATOP_BASE_ADDR + IMX6SL_ANATOP_SI_REV);
-		tmp = (tmp >> 16) & 0xff;
-		if ((IMX6_CPUTYPE_IMX6SL & 0xff) == tmp)
-			/* intentionally skip scu_get_core_count() for MX6SL */
-			return IMX6_CPUTYPE_IMX6SL;
-	}
+	uint32_t si_rev;
+	uint32_t cpu_type;
+
+	si_rev = readl(MX6_ANATOP_BASE_ADDR + IMX6_ANATOP_SI_REV);
+	cpu_type = SI_REV_CPUTYPE(si_rev);
 
-	val |= scu_get_core_count() << 8;
+	if (cpu_type >= 0x61 && cpu_type <= 0x65)
+		return si_rev;
 
-	return val;
+	/* try non-MX6-standard SI_REV reg offset for MX6SL */
+	si_rev = readl(MX6_ANATOP_BASE_ADDR + IMX6SL_ANATOP_SI_REV);
+	cpu_type = SI_REV_CPUTYPE(si_rev);
+
+	if (si_rev == 0x60)
+		return si_rev;
+
+	return 0;
 }
 
-static inline int imx6_cpu_type(void)
+static inline int __imx6_cpu_type(void)
 {
-	if (!cpu_is_mx6())
-		return 0;
+	uint32_t si_rev = __imx6_read_si_rev();
+	uint32_t cpu_type = SI_REV_CPUTYPE(si_rev);
+
+	/* intentionally skip scu_get_core_count() for MX6SL */
+	if (cpu_type == IMX6_CPUTYPE_IMX6SL)
+		return IMX6_CPUTYPE_IMX6SL;
 
-	return __imx6_cpu_type();
+	cpu_type |= scu_get_core_count() << 8;
+
+	if ((cpu_type == IMX6_CPUTYPE_IMX6D || cpu_type == IMX6_CPUTYPE_IMX6Q) &&
+	    SI_REV_MAJOR(si_rev) >= 1)
+		cpu_type |= 0x1000;
+
+	return cpu_type;
 }
 
+int imx6_cpu_type(void);
+
 #define DEFINE_MX6_CPU_TYPE(str, type)					\
 	static inline int cpu_mx6_is_##str(void)			\
 	{								\
@@ -76,10 +93,19 @@ static inline int imx6_cpu_type(void)
 		return cpu_mx6_is_##str();				\
 	}
 
+/*
+ * Below are defined:
+ *
+ * cpu_is_mx6s(), cpu_is_mx6dl(), cpu_is_mx6q(), cpu_is_mx6qp(), cpu_is_mx6d(),
+ * cpu_is_mx6dp(), cpu_is_mx6sx(), cpu_is_mx6sl(), cpu_is_mx6ul(),
+ * cpu_is_mx6ull()
+ */
 DEFINE_MX6_CPU_TYPE(mx6s, IMX6_CPUTYPE_IMX6S);
 DEFINE_MX6_CPU_TYPE(mx6dl, IMX6_CPUTYPE_IMX6DL);
 DEFINE_MX6_CPU_TYPE(mx6q, IMX6_CPUTYPE_IMX6Q);
+DEFINE_MX6_CPU_TYPE(mx6qp, IMX6_CPUTYPE_IMX6QP);
 DEFINE_MX6_CPU_TYPE(mx6d, IMX6_CPUTYPE_IMX6D);
+DEFINE_MX6_CPU_TYPE(mx6dp, IMX6_CPUTYPE_IMX6DP);
 DEFINE_MX6_CPU_TYPE(mx6sx, IMX6_CPUTYPE_IMX6SX);
 DEFINE_MX6_CPU_TYPE(mx6sl, IMX6_CPUTYPE_IMX6SL);
 DEFINE_MX6_CPU_TYPE(mx6ul, IMX6_CPUTYPE_IMX6UL);
@@ -87,27 +113,15 @@ DEFINE_MX6_CPU_TYPE(mx6ull, IMX6_CPUTYPE_IMX6ULL);
 
 static inline int __imx6_cpu_revision(void)
 {
-	uint32_t rev;
-	uint32_t si_rev_offset = IMX6_ANATOP_SI_REV;
+	uint32_t si_rev = __imx6_read_si_rev();
 	u8 major_part, minor_part;
 
-	if (IS_ENABLED(CONFIG_ARCH_IMX6SL) && cpu_mx6_is_mx6sl())
-		si_rev_offset = IMX6SL_ANATOP_SI_REV;
-
-	rev = readl(MX6_ANATOP_BASE_ADDR + si_rev_offset);
-
-	major_part = (rev >> 8) & 0xf;
-	minor_part = rev & 0xf;
+	major_part = (si_rev >> 8) & 0xf;
+	minor_part = si_rev & 0xf;
 
 	return ((major_part + 1) << 4) | minor_part;
 }
 
-static inline int imx6_cpu_revision(void)
-{
-	if (!cpu_is_mx6())
-		return 0;
-
-	return __imx6_cpu_revision();
-}
+int imx6_cpu_revision(void);
 
 #endif /* __MACH_IMX6_H */
diff --git a/arch/arm/mach-imx/include/mach/vf610-ddrmc.h b/arch/arm/mach-imx/include/mach/vf610-ddrmc.h
new file mode 100644
index 0000000000..07feb036e5
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/vf610-ddrmc.h
@@ -0,0 +1,18 @@
+#ifndef __MACH_DDRMC_H
+#define __MACH_DDRMC_H
+
+#include <mach/vf610-regs.h>
+
+
+#define DDRMC_CR(x)	((x) * 4)
+
+#define DDRMC_CR01_MAX_COL_REG(reg)	(((reg) >>  8) & 0b01111)
+#define DDRMC_CR01_MAX_ROW_REG(reg)	(((reg) >>  0) & 0b11111)
+#define DDRMC_CR73_COL_DIFF(reg)	(((reg) >> 16) & 0b00111)
+#define DDRMC_CR73_ROW_DIFF(reg)	(((reg) >>  8) & 0b00011)
+#define DDRMC_CR73_BANK_DIFF(reg)	(((reg) >>  0) & 0b00011)
+
+#define DDRMC_CR78_REDUC	BIT(8)
+
+
+#endif /* __MACH_MMDC_H */
diff --git a/arch/arm/mach-imx/include/mach/vf610-regs.h b/arch/arm/mach-imx/include/mach/vf610-regs.h
index 8be220b68c..87772ee76d 100644
--- a/arch/arm/mach-imx/include/mach/vf610-regs.h
+++ b/arch/arm/mach-imx/include/mach/vf610-regs.h
@@ -13,6 +13,8 @@
 #define VF610_AIPS0_BASE_ADDR		0x40000000
 #define VF610_AIPS1_BASE_ADDR		0x40080000
 
+#define VF610_RAM_BASE_ADDR		0x80000000
+
 /* AIPS 0 */
 #define VF610_MSCM_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x00001000)
 #define VF610_MSCM_IR_BASE_ADDR		(VF610_AIPS0_BASE_ADDR + 0x00001800)
diff --git a/drivers/clk/imx/clk-imx6.c b/drivers/clk/imx/clk-imx6.c
index d0571bce5e..8c3bb46a48 100644
--- a/drivers/clk/imx/clk-imx6.c
+++ b/drivers/clk/imx/clk-imx6.c
@@ -59,6 +59,11 @@
 static struct clk *clks[IMX6QDL_CLK_END];
 static struct clk_onecell_data clk_data;
 
+static inline int cpu_is_plus(void)
+{
+	return cpu_is_mx6qp() || cpu_is_mx6dp();
+}
+
 static const char *step_sels[] = {
 	"osc",
 	"pll2_pfd2_396m",
@@ -109,6 +114,15 @@ static const char *enfc_sels[]	= {
 	"pll2_pfd2_396m",
 };
 
+static const char *enfc_sels_plus[] = {
+	"pll2_pfd0_352m",
+	"pll2_bus",
+	"pll3_usb_otg",
+	"pll2_pfd2_396m",
+	"pll3_pfd3_454m",
+	"dummy",
+};
+
 static const char *eim_sels[] = {
 	"axi",
 	"pll3_usb_otg",
@@ -404,7 +418,10 @@ static int imx6_ccm_probe(struct device_d *dev)
 	clks[IMX6QDL_CLK_USDHC2_SEL]       = imx_clk_mux("usdhc2_sel",       base + 0x1c, 17, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
 	clks[IMX6QDL_CLK_USDHC3_SEL]       = imx_clk_mux("usdhc3_sel",       base + 0x1c, 18, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
 	clks[IMX6QDL_CLK_USDHC4_SEL]       = imx_clk_mux("usdhc4_sel",       base + 0x1c, 19, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
-	clks[IMX6QDL_CLK_ENFC_SEL]         = imx_clk_mux("enfc_sel",         base + 0x2c, 16, 2, enfc_sels,         ARRAY_SIZE(enfc_sels));
+	if (cpu_is_plus())
+		clks[IMX6QDL_CLK_ENFC_SEL]         = imx_clk_mux("enfc_sel",         base + 0x2c, 16, 2, enfc_sels_plus,    ARRAY_SIZE(enfc_sels_plus));
+	else
+		clks[IMX6QDL_CLK_ENFC_SEL]         = imx_clk_mux("enfc_sel",         base + 0x2c, 16, 2, enfc_sels,         ARRAY_SIZE(enfc_sels));
 	clks[IMX6QDL_CLK_EIM_SEL]          = imx_clk_mux("eim_sel",          base + 0x1c, 27, 2, eim_sels,          ARRAY_SIZE(eim_sels));
 	clks[IMX6QDL_CLK_EIM_SLOW_SEL]     = imx_clk_mux("eim_slow_sel",     base + 0x1c, 29, 2, eim_sels,          ARRAY_SIZE(eim_sels));
 	clks[IMX6QDL_CLK_VDO_AXI_SEL]      = imx_clk_mux("vdo_axi_sel",      base + 0x18, 11, 1, vdo_axi_sels,      ARRAY_SIZE(vdo_axi_sels));
@@ -514,6 +531,13 @@ static int imx6_ccm_probe(struct device_d *dev)
 
 	clk_set_parent(clks[IMX6QDL_CLK_LVDS1_SEL], clks[IMX6QDL_CLK_SATA_REF_100M]);
 
+	/*
+	 * The gpmi needs 100MHz frequency in the EDO/Sync mode,
+	 * We can not get the 100MHz from the pll2_pfd0_352m.
+	 * So choose pll2_pfd2_396m as enfc_sel's parent.
+	 */
+	clk_set_parent(clks[IMX6QDL_CLK_ENFC_SEL], clks[IMX6QDL_CLK_PLL2_PFD2_396M]);
+
 	return 0;
 }
 
diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index 52fb6d39c0..8f87f7b9cb 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -170,9 +170,7 @@ static int lpuart_serial_probe(struct device_d *dev)
 
 	cdev->linux_console_name = "ttyLP";
 
-	lpuart_setup_with_fifo(lpuart->base,
-			       clk_get_rate(lpuart->clk),
-			       15);
+	lpuart_setup(lpuart->base, clk_get_rate(lpuart->clk));
 
 	ret = console_register(cdev);
 	if (!ret) {
diff --git a/images/Makefile.imx b/images/Makefile.imx
index 90da95d4d0..43505b1ff9 100644
--- a/images/Makefile.imx
+++ b/images/Makefile.imx
@@ -440,6 +440,11 @@ CFG_start_phytec_phycore_imx6q_som_nand_1gib.pblx.imximg = $(board)/phytec-som-i
 FILE_barebox-phytec-phycore-imx6q-som-nand-1gib.img = start_phytec_phycore_imx6q_som_nand_1gib.pblx.imximg
 image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-phycore-imx6q-som-nand-1gib.img
 
+pblx-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_phycore_imx6qp_som_nand_1gib
+CFG_start_phytec_phycore_imx6qp_som_nand_1gib.pblx.imximg = $(board)/phytec-som-imx6/flash-header-phytec-pcm058qp-1gib.imxcfg
+FILE_barebox-phytec-phycore-imx6qp-som-nand-1gib.img = start_phytec_phycore_imx6qp_som_nand_1gib.pblx.imximg
+image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-phycore-imx6qp-som-nand-1gib.img
+
 pblx-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_phycore_imx6q_som_emmc_1gib
 CFG_start_phytec_phycore_imx6q_som_emmc_1gib.pblx.imximg = $(board)/phytec-som-imx6/flash-header-phytec-pcm058-1gib.imxcfg
 FILE_barebox-phytec-phycore-imx6q-som-emmc-1gib.img = start_phytec_phycore_imx6q_som_emmc_1gib.pblx.imximg
@@ -455,6 +460,11 @@ CFG_start_phytec_phycore_imx6dl_som_nand_256mb.pblx.imximg = $(board)/phytec-som
 FILE_barebox-phytec-phycore-imx6dl-som-nand-256mb.img = start_phytec_phycore_imx6dl_som_nand_256mb.pblx.imximg
 image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-phycore-imx6dl-som-nand-256mb.img
 
+pblx-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_phycore_imx6dl_som_nand_1gib
+CFG_start_phytec_phycore_imx6dl_som_nand_1gib.pblx.imximg = $(board)/phytec-som-imx6/flash-header-phytec-pcm058dl-1gib-32bit.imxcfg
+FILE_barebox-phytec-phycore-imx6dl-som-nand-1gib.img = start_phytec_phycore_imx6dl_som_nand_1gib.pblx.imximg
+image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-phycore-imx6dl-som-nand-1gib.img
+
 pblx-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_phycore_imx6dl_som_emmc_1gib
 CFG_start_phytec_phycore_imx6dl_som_emmc_1gib.pblx.imximg = $(board)/phytec-som-imx6/flash-header-phytec-pcm058dl-1gib.imxcfg
 FILE_barebox-phytec-phycore-imx6dl-som-emmc-1gib.img = start_phytec_phycore_imx6dl_som_emmc_1gib.pblx.imximg
@@ -490,6 +500,11 @@ CFG_start_imx6dl_eltec_hipercam.pblx.imximg = $(board)/eltec-hipercam/flash-head
 FILE_barebox-eltec-hipercam.img = start_imx6dl_eltec_hipercam.pblx.imximg
 image-$(CONFIG_MACH_ELTEC_HIPERCAM) += barebox-eltec-hipercam.img
 
+pblx-$(CONFIG_MACH_ADVANTECH_ROM_742X) += start_advantech_imx6dl_rom_7421
+CFG_start_advantech_imx6dl_rom_7421.pblx.imximg = $(board)/advantech-mx6/flash-header-advantech-rom-7421.imxcfg
+FILE_barebox-advantech-imx6dl-rom-7421.img = start_advantech_imx6dl_rom_7421.pblx.imximg
+image-$(CONFIG_MACH_ADVANTECH_ROM_742X) += barebox-advantech-imx6dl-rom-7421.img
+
 pblx-$(CONFIG_MACH_WARP7) += start_imx7s_element14_warp7
 CFG_start_imx7s_element14_warp7.pblx.imximg = $(board)/element14-warp7/flash-header-mx7-warp.imxcfg
 FILE_barebox-element14-imx7s-warp7.img = start_imx7s_element14_warp7.pblx.imximg
diff --git a/include/memory.h b/include/memory.h
index 56d16d20c8..73ee7661ef 100644
--- a/include/memory.h
+++ b/include/memory.h
@@ -32,4 +32,12 @@ void memory_bank_find_space(struct memory_bank *bank, resource_size_t *retstart,
 int memory_bank_first_find_space(resource_size_t *retstart,
 				 resource_size_t *retend);
 
+static inline u64 memory_sdram_size(unsigned int cols,
+				    unsigned int rows,
+				    unsigned int banks,
+				    unsigned int width)
+{
+	return (u64)banks * width << (rows + cols);
+}
+
 #endif
diff --git a/include/serial/lpuart.h b/include/serial/lpuart.h
index 917f644a59..a920291dec 100644
--- a/include/serial/lpuart.h
+++ b/include/serial/lpuart.h
@@ -238,22 +238,17 @@ static inline void lpuart_setbrg(void __iomem *base,
 	writeb(bfra, base + UARTCR4);
 }
 
-static inline void lpuart_setup_with_fifo(void __iomem *base,
-					  unsigned int refclock,
-					  unsigned int twfifo)
+static inline void lpuart_setup(void __iomem *base,
+				unsigned int refclock)
 {
 	/* Disable UART */
 	writeb(0, base + UARTCR2);
 	writeb(0, base + UARTMODEM);
 	writeb(0, base + UARTCR1);
 
-	if (twfifo) {
-		writeb(UARTPFIFO_TXFE | UARTPFIFO_RXFE, base + UARTPFIFO);
-		writeb((u8)twfifo, base + UARTTWFIFO);
-	} else {
-		writeb(0, base + UARTPFIFO);
-		writeb(0, base + UARTTWFIFO);
-	}
+	writeb(0, base + UARTPFIFO);
+	writeb(0, base + UARTTWFIFO);
+
 	writeb(1, base + UARTRWFIFO);
 	writeb(UARTCFIFO_RXFLUSH | UARTCFIFO_TXFLUSH, base + UARTCFIFO);
 
@@ -262,12 +257,6 @@ static inline void lpuart_setup_with_fifo(void __iomem *base,
 	writeb(UARTCR2_TE | UARTCR2_RE, base + UARTCR2);
 }
 
-static inline void lpuart_setup(void __iomem *base,
-				unsigned int refclock)
-{
-	lpuart_setup_with_fifo(base, refclock, 0x00);
-}
-
 static inline void lpuart_putc(void __iomem *base, int c)
 {
 	if (!(readb(base + UARTCR2) & UARTCR2_TE))