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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2009-01-30 12:15:36 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2009-01-30 12:20:10 +0100 |
| commit | b3f3ca075d9825f8a4cfe84146ff593a08e95a4b (patch) | |
| tree | dfc6b8dd59a96529fc0bbeecf786740456bd6c98 | |
| parent | 9995a8caf5cbc793c09c3d18feae77362caee3fd (diff) | |
| download | barebox-b3f3ca075d9825f8a4cfe84146ff593a08e95a4b.tar.gz barebox-b3f3ca075d9825f8a4cfe84146ff593a08e95a4b.tar.xz | |
[MX31] Clock Controller module: redefine registers as offsets
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| -rw-r--r-- | arch/arm/mach-imx/speed-imx31.c | 7 | ||||
| -rw-r--r-- | board/pcm037/lowlevel_init.S | 12 | ||||
| -rw-r--r-- | include/asm-arm/arch-imx/imx31-regs.h | 21 |
3 files changed, 21 insertions, 19 deletions
diff --git a/arch/arm/mach-imx/speed-imx31.c b/arch/arm/mach-imx/speed-imx31.c index a626692d3e..c3fef00cbc 100644 --- a/arch/arm/mach-imx/speed-imx31.c +++ b/arch/arm/mach-imx/speed-imx31.c @@ -16,6 +16,7 @@ */ #include <common.h> +#include <asm/io.h> #include <asm/arch/imx-regs.h> #include <asm/arch/clock.h> #include <init.h> @@ -24,12 +25,12 @@ ulong imx_get_mpl_dpdgck_clk(void) { ulong infreq; - if ((__REG(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM) + if ((readl(IMX_CCM_BASE + CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM) infreq = CONFIG_MX31_CLK32 * 1024; else infreq = CONFIG_MX31_HCLK_FREQ; - return imx_decode_pll(__REG(CCM_MPCTL), infreq); + return imx_decode_pll(readl(IMX_CCM_BASE + CCM_MPCTL), infreq); } ulong imx_get_mcu_main_clk(void) @@ -43,7 +44,7 @@ ulong imx_get_mcu_main_clk(void) ulong imx_get_perclk1(void) { u32 freq = imx_get_mcu_main_clk(); - u32 pdr0 = __REG(CCM_PDR0); + u32 pdr0 = readl(IMX_CCM_BASE + CCM_PDR0); freq /= ((pdr0 >> 3) & 0x7) + 1; freq /= ((pdr0 >> 6) & 0x3) + 1; diff --git a/board/pcm037/lowlevel_init.S b/board/pcm037/lowlevel_init.S index ae903a14d8..a0926caa29 100644 --- a/board/pcm037/lowlevel_init.S +++ b/board/pcm037/lowlevel_init.S @@ -46,12 +46,12 @@ board_init_lowlevel: writel(IPU_CONF_DI_EN, IPU_CONF) - writel(0x074B0BF5, CCM_CCMR) + writel(0x074B0BF5, IMX_CCM_BASE + CCM_CCMR) DELAY 0x40000 - writel(0x074B0BF5 | CCMR_MPE, CCM_CCMR) - writel((0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS, CCM_CCMR) + writel(0x074B0BF5 | CCMR_MPE, IMX_CCM_BASE + CCM_CCMR) + writel((0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS, IMX_CCM_BASE + CCM_CCMR) writel(PDR0_CSI_PODF(0xff1) | \ PDR0_PER_PODF(7) | \ @@ -60,10 +60,10 @@ board_init_lowlevel: PDR0_IPG_PODF(1) | \ PDR0_MAX_PODF(3) | \ PDR0_MCU_PODF(0), \ - CCM_PDR0) + IMX_CCM_BASE + CCM_PDR0) - writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0xe) | IMX_PLL_MFI(9) | IMX_PLL_MFN(0xd), CCM_MPCTL) - writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) | IMX_PLL_MFN(1), CCM_SPCTL) + writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0xe) | IMX_PLL_MFI(9) | IMX_PLL_MFN(0xd), IMX_CCM_BASE + CCM_MPCTL) + writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) | IMX_PLL_MFN(1), IMX_CCM_BASE + CCM_SPCTL) /* Skip SDRAM initialization if we run from RAM */ cmp pc, #0x80000000 diff --git a/include/asm-arm/arch-imx/imx31-regs.h b/include/asm-arm/arch-imx/imx31-regs.h index 1cda4dc3cc..fb75abeead 100644 --- a/include/asm-arm/arch-imx/imx31-regs.h +++ b/include/asm-arm/arch-imx/imx31-regs.h @@ -35,6 +35,7 @@ #define IMX_WDT_BASE 0x53FDC000 #define IMX_RTC_BASE 0x53FD8000 #define IMX_TIM1_BASE 0x53F90000 +#define IMX_IIM_BASE 0x5001C000 #define IMX_SDRAM_CS0 0x80000000 #define IMX_SDRAM_CS1 0x90000000 @@ -128,17 +129,17 @@ #define WCR_WDE 0x04 /* - * ???????????? + * Clock Controller Module (CCM) */ -#define CCM_BASE 0x53f80000 -#define CCM_CCMR (CCM_BASE + 0x00) -#define CCM_PDR0 (CCM_BASE + 0x04) -#define CCM_PDR1 (CCM_BASE + 0x08) -#define CCM_RCSR (CCM_BASE + 0x0c) -#define CCM_MPCTL (CCM_BASE + 0x10) -#define CCM_UPCTL (CCM_BASE + 0x10) -#define CCM_SPCTL (CCM_BASE + 0x18) -#define CCM_COSR (CCM_BASE + 0x1C) +#define IMX_CCM_BASE 0x53f80000 +#define CCM_CCMR 0x00 +#define CCM_PDR0 0x04 +#define CCM_PDR1 0x08 +#define CCM_RCSR 0x0c +#define CCM_MPCTL 0x10 +#define CCM_UPCTL 0x10 +#define CCM_SPCTL 0x18 +#define CCM_COSR 0x1C /* * ????????????? |