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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2019-05-03 13:54:29 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-05-10 08:18:25 +0200 |
| commit | f1fa2099a9432a0913d7d087372db1f7287e9226 (patch) | |
| tree | 77d3ec7f7f3f887ae784e4c8235efd700a26ac09 | |
| parent | 163c3a08168f1528da949d167c13511ad407f25b (diff) | |
| download | barebox-f1fa2099a9432a0913d7d087372db1f7287e9226.tar.gz barebox-f1fa2099a9432a0913d7d087372db1f7287e9226.tar.xz | |
ARM: Layerscape: TQMLS1046a: configure qspi divider
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| -rw-r--r-- | arch/arm/boards/tqmls1046a/board.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/boards/tqmls1046a/board.c b/arch/arm/boards/tqmls1046a/board.c index 4fc8e76d65..caf0f7ce38 100644 --- a/arch/arm/boards/tqmls1046a/board.c +++ b/arch/arm/boards/tqmls1046a/board.c @@ -32,6 +32,9 @@ static int tqmls1046a_postcore_init(void) /* Configure iomux for i2c4 */ out_be32(&scfg->rcwpmuxcr0, 0x3300); + /* divide CGA1/CGA2 PLL by 24 to get QSPI interface clock */ + out_be32(&scfg->qspi_cfg, 0x30100000); + return 0; } |