ARM: nitrogen: rename to nitrogen6

Now that the MAX variant of the board is also supported by the
same code, rename the board directory to the more generic nitrogen6.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

14 files changed, 521 insertions, 0 deletions

diff --git a/arch/arm/boards/boundarydevices-nitrogen6/1066mhz_4x128mx16.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/1066mhz_4x128mx16.imxcfg
new file mode 100644
index 0000000000..c5a286b4e0
--- /dev/null
+++ b/arch/arm/boards/boundarydevices-nitrogen6/1066mhz_4x128mx16.imxcfg
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+wm 32 MX6_MMDC_P0_MDPDC			0x00020036
+wm 32 MX6_MMDC_P0_MDCFG0		0x555A7974
+wm 32 MX6_MMDC_P0_MDCFG1		0xDB538F64
+wm 32 MX6_MMDC_P0_MDCFG2		0x01FF00DB
+wm 32 MX6_MMDC_P0_MDRWD			0x000026D2
+wm 32 MX6_MMDC_P0_MDOR			0x005A1023
+wm 32 MX6_MMDC_P0_MDOTC			0x09444040
+wm 32 MX6_MMDC_P0_MDPDC			0x00025576
+wm 32 MX6_MMDC_P0_MDASP			0x00000027
+wm 32 MX6_MMDC_P0_MDCTL			0x831A0000
+wm 32 MX6_MMDC_P0_MDSCR			0x04088032
+wm 32 MX6_MMDC_P0_MDSCR			0x00008033
+wm 32 MX6_MMDC_P0_MDSCR			0x00428031
+wm 32 MX6_MMDC_P0_MDSCR			0x19308030
+wm 32 MX6_MMDC_P0_MDSCR			0x04008040
+wm 32 MX6_MMDC_P0_MPZQHWCTRL		0xA1390003
+wm 32 MX6_MMDC_P1_MPZQHWCTRL		0xA1390003
+wm 32 MX6_MMDC_P0_MDREF			0x00005800
+wm 32 MX6_MMDC_P0_MPODTCTRL		0x00022227
+wm 32 MX6_MMDC_P1_MPODTCTRL		0x00022227
+wm 32 MX6_MMDC_P0_MPDGCTRL0		0x42720306
+wm 32 MX6_MMDC_P0_MPDGCTRL1		0x026F0266
+wm 32 MX6_MMDC_P1_MPDGCTRL0		0x4273030A
+wm 32 MX6_MMDC_P1_MPDGCTRL1		0x02740240
+wm 32 MX6_MMDC_P0_MPRDDLCTL		0x45393B3E
+wm 32 MX6_MMDC_P1_MPRDDLCTL		0x403A3747
+wm 32 MX6_MMDC_P0_MPWRDLCTL		0x40434541
+wm 32 MX6_MMDC_P1_MPWRDLCTL		0x473E4A3B
+wm 32 MX6_MMDC_P0_MPWLDECTRL0		0x0011000E
+wm 32 MX6_MMDC_P0_MPWLDECTRL1		0x000E001B
+wm 32 MX6_MMDC_P1_MPWLDECTRL0		0x00190015
+wm 32 MX6_MMDC_P1_MPWLDECTRL1		0x00070018
+wm 32 MX6_MMDC_P0_MPMUR0		0x00000800
+wm 32 MX6_MMDC_P1_MPMUR0		0x00000800
+wm 32 MX6_MMDC_P0_MDSCR			0x00000000
+wm 32 MX6_MMDC_P0_MAPSR			0x00011006
diff --git a/arch/arm/boards/boundarydevices-nitrogen6/1066mhz_4x256mx16.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/1066mhz_4x256mx16.imxcfg
new file mode 100644
index 0000000000..4d8a715150
--- /dev/null
+++ b/arch/arm/boards/boundarydevices-nitrogen6/1066mhz_4x256mx16.imxcfg
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+wm 32 MX6_MMDC_P0_MDPDC 0x00020036
+wm 32 MX6_MMDC_P0_MDCFG0 0x898E7974
+wm 32 MX6_MMDC_P0_MDCFG1 0xDB538F64
+wm 32 MX6_MMDC_P0_MDCFG2 0x01FF00DB
+wm 32 MX6_MMDC_P0_MDRWD 0x000026D2
+wm 32 MX6_MMDC_P0_MDOR 0x008E1023
+wm 32 MX6_MMDC_P0_MDOTC 0x09444040
+wm 32 MX6_MMDC_P0_MDPDC 0x00025576
+wm 32 MX6_MMDC_P0_MDASP 0x00000047
+wm 32 MX6_MMDC_P0_MDCTL 0x841A0000
+wm 32 MX6_MMDC_P0_MDSCR 0x04088032
+wm 32 MX6_MMDC_P0_MDSCR 0x00008033
+wm 32 MX6_MMDC_P0_MDSCR 0x00428031
+wm 32 MX6_MMDC_P0_MDSCR 0x19308030
+wm 32 MX6_MMDC_P0_MDSCR 0x04008040
+wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xA1390003
+wm 32 MX6_MMDC_P1_MPZQHWCTRL 0xA1390003
+wm 32 MX6_MMDC_P0_MDREF 0x00007800
+wm 32 MX6_MMDC_P0_MPODTCTRL 0x00022227
+wm 32 MX6_MMDC_P1_MPODTCTRL 0x00022227
+wm 32 MX6_MMDC_P0_MPDGCTRL0 0x43040319
+wm 32 MX6_MMDC_P0_MPDGCTRL1 0x03040279
+wm 32 MX6_MMDC_P1_MPDGCTRL0 0x43040321
+wm 32 MX6_MMDC_P1_MPDGCTRL1 0x03030251
+wm 32 MX6_MMDC_P0_MPRDDLCTL 0x4d434248
+wm 32 MX6_MMDC_P1_MPRDDLCTL 0x42413c4d
+wm 32 MX6_MMDC_P0_MPWRDLCTL 0x34424543
+wm 32 MX6_MMDC_P1_MPWRDLCTL 0x49324933
+wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x001a0017
+wm 32 MX6_MMDC_P0_MPWLDECTRL1 0x001F001F
+wm 32 MX6_MMDC_P1_MPWLDECTRL0 0x00170027
+wm 32 MX6_MMDC_P1_MPWLDECTRL1 0x000a001f
+wm 32 MX6_MMDC_P0_MPMUR0 0x00000800
+wm 32 MX6_MMDC_P1_MPMUR0 0x00000800
+wm 32 MX6_MMDC_P0_MDSCR 0x00000000
+wm 32 MX6_MMDC_P0_MAPSR 0x00011006
diff --git a/arch/arm/boards/boundarydevices-nitrogen6/1066mhz_4x512mx16-qp.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/1066mhz_4x512mx16-qp.imxcfg
new file mode 100644
index 0000000000..6409b745d7
--- /dev/null
+++ b/arch/arm/boards/boundarydevices-nitrogen6/1066mhz_4x512mx16-qp.imxcfg
@@ -0,0 +1,67 @@
+/*
+ * Copyright (C) 2016 Boundary Devices
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* NOC setup */
+wm 32 0x00bb0008				0x00000004
+wm 32 0x00bb000c				0x2891E41A
+wm 32 0x00bb0038				0x00000564
+wm 32 0x00bb0014				0x00000040
+wm 32 0x00bb0028				0x00000020
+wm 32 0x00bb002c				0x00000020
+
+/* Disable all MMDC arbitration and reordering controls */
+wm 32 0x021b0400				0x14420000
+
+wm 32 MX6_MMDC_P0_MDPDC			0x00020036
+wm 32 MX6_MMDC_P0_MDSCR			0x00008000
+wm 32 MX6_MMDC_P0_MDCFG0		0x898E79A4
+wm 32 MX6_MMDC_P0_MDCFG1		0xDB538F64
+wm 32 MX6_MMDC_P0_MDCFG2		0x01FF00DD
+wm 32 MX6_MMDC_P0_MDRWD			0x0f9f26d2
+wm 32 MX6_MMDC_P0_MDOR			0x008E1023
+wm 32 MX6_MMDC_P0_MDOTC			0x09444040
+wm 32 MX6_MMDC_P0_MDPDC			0x00025576
+wm 32 MX6_MMDC_P0_MDASP			0x00000047
+wm 32 MX6_MMDC_P0_MDCTL			0xC41A0000
+wm 32 MX6_MMDC_P0_MDSCR			0x04088032
+wm 32 MX6_MMDC_P0_MDSCR			0x0408803a
+wm 32 MX6_MMDC_P0_MDSCR			0x00008033
+wm 32 MX6_MMDC_P0_MDSCR			0x0000803b
+wm 32 MX6_MMDC_P0_MDSCR			0x00428031
+wm 32 MX6_MMDC_P0_MDSCR			0x00428039
+wm 32 MX6_MMDC_P0_MDSCR			0x19308030
+wm 32 MX6_MMDC_P0_MDSCR			0x19308038
+wm 32 MX6_MMDC_P0_MDSCR			0x04008040
+wm 32 MX6_MMDC_P0_MDSCR			0x04008048
+wm 32 MX6_MMDC_P0_MPZQHWCTRL	0xA1390003
+wm 32 MX6_MMDC_P1_MPZQHWCTRL	0xA1390003
+wm 32 MX6_MMDC_P0_MDREF			0x00007800
+wm 32 MX6_MMDC_P0_MPODTCTRL		0x00022227
+wm 32 MX6_MMDC_P1_MPODTCTRL		0x00022227
+wm 32 MX6_MMDC_P0_MPDGCTRL0		0x4327033b
+wm 32 MX6_MMDC_P0_MPDGCTRL1		0x0324031a
+wm 32 MX6_MMDC_P1_MPDGCTRL0		0x43240337
+wm 32 MX6_MMDC_P1_MPDGCTRL1		0x03210269
+wm 32 MX6_MMDC_P0_MPRDDLCTL		0x483c3e4a
+wm 32 MX6_MMDC_P1_MPRDDLCTL		0x423a3848
+wm 32 MX6_MMDC_P0_MPWRDLCTL		0x33363a2c
+wm 32 MX6_MMDC_P1_MPWRDLCTL		0x3e314137
+wm 32 MX6_MMDC_P0_MPWLDECTRL0	0x00200026
+wm 32 MX6_MMDC_P0_MPWLDECTRL1	0x00260021
+wm 32 MX6_MMDC_P1_MPWLDECTRL0	0x00180028
+wm 32 MX6_MMDC_P1_MPWLDECTRL1	0x000f001e
+wm 32 MX6_MMDC_P0_MPMUR0		0x00000800
+wm 32 MX6_MMDC_P1_MPMUR0		0x00000800
+wm 32 MX6_MMDC_P0_MDSCR			0x00000000
+wm 32 MX6_MMDC_P0_MAPSR			0x00011006
diff --git a/arch/arm/boards/boundarydevices-nitrogen6/800mhz_4x128mx16.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/800mhz_4x128mx16.imxcfg
new file mode 100644
index 0000000000..936a2f54bf
--- /dev/null
+++ b/arch/arm/boards/boundarydevices-nitrogen6/800mhz_4x128mx16.imxcfg
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+wm 32 MX6_MMDC_P0_MDPDC 0x0002002D
+wm 32 MX6_MMDC_P0_MDCFG0 0x40435323
+wm 32 MX6_MMDC_P0_MDCFG1 0xB66E8D63
+wm 32 MX6_MMDC_P0_MDCFG2 0x01FF00DB
+wm 32 MX6_MMDC_P0_MDRWD 0x000026D2
+wm 32 MX6_MMDC_P0_MDOR 0x00431023
+wm 32 MX6_MMDC_P0_MDOTC 0x00333030
+wm 32 MX6_MMDC_P0_MDPDC 0x0002556D
+wm 32 MX6_MMDC_P0_MDASP 0x00000027
+wm 32 MX6_MMDC_P0_MDCTL 0x831A0000
+wm 32 MX6_MMDC_P0_MDSCR 0x04008032
+wm 32 MX6_MMDC_P0_MDSCR 0x00008033
+wm 32 MX6_MMDC_P0_MDSCR 0x00048031
+wm 32 MX6_MMDC_P0_MDSCR 0x13208030
+wm 32 MX6_MMDC_P0_MDSCR 0x04008040
+wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xA1390003
+wm 32 MX6_MMDC_P1_MPZQHWCTRL 0xA1390003
+wm 32 MX6_MMDC_P0_MDREF 0x00005800
+wm 32 MX6_MMDC_P0_MPODTCTRL 0x00022227
+wm 32 MX6_MMDC_P1_MPODTCTRL 0x00022227
+wm 32 MX6_MMDC_P0_MPDGCTRL0 0x420F020F
+wm 32 MX6_MMDC_P0_MPDGCTRL1 0x01760175
+wm 32 MX6_MMDC_P1_MPDGCTRL0 0x41640171
+wm 32 MX6_MMDC_P1_MPDGCTRL1 0x015E0160
+wm 32 MX6_MMDC_P0_MPRDDLCTL 0x45464B4A
+wm 32 MX6_MMDC_P1_MPRDDLCTL 0x49484A46
+wm 32 MX6_MMDC_P0_MPWRDLCTL 0x40402E32
+wm 32 MX6_MMDC_P1_MPWRDLCTL 0x3A3A3231
+wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x003A003A
+wm 32 MX6_MMDC_P0_MPWLDECTRL1 0x0030002F
+wm 32 MX6_MMDC_P1_MPWLDECTRL0 0x002F0038
+wm 32 MX6_MMDC_P1_MPWLDECTRL1 0x00270039
+wm 32 MX6_MMDC_P0_MPMUR0 0x00000800
+wm 32 MX6_MMDC_P1_MPMUR0 0x00000800
+wm 32 MX6_MMDC_P0_MDSCR 0x00000000
+wm 32 MX6_MMDC_P0_MAPSR 0x00011006
diff --git a/arch/arm/boards/boundarydevices-nitrogen6/800mhz_4x256mx16.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/800mhz_4x256mx16.imxcfg
new file mode 100644
index 0000000000..09c855544d
--- /dev/null
+++ b/arch/arm/boards/boundarydevices-nitrogen6/800mhz_4x256mx16.imxcfg
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+wm 32 MX6_MMDC_P0_MDPDC 0x0002002D
+wm 32 MX6_MMDC_P0_MDCFG0 0x696C5323
+wm 32 MX6_MMDC_P0_MDCFG1 0xB66E8D63
+wm 32 MX6_MMDC_P0_MDCFG2 0x01FF00DB
+wm 32 MX6_MMDC_P0_MDRWD 0x000026D2
+wm 32 MX6_MMDC_P0_MDOR 0x006C1023
+wm 32 MX6_MMDC_P0_MDOTC 0x00333030
+wm 32 MX6_MMDC_P0_MDPDC 0x0002556D
+wm 32 MX6_MMDC_P0_MDASP 0x00000047
+wm 32 MX6_MMDC_P0_MDCTL 0x841A0000
+wm 32 MX6_MMDC_P0_MDSCR 0x04008032
+wm 32 MX6_MMDC_P0_MDSCR 0x00008033
+wm 32 MX6_MMDC_P0_MDSCR 0x00048031
+wm 32 MX6_MMDC_P0_MDSCR 0x13208030
+wm 32 MX6_MMDC_P0_MDSCR 0x04008040
+wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xA1390003
+wm 32 MX6_MMDC_P1_MPZQHWCTRL 0xA1390003
+wm 32 MX6_MMDC_P0_MDREF 0x00007800
+wm 32 MX6_MMDC_P0_MPODTCTRL 0x00022227
+wm 32 MX6_MMDC_P1_MPODTCTRL 0x00022227
+wm 32 MX6_MMDC_P0_MPDGCTRL0 0x42350231
+wm 32 MX6_MMDC_P0_MPDGCTRL1 0x021A0218
+wm 32 MX6_MMDC_P1_MPDGCTRL0 0x42350231
+wm 32 MX6_MMDC_P1_MPDGCTRL1 0x021A0218
+wm 32 MX6_MMDC_P0_MPRDDLCTL 0x4B4B4E49
+wm 32 MX6_MMDC_P1_MPRDDLCTL 0x4B4B4E49
+wm 32 MX6_MMDC_P0_MPWRDLCTL 0x3F3F3035
+wm 32 MX6_MMDC_P1_MPWRDLCTL 0x3F3F3035
+wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x0040003C
+wm 32 MX6_MMDC_P0_MPWLDECTRL1 0x0032003E
+wm 32 MX6_MMDC_P1_MPWLDECTRL0 0x0040003C
+wm 32 MX6_MMDC_P1_MPWLDECTRL1 0x0032003E
+wm 32 MX6_MMDC_P0_MPMUR0 0x00000800
+wm 32 MX6_MMDC_P1_MPMUR0 0x00000800
+wm 32 MX6_MMDC_P0_MDSCR 0x00000000
+wm 32 MX6_MMDC_P0_MAPSR 0x00011006
diff --git a/arch/arm/boards/boundarydevices-nitrogen6/Makefile b/arch/arm/boards/boundarydevices-nitrogen6/Makefile
new file mode 100644
index 0000000000..0ec04ce898
--- /dev/null
+++ b/arch/arm/boards/boundarydevices-nitrogen6/Makefile
@@ -0,0 +1,2 @@
+obj-y += board.o 
+lwl-y += lowlevel.o
diff --git a/arch/arm/boards/boundarydevices-nitrogen6/board.c b/arch/arm/boards/boundarydevices-nitrogen6/board.c
new file mode 100644
index 0000000000..d9514d9d48
--- /dev/null
+++ b/arch/arm/boards/boundarydevices-nitrogen6/board.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2014 Lucas Stach, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <environment.h>
+#include <mach/bbu.h>
+#include <linux/phy.h>
+#include <linux/micrel_phy.h>
+#include <mach/imx6.h>
+
+static int nitrogen6x_devices_init(void)
+{
+	if (!of_machine_is_compatible("boundary,imx6dl-nitrogen6x") &&
+	    !of_machine_is_compatible("boundary,imx6q-nitrogen6x") &&
+	    !of_machine_is_compatible("boundary,imx6qp-nitrogen6_max"))
+		return 0;
+
+	imx6_bbu_internal_spi_i2c_register_handler("spiflash", "/dev/m25p0.barebox",
+			BBU_HANDLER_FLAG_DEFAULT);
+
+	if (of_machine_is_compatible("boundary,imx6qp-nitrogen6_max"))
+		barebox_set_hostname("nitrogen6max");
+	else
+		barebox_set_hostname("nitrogen6x");
+
+	return 0;
+}
+device_initcall(nitrogen6x_devices_init);
+
+static int ksz9021rn_phy_fixup(struct phy_device *dev)
+{
+	phy_write(dev, 0x09, 0x0f00);
+
+	/* do same as linux kernel */
+	/* min rx data delay */
+	phy_write(dev, 0x0b, 0x8105);
+	phy_write(dev, 0x0c, 0x0000);
+
+	/* max rx/tx clock delay, min rx/tx control delay */
+	phy_write(dev, 0x0b, 0x8104);
+	phy_write(dev, 0x0c, 0xf0f0);
+	phy_write(dev, 0x0b, 0x104);
+
+	return 0;
+}
+
+static int nitrogen6x_coredevices_init(void)
+{
+	if (!of_machine_is_compatible("boundary,imx6dl-nitrogen6x") &&
+	    !of_machine_is_compatible("boundary,imx6q-nitrogen6x") &&
+	    !of_machine_is_compatible("boundary,imx6qp-nitrogen6_max"))
+		return 0;
+
+	phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
+					   ksz9021rn_phy_fixup);
+	return 0;
+}
+coredevice_initcall(nitrogen6x_coredevices_init);
diff --git a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-1g.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-1g.imxcfg
new file mode 100644
index 0000000000..0773f4d276
--- /dev/null
+++ b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-1g.imxcfg
@@ -0,0 +1,10 @@
+soc imx6
+loadaddr 0x20000000
+dcdofs 0x400
+
+#include <mach/imx6-ddr-regs.h>
+#include <mach/imx6dl-ddr-regs.h>
+#include <mach/imx6-ccm-regs.h>
+
+#include "ram-base.imxcfg"
+#include "800mhz_4x128mx16.imxcfg"
diff --git a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-2g.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-2g.imxcfg
new file mode 100644
index 0000000000..6622c517fa
--- /dev/null
+++ b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-2g.imxcfg
@@ -0,0 +1,10 @@
+soc imx6
+loadaddr 0x20000000
+dcdofs 0x400
+
+#include <mach/imx6-ddr-regs.h>
+#include <mach/imx6dl-ddr-regs.h>
+#include <mach/imx6-ccm-regs.h>
+
+#include "ram-base.imxcfg"
+#include "800mhz_4x256mx16.imxcfg"
diff --git a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-1g.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-1g.imxcfg
new file mode 100644
index 0000000000..bd4134f8a9
--- /dev/null
+++ b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-1g.imxcfg
@@ -0,0 +1,10 @@
+soc imx6
+loadaddr 0x20000000
+dcdofs 0x400
+
+#include <mach/imx6-ddr-regs.h>
+#include <mach/imx6q-ddr-regs.h>
+#include <mach/imx6-ccm-regs.h>
+
+#include "ram-base.imxcfg"
+#include "1066mhz_4x128mx16.imxcfg"
diff --git a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-2g.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-2g.imxcfg
new file mode 100644
index 0000000000..89aa21c300
--- /dev/null
+++ b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-2g.imxcfg
@@ -0,0 +1,10 @@
+soc imx6
+loadaddr 0x20000000
+dcdofs 0x400
+
+#include <mach/imx6-ddr-regs.h>
+#include <mach/imx6q-ddr-regs.h>
+#include <mach/imx6-ccm-regs.h>
+
+#include "ram-base.imxcfg"
+#include "1066mhz_4x256mx16.imxcfg"
diff --git a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6qp-max.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6qp-max.imxcfg
new file mode 100644
index 0000000000..66f0e1a860
--- /dev/null
+++ b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6qp-max.imxcfg
@@ -0,0 +1,10 @@
+soc imx6
+loadaddr 0x20000000
+dcdofs 0x400
+
+#include <mach/imx6-ddr-regs.h>
+#include <mach/imx6q-ddr-regs.h>
+#include <mach/imx6-ccm-regs.h>
+
+#include "ram-base.imxcfg"
+#include "1066mhz_4x512mx16-qp.imxcfg"
diff --git a/arch/arm/boards/boundarydevices-nitrogen6/lowlevel.c b/arch/arm/boards/boundarydevices-nitrogen6/lowlevel.c
new file mode 100644
index 0000000000..bee70a5af4
--- /dev/null
+++ b/arch/arm/boards/boundarydevices-nitrogen6/lowlevel.c
@@ -0,0 +1,65 @@
+#include <common.h>
+#include <mach/generic.h>
+#include <mach/esdctl.h>
+#include <asm/barebox-arm.h>
+
+extern char __dtb_imx6q_nitrogen6x_start[];
+
+ENTRY_FUNCTION(start_imx6q_nitrogen6x_1g, r0, r1, r2)
+{
+	void *fdt;
+
+	imx6_cpu_lowlevel_init();
+
+	fdt = __dtb_imx6q_nitrogen6x_start - get_runtime_offset();
+
+	imx6q_barebox_entry(fdt);
+}
+
+ENTRY_FUNCTION(start_imx6q_nitrogen6x_2g, r0, r1, r2)
+{
+	void *fdt;
+
+	imx6_cpu_lowlevel_init();
+
+	fdt = __dtb_imx6q_nitrogen6x_start - get_runtime_offset();
+
+	imx6q_barebox_entry(fdt);
+}
+
+extern char __dtb_imx6dl_nitrogen6x_start[];
+
+ENTRY_FUNCTION(start_imx6dl_nitrogen6x_1g, r0, r1, r2)
+{
+	void *fdt;
+
+	imx6_cpu_lowlevel_init();
+
+	fdt = __dtb_imx6dl_nitrogen6x_start - get_runtime_offset();
+
+	imx6q_barebox_entry(fdt);
+}
+
+ENTRY_FUNCTION(start_imx6dl_nitrogen6x_2g, r0, r1, r2)
+{
+	void *fdt;
+
+	imx6_cpu_lowlevel_init();
+
+	fdt = __dtb_imx6dl_nitrogen6x_start - get_runtime_offset();
+
+	imx6q_barebox_entry(fdt);
+}
+
+extern char __dtb_imx6qp_nitrogen6_max_start[];
+
+ENTRY_FUNCTION(start_imx6qp_nitrogen6_max, r0, r1, r2)
+{
+	void *fdt;
+
+	imx6_cpu_lowlevel_init();
+
+	fdt = __dtb_imx6qp_nitrogen6_max_start - get_runtime_offset();
+
+	imx6q_barebox_entry(fdt);
+}
diff --git a/arch/arm/boards/boundarydevices-nitrogen6/ram-base.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/ram-base.imxcfg
new file mode 100644
index 0000000000..5d675883fd
--- /dev/null
+++ b/arch/arm/boards/boundarydevices-nitrogen6/ram-base.imxcfg
@@ -0,0 +1,67 @@
+wm 32 MX6_IOM_DRAM_SDQS0		0x00000030
+wm 32 MX6_IOM_DRAM_SDQS1		0x00000030
+wm 32 MX6_IOM_DRAM_SDQS2		0x00000030
+wm 32 MX6_IOM_DRAM_SDQS3		0x00000030
+wm 32 MX6_IOM_DRAM_SDQS4		0x00000030
+wm 32 MX6_IOM_DRAM_SDQS5		0x00000030
+wm 32 MX6_IOM_DRAM_SDQS6		0x00000030
+wm 32 MX6_IOM_DRAM_SDQS7		0x00000030
+
+wm 32 MX6_IOM_GRP_B0DS			0x00000030
+wm 32 MX6_IOM_GRP_B1DS			0x00000030
+wm 32 MX6_IOM_GRP_B2DS			0x00000030
+wm 32 MX6_IOM_GRP_B3DS			0x00000030
+wm 32 MX6_IOM_GRP_B4DS			0x00000030
+wm 32 MX6_IOM_GRP_B5DS			0x00000030
+wm 32 MX6_IOM_GRP_B6DS			0x00000030
+wm 32 MX6_IOM_GRP_B7DS			0x00000030
+wm 32 MX6_IOM_GRP_ADDDS			0x00000030
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+wm 32 MX6_IOM_GRP_CTLDS			0x00000030
+
+wm 32 MX6_IOM_DRAM_DQM0			0x00020030
+wm 32 MX6_IOM_DRAM_DQM1			0x00020030
+wm 32 MX6_IOM_DRAM_DQM2			0x00020030
+wm 32 MX6_IOM_DRAM_DQM3			0x00020030
+wm 32 MX6_IOM_DRAM_DQM4			0x00020030
+wm 32 MX6_IOM_DRAM_DQM5			0x00020030
+wm 32 MX6_IOM_DRAM_DQM6			0x00020030
+wm 32 MX6_IOM_DRAM_DQM7			0x00020030
+
+wm 32 MX6_IOM_DRAM_CAS			0x00020030
+wm 32 MX6_IOM_DRAM_RAS			0x00020030
+wm 32 MX6_IOM_DRAM_SDCLK_0		0x00020030
+wm 32 MX6_IOM_DRAM_SDCLK_1		0x00020030
+
+wm 32 MX6_IOM_DRAM_RESET		0x00020030
+wm 32 MX6_IOM_DRAM_SDCKE0		0x00003000
+wm 32 MX6_IOM_DRAM_SDCKE1		0x00003000
+
+wm 32 MX6_IOM_DRAM_SDODT0		0x00003030
+wm 32 MX6_IOM_DRAM_SDODT1		0x00003030
+
+/* (differential input) */
+wm 32 MX6_IOM_DDRMODE_CTL		0x00020000
+/* (differential input) */
+wm 32 MX6_IOM_GRP_DDRMODE		0x00020000
+/* disable ddr pullups */
+wm 32 MX6_IOM_GRP_DDRPKE		0x00000000
+wm 32 MX6_IOM_DRAM_SDBA2		0x00000000
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+wm 32 MX6_IOM_GRP_DDR_TYPE		0x000C0000
+
+/* Read data DQ Byte0-3 delay */
+wm 32 MX6_MMDC_P0_MPRDDQBY0DL	0x33333333
+wm 32 MX6_MMDC_P0_MPRDDQBY1DL	0x33333333
+wm 32 MX6_MMDC_P0_MPRDDQBY2DL	0x33333333
+wm 32 MX6_MMDC_P0_MPRDDQBY3DL	0x33333333
+wm 32 MX6_MMDC_P1_MPRDDQBY0DL	0x33333333
+wm 32 MX6_MMDC_P1_MPRDDQBY1DL	0x33333333
+wm 32 MX6_MMDC_P1_MPRDDQBY2DL	0x33333333
+wm 32 MX6_MMDC_P1_MPRDDQBY3DL	0x33333333
+
+/* MDMISC	mirroring-off	interleaved (row/bank/col) */
+wm 32 MX6_MMDC_P0_MDMISC		0x00001740
+
+/* MDSCR	con_req */
+wm 32 MX6_MMDC_P0_MDSCR			0x00008000