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author | Alexander Shiyan <shc_work@mail.ru> | 2012-11-02 13:17:16 +0400 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2012-11-02 11:24:58 +0100 |
commit | 27794047ff7e6744ce71875cae6d1747ce1346c0 (patch) | |
tree | e1246ea6af35eb56382a4a74f6c76db39ef5d07b /arch/arm/boards/clep7212/lowlevel.c | |
parent | bedf7dfce5bcf728937b9569ac0d038267f588f3 (diff) | |
download | barebox-27794047ff7e6744ce71875cae6d1747ce1346c0.tar.gz barebox-27794047ff7e6744ce71875cae6d1747ce1346c0.tar.xz |
ARM: clps711x: Add generic board support (CLEP7212)
This patch adds generic board support (CLEP7212, Linux ARM ID=91)
for CLPS711X-target.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/boards/clep7212/lowlevel.c')
-rw-r--r-- | arch/arm/boards/clep7212/lowlevel.c | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/arch/arm/boards/clep7212/lowlevel.c b/arch/arm/boards/clep7212/lowlevel.c new file mode 100644 index 0000000000..9b7e2410f3 --- /dev/null +++ b/arch/arm/boards/clep7212/lowlevel.c @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <common.h> +#include <init.h> + +#include <asm/io.h> +#include <asm/barebox-arm.h> +#include <asm/barebox-arm-head.h> + +#include <mach/clps711x.h> + +#define MAIN_CLOCK 3686400 +#define CPU_SPEED 92160000 +#define BUS_SPEED (CPU_SPEED / 2) + +#define PLL_VALUE (((CPU_SPEED * 2) / MAIN_CLOCK) << 24) +#define SDRAM_REFRESH_RATE (64 * (BUS_SPEED / (8192 * 1000))) + +void __naked __bare_init reset(void) +{ + u32 tmp; + + common_reset(); + + /* Setup base clock */ + writel(SYSCON3_CLKCTL0 | SYSCON3_CLKCTL1, SYSCON3); + asm("nop"); + + /* Setup PLL */ + writel(PLL_VALUE, PLLW); + asm("nop"); + + /* CLKEN select, SDRAM width=32 */ + writel(SYSCON2_CLKENSL, SYSCON2); + + /* Enable SDQM pins */ + tmp = readl(SYSCON3); + tmp &= ~SYSCON3_ENPD67; + writel(tmp, SYSCON3); + + /* Setup Refresh Rate (64ms 8K Blocks) */ + writel(SDRAM_REFRESH_RATE, SDRFPR); + + /* Setup SDRAM (32MB, 16Bit*2, CAS=3) */ + writel(SDCONF_CASLAT_3 | SDCONF_SIZE_256 | SDCONF_WIDTH_16 | + SDCONF_CLKCTL | SDCONF_ACTIVE, SDCONF); + + board_init_lowlevel_return(); +} |