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| author | Alexander Shiyan <shc_work@mail.ru> | 2013-02-13 15:41:37 +0400 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2013-02-13 18:34:25 +0100 |
| commit | 86fda721e300ab63a49602d2b2d5db199ad237b1 (patch) | |
| tree | 81fc1a9974cd11a362d1fa5fa7591fe29f189587 /arch/arm/boards/clep7212 | |
| parent | c1a4087f5d8113d3612c574c9c35bbb2f5c98078 (diff) | |
| download | barebox-86fda721e300ab63a49602d2b2d5db199ad237b1.tar.gz barebox-86fda721e300ab63a49602d2b2d5db199ad237b1.tar.xz | |
ARM: clps711x: Move basic lowlevel initialization in common CLPS711X location
One lowlevel initialization will be used on any CLPS711X-target,
so move it in the common location.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/boards/clep7212')
| -rw-r--r-- | arch/arm/boards/clep7212/lowlevel.c | 48 |
1 files changed, 1 insertions, 47 deletions
diff --git a/arch/arm/boards/clep7212/lowlevel.c b/arch/arm/boards/clep7212/lowlevel.c index fcee5bf204..b7d6d1dd00 100644 --- a/arch/arm/boards/clep7212/lowlevel.c +++ b/arch/arm/boards/clep7212/lowlevel.c @@ -9,60 +9,14 @@ #include <common.h> #include <init.h> -#include <sizes.h> -#include <asm/io.h> -#include <asm/barebox-arm.h> #include <asm/barebox-arm-head.h> #include <mach/clps711x.h> void __naked __bare_init barebox_arm_reset_vector(void) { - const u32 pllmult = 50; - u32 cpu, bus; - arm_cpu_lowlevel_init(); - /* Setup base clocking, Enable SDQM pins */ - writel(SYSCON3_CLKCTL0 | SYSCON3_CLKCTL1, SYSCON3); - asm("nop"); - - /* Check if we running from external 13 MHz clock */ - if (!(readl(SYSFLG2) & SYSFLG2_CKMODE)) { - /* Setup PLL */ - writel(pllmult << 24, PLLW); - asm("nop"); - - /* Check for old CPUs without PLL */ - if ((readl(PLLR) >> 24) != pllmult) - cpu = 73728000; - else - cpu = pllmult * 3686400; - - if (cpu >= 36864000) - bus = cpu /2; - else - bus = 36864000 / 2; - } else - bus = 13000000; - - /* CLKEN select, SDRAM width=32 */ - writel(SYSCON2_CLKENSL, SYSCON2); - - /* Setup SDRAM params (64MB, 16Bit*2, CAS=3) */ - writel(SDCONF_CASLAT_3 | SDCONF_SIZE_256 | SDCONF_WIDTH_16 | - SDCONF_CLKCTL | SDCONF_ACTIVE, SDCONF); - - /* Setup Refresh Rate (64ms 8K Blocks) */ - writel((64 * bus) / (8192 * 1000), SDRFPR); - - /* Disable UART, IrDa, LCD */ - writel(0, SYSCON1); - /* Disable PWM */ - writew(0, PMPCON); - /* Disable LED flasher */ - writew(0, LEDFLSH); - - barebox_arm_entry(SDRAM0_BASE, SZ_8M, 0); + clps711x_barebox_entry(); } |