summaryrefslogtreecommitdiffstats
path: root/arch/arm/boards/efika-mx-smartbook
diff options
context:
space:
mode:
authorSascha Hauer <s.hauer@pengutronix.de>2013-06-12 11:33:43 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2013-06-18 09:02:13 +0200
commitc65f734d4ba898058225baba699786a7cef0d371 (patch)
tree3e66faa34585d2fc41a97a9437c45e8d483eea95 /arch/arm/boards/efika-mx-smartbook
parent6ce708895cd141a428aab34c2615e22756fb82e5 (diff)
downloadbarebox-c65f734d4ba898058225baba699786a7cef0d371.tar.gz
barebox-c65f734d4ba898058225baba699786a7cef0d371.tar.xz
ARM: i.MX51 efikasb: call imx51_lowlevel_init from lowlevel init
Adjusting the PLLs when MMU/caching is already enabled seems to be unstable on the Smartbook, so do it during early init. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/boards/efika-mx-smartbook')
-rw-r--r--arch/arm/boards/efika-mx-smartbook/board.c5
-rw-r--r--arch/arm/boards/efika-mx-smartbook/lowlevel.c3
2 files changed, 3 insertions, 5 deletions
diff --git a/arch/arm/boards/efika-mx-smartbook/board.c b/arch/arm/boards/efika-mx-smartbook/board.c
index e9b6062872..98f9dcd572 100644
--- a/arch/arm/boards/efika-mx-smartbook/board.c
+++ b/arch/arm/boards/efika-mx-smartbook/board.c
@@ -270,11 +270,6 @@ static void efikamx_power_init(void)
mc13xxx_reg_write(mc, MC13892_REG_SW_2, val);
udelay(50);
- /* Raise the core frequency to 800MHz */
- console_flush();
- imx51_init_lowlevel(800);
- clock_notifier_call_chain();
-
/* Set switchers in Auto in NORMAL mode & STANDBY mode */
/* Setup the switcher mode for SW1 & SW2*/
mc13xxx_reg_read(mc, MC13892_REG_SW_4, &val);
diff --git a/arch/arm/boards/efika-mx-smartbook/lowlevel.c b/arch/arm/boards/efika-mx-smartbook/lowlevel.c
index 3e6a0ee328..11abc938ad 100644
--- a/arch/arm/boards/efika-mx-smartbook/lowlevel.c
+++ b/arch/arm/boards/efika-mx-smartbook/lowlevel.c
@@ -1,9 +1,12 @@
#include <common.h>
#include <mach/esdctl.h>
#include <asm/barebox-arm-head.h>
+#include <mach/imx5.h>
void __naked barebox_arm_reset_vector(void)
{
arm_cpu_lowlevel_init();
+ arm_setup_stack(0x20000000 - 16);
+ imx51_init_lowlevel(800);
imx51_barebox_entry(0);
}