ARM: i.MX: Remove old boards

This removes a bunch of old boards that nobody showed interest in
for a long time:

Freescale boards
================
MACH_IMX21ADS
MACH_IMX27ADS
MACH_FREESCALE_MX25_3STACK
MACH_FREESCALE_MX35_3STACK
MACH_FREESCALE_MX53_SMD

Eukrea boards
=============
MACH_EUKREA_CPUIMX25
MACH_EUKREA_CPUIMX27
MACH_EUKREA_CPUIMX35
MACH_EUKREA_CPUIMX51SD

Garz+Fricke boards
==================
MACH_NESO
MACH_GUF_CUPID

Phytec boards
=============
MACH_PCM037
MACH_PCM043

Amazon boards
=============
MACH_KINDLE3

All these boards have not been converted to device tree nor do they
support multi-image generation. As they are becoming a maintenance
burden remove them now.

A board can always be added back once it is ported to support the
recent barebox interfaces.

Link: https://lore.barebox.org/20230302105225.943524-2-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

6 files changed, 0 insertions, 589 deletions

diff --git a/arch/arm/boards/eukrea_cpuimx35/Makefile b/arch/arm/boards/eukrea_cpuimx35/Makefile
deleted file mode 100644
index f1a8e7a5d6..0000000000
--- a/arch/arm/boards/eukrea_cpuimx35/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2007 Juergen Beisert <jbe@pengutronix.de>
-
-obj-y					+= eukrea_cpuimx35.o
-lwl-y					+= lowlevel.o
-bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-eukrea_cpuimx35
diff --git a/arch/arm/boards/eukrea_cpuimx35/defaultenv-eukrea_cpuimx35/bin/init_board b/arch/arm/boards/eukrea_cpuimx35/defaultenv-eukrea_cpuimx35/bin/init_board
deleted file mode 100644
index 2a07a8425a..0000000000
--- a/arch/arm/boards/eukrea_cpuimx35/defaultenv-eukrea_cpuimx35/bin/init_board
+++ /dev/null
@@ -1,41 +0,0 @@
-#!/bin/sh
-
-if [ -f /env/logo.bmp ]; then
-	splash /env/logo.bmp
-	fb0.enable=1
-	gpio_set_value 1 1
-elif [ -f /env/logo.bmp.lzo ]; then
-	uncompress /env/logo.bmp.lzo /logo.bmp
-	splash /logo.bmp
-	fb0.enable=1
-	gpio_set_value 1 1
-fi
-
-gpio_get_value 89
-if [ $? -eq 0 ]; then
-	gpio_set_value 93 0
-	usbserial
-	timeout -s -a 2
-	gpio_get_value 89
-	if [ $? -eq 0 ]; then
-		usbserial -d
-		dfu -V 0x1234 -P 0x1234 /dev/nand0.barebox.bb(barebox)sr,/dev/nand0.kernel.bb(kernel)r,/dev/nand0.root.bb(root)r
-		gpio_get_value 89
-		if [ $? -eq 0 ]; then
-			usbserial
-			autoboot_timeout=60
-		else
-			reset
-		fi
-	else
-		autoboot_timeout=28
-	fi
-fi
-
-if [ -z $eth0.ethaddr ]; then
-	while [ -z $eth0.ethaddr ]; do
-		readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr
-	done
-	echo -a /env/config "eth0.ethaddr=$eth0.ethaddr"
-	saveenv
-fi
diff --git a/arch/arm/boards/eukrea_cpuimx35/defaultenv-eukrea_cpuimx35/config b/arch/arm/boards/eukrea_cpuimx35/defaultenv-eukrea_cpuimx35/config
deleted file mode 100644
index 05c4391d35..0000000000
--- a/arch/arm/boards/eukrea_cpuimx35/defaultenv-eukrea_cpuimx35/config
+++ /dev/null
@@ -1,47 +0,0 @@
-#!/bin/sh
-
-# otg port mode : can be 'host' or 'device'
-otg_mode="device"
-# video : can be CMO-QVGA, URT-WVGA, DVI-VGA or DVI-SVGA
-video="CMO-QVGA"
-
-# use 'dhcp' to do dhcp in barebox and in kernel
-# use 'none' if you want to skip kernel ip autoconfiguration
-ip=none
-
-# or set your networking parameters here
-#eth0.ipaddr=a.b.c.d
-#eth0.netmask=a.b.c.d
-#eth0.gateway=a.b.c.d
-#eth0.serverip=a.b.c.d
-
-# can be either 'nfs', 'tftp' or 'nand'
-kernel_loc=nand
-# can be either 'net', 'nand' or 'initrd'
-rootfs_loc=nand
-
-# rootfs
-rootfs_type=ubifs
-rootfsimage=${global.hostname}/rootfs.$rootfs_type
-
-# kernel
-kernelimage=${global.hostname}/uImage-${global.hostname}.bin
-
-# barebox and it's env
-bareboximage=${global.hostname}/barebox-${global.hostname}.bin
-bareboxenvimage=${global.hostname}/bareboxenv-${global.hostname}.bin
-
-nfsroot="$eth0.serverip:/srv/nfs/${global.hostname}"
-
-autoboot_timeout=1
-
-bootargs="console=ttymxc0,115200 otg_mode=$otg_mode video=mx3fb:$video"
-
-nand_parts="256k(barebox)ro,128k(bareboxenv),3M(kernel),-(root)"
-rootfs_mtdblock_nand=3
-nand_device="mxc_nand"
-ubiroot="${global.hostname}-rootfs"
-device_type="nand"
-
-# set a fancy prompt (if support is compiled in)
-PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "
diff --git a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
deleted file mode 100644
index 2506ae8b06..0000000000
--- a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
+++ /dev/null
@@ -1,346 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-/*
- * Copyright (C) 2007 Sascha Hauer, Pengutronix
- *               2009 Marc Kleine-Budde, Pengutronix
- * (c) 2010 Eukrea Electromatique, Eric Bénard <eric@eukrea.com>
- *
- * Derived from:
- *
- * * mx35_3stack.c - board file for uboot-v1
- *   Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *   (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <environment.h>
-#include <errno.h>
-#include <fcntl.h>
-#include <platform_data/eth-fec.h>
-#include <fs.h>
-#include <init.h>
-#include <nand.h>
-#include <net.h>
-#include <gpio.h>
-#include <envfs.h>
-
-#include <asm/armlinux.h>
-#include <io.h>
-#include <generated/mach-types.h>
-#include <asm/mmu.h>
-
-#include <mach/imx-nand.h>
-#include <mach/imx35-regs.h>
-#include <mach/iomux-mx35.h>
-#include <mach/iomux-v3.h>
-#include <mach/imx-ipu-fb.h>
-#include <mach/imx-pll.h>
-#include <i2c/i2c.h>
-#include <usb/fsl_usb2.h>
-#include <mach/usb.h>
-#include <mach/devices-imx35.h>
-
-static struct fec_platform_data fec_info = {
-	.xcv_type	= PHY_INTERFACE_MODE_MII,
-	.phy_addr	= 0,
-};
-
-struct imx_nand_platform_data nand_info = {
-	.width		= 1,
-	.hw_ecc		= 1,
-	.flash_bbt	= 1,
-};
-
-static struct fb_videomode imxfb_mode = {
-	.name		= "CMO_QVGA",
-	.refresh	= 60,
-	.xres		= 320,
-	.yres		= 240,
-	.pixclock	= KHZ2PICOS(7000),
-	.left_margin	= 68,
-	.right_margin	= 20,
-	.upper_margin	= 15,
-	.lower_margin	= 4,
-	.hsync_len	= 30,
-	.vsync_len	= 3,
-	.sync		= 0,
-	.vmode		= FB_VMODE_NONINTERLACED,
-};
-
-static void eukrea_cpuimx35_enable_display(int enable)
-{
-	gpio_direction_output(4, enable);
-}
-
-static struct imx_ipu_fb_platform_data ipu_fb_data = {
-	.mode		= &imxfb_mode,
-	.num_modes	= 1,
-	.bpp		= 16,
-	.enable		= eukrea_cpuimx35_enable_display,
-};
-
-#ifdef CONFIG_USB
-#ifndef CONFIG_USB_GADGET
-struct imxusb_platformdata otg_pdata = {
-	.flags = MXC_EHCI_INTERFACE_DIFF_UNI,
-	.mode = USB_DR_MODE_HOST,
-	.phymode = USBPHY_INTERFACE_MODE_UTMI,
-};
-#endif
-
-struct imxusb_platformdata hs_pdata = {
-	.flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN,
-	.mode = USB_DR_MODE_HOST,
-};
-#endif
-
-#ifdef CONFIG_USB_GADGET
-static struct fsl_usb2_platform_data usb_pdata = {
-	.operating_mode	= FSL_USB2_DR_DEVICE,
-	.phy_mode	= FSL_USB2_PHY_UTMI,
-};
-#endif
-
-static int eukrea_cpuimx35_mmu_init(void)
-{
-	l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000);
-
-	return 0;
-}
-postmmu_initcall(eukrea_cpuimx35_mmu_init);
-
-static iomux_v3_cfg_t eukrea_cpuimx35_pads[] = {
-	MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
-	MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
-	MX35_PAD_FEC_RX_DV__FEC_RX_DV,
-	MX35_PAD_FEC_COL__FEC_COL,
-	MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
-	MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
-	MX35_PAD_FEC_TX_EN__FEC_TX_EN,
-	MX35_PAD_FEC_MDC__FEC_MDC,
-	MX35_PAD_FEC_MDIO__FEC_MDIO,
-	MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
-	MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
-	MX35_PAD_FEC_CRS__FEC_CRS,
-	MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
-	MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
-	MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
-	MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
-	MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
-	MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
-	MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
-	MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
-
-	MX35_PAD_RXD1__UART1_RXD_MUX,
-	MX35_PAD_TXD1__UART1_TXD_MUX,
-	MX35_PAD_RTS1__UART1_RTS,
-	MX35_PAD_CTS1__UART1_CTS,
-
-	MX35_PAD_LD23__GPIO3_29,
-	MX35_PAD_CONTRAST__GPIO1_1,
-	MX35_PAD_D3_CLS__GPIO1_4,
-
-	MX35_PAD_I2C1_CLK__I2C1_SCL,
-	MX35_PAD_I2C1_DAT__I2C1_SDA,
-
-	MX35_PAD_SD1_CMD__ESDHC1_CMD,
-	MX35_PAD_SD1_CLK__ESDHC1_CLK,
-	MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
-	MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
-	MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
-	MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
-
-	MX35_PAD_LD19__GPIO3_25,
-};
-
-static int eukrea_cpuimx35_devices_init(void)
-{
-#ifdef CONFIG_USB_GADGET
-	unsigned int tmp;
-#endif
-	mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads,
-		ARRAY_SIZE(eukrea_cpuimx35_pads));
-
-	imx35_add_nand(&nand_info);
-
-	devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
-	dev_add_bb_dev("self_raw", "self0");
-	devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw");
-	dev_add_bb_dev("env_raw", "env0");
-
-	imx35_add_fec(&fec_info);
-	imx35_add_fb(&ipu_fb_data);
-
-	imx35_add_i2c0(NULL);
-	imx35_add_mmc0(NULL);
-
-	/* led default off */
-	gpio_direction_output(32 * 2 + 29, 1);
-
-	/* Switch : input */
-	gpio_direction_input(32 * 2 + 25);
-
-	/* screen default on to prevent flicker */
-	gpio_direction_output(4, 0);
-	/* backlight default off */
-	gpio_direction_output(1, 0);
-
-#ifdef CONFIG_USB
-#ifndef CONFIG_USB_GADGET
-	imx_add_usb((void *)MX35_USB_OTG_BASE_ADDR, 0, &otg_pdata);
-#endif
-	imx_add_usb((void *)MX35_USB_HS_BASE_ADDR, 1, &hs_pdata);
-#endif
-
-#ifdef CONFIG_USB_GADGET
-	/* Workaround ENGcm09152 */
-	tmp = readl(MX35_USB_OTG_BASE_ADDR + 0x608);
-	writel(tmp | (1 << 23), MX35_USB_OTG_BASE_ADDR + 0x608);
-	add_generic_device("fsl-udc", DEVICE_ID_DYNAMIC, NULL, MX35_USB_OTG_BASE_ADDR, 0x200,
-			   IORESOURCE_MEM, &usb_pdata);
-#endif
-	armlinux_set_architecture(MACH_TYPE_EUKREA_CPUIMX35SD);
-
-	if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT_GENERIC))
-		defaultenv_append_directory(defaultenv_eukrea_cpuimx35);
-
-	return 0;
-}
-
-device_initcall(eukrea_cpuimx35_devices_init);
-
-static int eukrea_cpuimx35_console_init(void)
-{
-	barebox_set_model("Eukrea CPUIMX35");
-	barebox_set_hostname("eukrea-cpuimx35");
-
-	imx35_add_uart0();
-	return 0;
-}
-
-console_initcall(eukrea_cpuimx35_console_init);
-
-static int eukrea_cpuimx35_core_init(void)
-{
-	u32 reg;
-
-	/* enable clock for I2C1, ESDHC1, USB and FEC */
-	reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR0);
-	reg |= 0x3 << MX35_CCM_CGR0_ESDHC1_SHIFT;
-	reg = writel(reg, MX35_CCM_BASE_ADDR + MX35_CCM_CGR0);
-	reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR1);
-	reg |= 0x3 << MX35_CCM_CGR1_FEC_SHIFT;
-	reg |= 0x3 << MX35_CCM_CGR1_I2C1_SHIFT;
-	reg = writel(reg, MX35_CCM_BASE_ADDR + MX35_CCM_CGR1);
-	reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR2);
-	reg |= 0x3 << MX35_CCM_CGR2_USB_SHIFT;
-	reg = writel(reg, MX35_CCM_BASE_ADDR + MX35_CCM_CGR2);
-
-	/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
-	/*
-	 * Set all MPROTx to be non-bufferable, trusted for R/W,
-	 * not forced to user-mode.
-	 */
-	writel(0x77777777, MX35_AIPS1_BASE_ADDR);
-	writel(0x77777777, MX35_AIPS1_BASE_ADDR + 0x4);
-	writel(0x77777777, MX35_AIPS2_BASE_ADDR);
-	writel(0x77777777, MX35_AIPS2_BASE_ADDR + 0x4);
-
-	/*
-	 * Clear the on and off peripheral modules Supervisor Protect bit
-	 * for SDMA to access them. Did not change the AIPS control registers
-	 * (offset 0x20) access type
-	 */
-	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x40);
-	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x44);
-	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x48);
-	writel(0x0, MX35_AIPS1_BASE_ADDR + 0x4C);
-	reg = readl(MX35_AIPS1_BASE_ADDR + 0x50);
-	reg &= 0x00FFFFFF;
-	writel(reg, MX35_AIPS1_BASE_ADDR + 0x50);
-
-	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x40);
-	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x44);
-	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x48);
-	writel(0x0, MX35_AIPS2_BASE_ADDR + 0x4C);
-	reg = readl(MX35_AIPS2_BASE_ADDR + 0x50);
-	reg &= 0x00FFFFFF;
-	writel(reg, MX35_AIPS2_BASE_ADDR + 0x50);
-
-	/* MAX (Multi-Layer AHB Crossbar Switch) setup */
-
-	/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
-#define MAX_PARAM1 0x00302154
-	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x000); /* for S0 */
-	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x100); /* for S1 */
-	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x200); /* for S2 */
-	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x300); /* for S3 */
-	writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x400); /* for S4 */
-
-	/* SGPCR - always park on last master */
-	writel(0x10, MX35_MAX_BASE_ADDR + 0x10);	/* for S0 */
-	writel(0x10, MX35_MAX_BASE_ADDR + 0x110);	/* for S1 */
-	writel(0x10, MX35_MAX_BASE_ADDR + 0x210);	/* for S2 */
-	writel(0x10, MX35_MAX_BASE_ADDR + 0x310);	/* for S3 */
-	writel(0x10, MX35_MAX_BASE_ADDR + 0x410);	/* for S4 */
-
-	/* MGPCR - restore default values */
-	writel(0x0, MX35_MAX_BASE_ADDR + 0x800);	/* for M0 */
-	writel(0x0, MX35_MAX_BASE_ADDR + 0x900);	/* for M1 */
-	writel(0x0, MX35_MAX_BASE_ADDR + 0xa00);	/* for M2 */
-	writel(0x0, MX35_MAX_BASE_ADDR + 0xb00);	/* for M3 */
-	writel(0x0, MX35_MAX_BASE_ADDR + 0xc00);	/* for M4 */
-	writel(0x0, MX35_MAX_BASE_ADDR + 0xd00);	/* for M5 */
-
-	/*
-	 * M3IF Control Register (M3IFCTL)
-	 * MRRP[0] = L2CC0 not on priority list (0 << 0)	= 0x00000000
-	 * MRRP[1] = MAX1 not on priority list (0 << 0)		= 0x00000000
-	 * MRRP[2] = L2CC1 not on priority list (0 << 0)	= 0x00000000
-	 * MRRP[3] = USB  not on priority list (0 << 0)		= 0x00000000
-	 * MRRP[4] = SDMA not on priority list (0 << 0)		= 0x00000000
-	 * MRRP[5] = GPU not on priority list (0 << 0)		= 0x00000000
-	 * MRRP[6] = IPU1 on priority list (1 << 6)		= 0x00000040
-	 * MRRP[7] = IPU2 not on priority list (0 << 0)		= 0x00000000
-	 *                                                       ------------
-	 *                                                        0x00000040
-	 */
-	writel(0x40, MX35_M3IF_BASE_ADDR);
-
-	return 0;
-}
-
-core_initcall(eukrea_cpuimx35_core_init);
-
-static int do_cpufreq(int argc, char *argv[])
-{
-	unsigned long freq;
-
-	if (argc != 2)
-		return COMMAND_ERROR_USAGE;
-
-	freq = simple_strtoul(argv[1], NULL, 0);
-
-	switch (freq) {
-	case 399:
-		writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL);
-		break;
-	case 532:
-		writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL);
-		break;
-	default:
-		return COMMAND_ERROR_USAGE;
-	}
-
-	printf("Switched CPU frequency to %luMHz\n", freq);
-
-	return 0;
-}
-
-BAREBOX_CMD_START(cpufreq)
-	.cmd            = do_cpufreq,
-	BAREBOX_CMD_DESC("adjust CPU frequency")
-	BAREBOX_CMD_OPTS("399|532")
-	BAREBOX_CMD_GROUP(CMD_GRP_HWMANIP)
-BAREBOX_CMD_END
diff --git a/arch/arm/boards/eukrea_cpuimx35/flash-header.imxcfg b/arch/arm/boards/eukrea_cpuimx35/flash-header.imxcfg
deleted file mode 100644
index ad187db742..0000000000
--- a/arch/arm/boards/eukrea_cpuimx35/flash-header.imxcfg
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-soc imx35
-loadaddr 0x80000000
-ivtofs 0x400
-
-wm 32 0x53F80004 0x00821000
-wm 32 0x53F80004 0x00821000
-wm 32 0xb8001010 0x00000004
-wm 32 0xB8001010 0x0000000C
-wm 32 0xb8001004 0x0009572B
-wm 32 0xb8001000 0x92220000
-wm 8 0x80000400 0xda
-wm 32 0xb8001000 0xa2220000
-wm 32 0x80000000 0x12344321
-wm 32 0x80000000 0x12344321
-wm 32 0xb8001000 0xb2220000
-wm 8 0x80000033 0xda
-wm 8 0x82000000 0xda
-wm 32 0xb8001000 0x82224080
-wm 32 0xb8001010 0x00000004
diff --git a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
deleted file mode 100644
index 7970b82136..0000000000
--- a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
+++ /dev/null
@@ -1,128 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-// SPDX-FileCopyrightText: 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
-
-#include <common.h>
-#include <init.h>
-#include <mach/imx35-regs.h>
-#include <mach/imx-pll.h>
-#include <mach/esdctl.h>
-#include <asm/cache-l2x0.h>
-#include <io.h>
-#include <mach/imx-nand.h>
-#include <asm/barebox-arm.h>
-#include <asm/barebox-arm-head.h>
-#include <asm/sections.h>
-#include <asm-generic/memory_layout.h>
-#include <asm/system.h>
-
-void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
-{
-	uint32_t r, s;
-	unsigned long ccm_base = MX35_CCM_BASE_ADDR;
-	register uint32_t loops = 0x20000;
-
-	arm_cpu_lowlevel_init();
-
-	arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE);
-
-	r = get_cr();
-	r |= CR_Z; /* Flow prediction (Z) */
-	r |= CR_U; /* unaligned accesses  */
-	r |= CR_FI; /* Low Int Latency     */
-
-	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(s));
-	s |= 0x7;
-	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1" : : "r"(s));
-
-	set_cr(r);
-
-	r = 0;
-	__asm__ __volatile__("mcr p15, 0, %0, c15, c2, 4" : : "r"(r));
-
-	/*
-	 * Branch predicition is now enabled.  Flush the BTAC to ensure a valid
-	 * starting point.  Don't flush BTAC while it is disabled to avoid
-	 * ARM1136 erratum 408023.
-	 */
-	__asm__ __volatile__("mcr p15, 0, %0, c7, c5, 6" : : "r"(r));
-
-	/* invalidate I cache and D cache */
-	__asm__ __volatile__("mcr p15, 0, %0, c7, c7, 0" : : "r"(r));
-
-	/* invalidate TLBs */
-	__asm__ __volatile__("mcr p15, 0, %0, c8, c7, 0" : : "r"(r));
-
-	/* Drain the write buffer */
-	__asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" : : "r"(r));
-
-	/* Also setup the Peripheral Port Remap register inside the core */
-	r = 0x40000015; /* start from AIPS 2GB region */
-	__asm__ __volatile__("mcr p15, 0, %0, c15, c2, 4" : : "r"(r));
-
-	/*
-	 * End of ARM1136 init
-	 */
-
-	writel(0x003F4208, ccm_base + MX35_CCM_CCMR);
-
-	/* Set MPLL , arm clock and ahb clock*/
-	writel(MPCTL_PARAM_532, ccm_base + MX35_CCM_MPCTL);
-
-	writel(PPCTL_PARAM_300, ccm_base + MX35_CCM_PPCTL);
-	writel(0x00001000, ccm_base + MX35_CCM_PDR0);
-
-	r = readl(ccm_base + MX35_CCM_CGR0);
-	r |= 0x3 << MX35_CCM_CGR0_EPIT1_SHIFT;
-	writel(r, ccm_base + MX35_CCM_CGR0);
-
-	r = readl(ccm_base + MX35_CCM_CGR1);
-	r |= 0x3 << MX35_CCM_CGR1_FEC_SHIFT;
-	r |= 0x3 << MX35_CCM_CGR1_I2C1_SHIFT;
-	r |= 0x3 << MX35_CCM_CGR1_IOMUX_SHIFT;
-	writel(r, ccm_base + MX35_CCM_CGR1);
-
-	/* enable watchdog asap */
-	r = readl(ccm_base + MX35_CCM_CGR2);
-	r |= 0x3 << MX35_CCM_CGR2_WDOG_SHIFT;
-	writel(r, ccm_base + MX35_CCM_CGR2);
-
-	r = readl(MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL);
-	r |= 0x1000;
-	writel(r, MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL);
-
-	/* Skip SDRAM initialization if we run from RAM */
-	r = get_pc();
-	if (r > 0x80000000 && r < 0x90000000)
-		goto out;
-
-	/* Init Mobile DDR */
-	writel(0x0000000E, MX35_ESDCTL_BASE_ADDR + IMX_ESDMISC);
-	writel(0x00000004, MX35_ESDCTL_BASE_ADDR + IMX_ESDMISC);
-	__asm__ volatile ("1:\n"
-			"subs %0, %1, #1\n"
-			"bne 1b":"=r" (loops):"0" (loops));
-
-	writel(0x0009572B, MX35_ESDCTL_BASE_ADDR + IMX_ESDCFG0);
-	writel(0x92220000, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
-	writeb(0xda, MX35_CSD0_BASE_ADDR + 0x400);
-	writel(0xA2220000, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
-	writeb(0xda, MX35_CSD0_BASE_ADDR);
-	writeb(0xda, MX35_CSD0_BASE_ADDR);
-	writel(0xB2220000, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
-	writeb(0xda, MX35_CSD0_BASE_ADDR + 0x33);
-	writeb(0xda, MX35_CSD0_BASE_ADDR + 0x2000000);
-	writel(0x82228080, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
-
-	if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) {
-		/* Speed up NAND controller by adjusting the NFC divider */
-		r = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
-		r &= ~(0xf << 28);
-		r |= 0x1 << 28;
-		writel(r, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
-
-		imx35_barebox_boot_nand_external();
-	}
-
-out:
-	imx35_barebox_entry(NULL);
-}