ARM: rename boards to more consistent naming

This renames the Freescale and Phytec board directories and defconfig
files to a common naming scheme. The board directories are named
<vendor>-<board> and the defconfig files are named
<vendor>-<board>_defconfig. Also the DataModul realq7 is renamed to its
Marketing Name eDM-QMX6.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

5 files changed, 345 insertions, 0 deletions

diff --git a/arch/arm/boards/freescale-mx21-ads/Makefile b/arch/arm/boards/freescale-mx21-ads/Makefile
new file mode 100644
index 0000000000..a43425b9ea
--- /dev/null
+++ b/arch/arm/boards/freescale-mx21-ads/Makefile
@@ -0,0 +1,2 @@
+lwl-y += lowlevel_init.o
+obj-y += imx21ads.o
diff --git a/arch/arm/boards/freescale-mx21-ads/env/bin/init b/arch/arm/boards/freescale-mx21-ads/env/bin/init
new file mode 100644
index 0000000000..224a6b40be
--- /dev/null
+++ b/arch/arm/boards/freescale-mx21-ads/env/bin/init
@@ -0,0 +1 @@
+# Dummy Init environment script
diff --git a/arch/arm/boards/freescale-mx21-ads/imx21ads.c b/arch/arm/boards/freescale-mx21-ads/imx21ads.c
new file mode 100644
index 0000000000..1bbd8cbf2a
--- /dev/null
+++ b/arch/arm/boards/freescale-mx21-ads/imx21ads.c
@@ -0,0 +1,194 @@
+/*
+ * Copyright (C) 2009 Ivo Clarysse
+ * 
+ * Based on imx27ads.c,
+ *   Copyright (C) 2007 Sascha Hauer, Pengutronix 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *
+ */
+
+#include <common.h>
+#include <net.h>
+#include <init.h>
+#include <environment.h>
+#include <mach/imx21-regs.h>
+#include <asm/armlinux.h>
+#include <asm/sections.h>
+#include <asm/barebox-arm.h>
+#include <io.h>
+#include <gpio.h>
+#include <mach/weim.h>
+#include <partition.h>
+#include <fs.h>
+#include <sizes.h>
+#include <fcntl.h>
+#include <generated/mach-types.h>
+#include <mach/imx-nand.h>
+#include <mach/imxfb.h>
+#include <mach/iomux-mx21.h>
+#include <mach/devices-imx21.h>
+
+#define MX21ADS_IO_REG    0xCC800000
+#define MX21ADS_IO_LCDON  (1 << 9)
+
+struct imx_nand_platform_data nand_info = {
+	.width = 1,
+	.hw_ecc = 1,
+};
+
+/* Sharp LQ035Q7DB02 QVGA display */
+static struct imx_fb_videomode imx_fb_modedata = {
+        .mode = {
+		.name           = "Sharp-LQ035Q7",
+		.refresh        = 60,
+		.xres           = 240,
+		.yres           = 320,
+		.pixclock       = 188679,
+		.left_margin    = 6,
+		.right_margin   = 16,
+		.upper_margin   = 8,
+		.lower_margin   = 10,
+		.hsync_len      = 2,
+		.vsync_len      = 1,
+		.sync           = 0,
+		.vmode          = FB_VMODE_NONINTERLACED,
+		.flag           = 0,
+	},
+        .pcr            = 0xfb108bc7,
+        .bpp            = 16,
+};
+
+static struct imx_fb_platform_data imx_fb_data = {
+	.mode           = &imx_fb_modedata,
+	.num_modes	= 1,
+	.cmap_greyscale = 0,
+	.cmap_inverse   = 0,
+	.cmap_static    = 0,
+	.pwmr           = 0x00a903ff,
+	.lscr1          = 0x00120300,
+	.dmacr          = 0x00020008,
+};
+
+static int imx21ads_timing_init(void)
+{
+	u32 temp;
+
+	/* Configure External Interface Module */
+	/* CS0: burst flash */
+	imx21_setup_eimcs(0, 0x00003E00, 0x00000E01);
+
+	/* CS1: Ethernet controller, external UART, memory-mapped I/O (16-bit) */
+	imx21_setup_eimcs(1, 0x00002000, 0x11118501);
+
+	/* CS2-CS5: disable */
+	imx21_setup_eimcs(2, 0x0, 0x0);
+	imx21_setup_eimcs(3, 0x0, 0x0);
+	imx21_setup_eimcs(4, 0x0, 0x0);
+	imx21_setup_eimcs(5, 0x0, 0x0);
+
+	temp = readl(MX21_CCM_BASE_ADDR + MX21_PCDR0);
+	temp &= ~0xF000;
+	temp |= 0xA000;  /* Set NFC divider; 0xA yields 24.18MHz */
+	writel(temp, MX21_CCM_BASE_ADDR + MX21_PCDR0);
+
+	return 0;
+}
+
+core_initcall(imx21ads_timing_init);
+
+static int mx21ads_mem_init(void)
+{
+	arm_add_mem_device("ram0", 0xc0000000, SZ_64M);
+
+	return 0;
+}
+mem_initcall(mx21ads_mem_init);
+
+static int mx21ads_devices_init(void)
+{
+	int i;
+	unsigned int mode[] = {
+		PA5_PF_LSCLK,
+		PA6_PF_LD0,
+		PA7_PF_LD1,
+		PA8_PF_LD2,
+		PA9_PF_LD3,
+		PA10_PF_LD4,
+		PA11_PF_LD5,
+		PA12_PF_LD6,
+		PA13_PF_LD7,
+		PA14_PF_LD8,
+		PA15_PF_LD9,
+		PA16_PF_LD10,
+		PA17_PF_LD11,
+		PA18_PF_LD12,
+		PA19_PF_LD13,
+		PA20_PF_LD14,
+		PA21_PF_LD15,
+		PA22_PF_LD16,
+		PA23_PF_LD17,
+		PA24_PF_REV,
+		PA25_PF_CLS,
+		PA26_PF_PS,
+		PA27_PF_SPL_SPR,
+		PA28_PF_HSYNC,
+		PA29_PF_VSYNC,
+		PA30_PF_CONTRAST,
+		PA31_PF_OE_ACD,
+		PE12_PF_UART1_TXD,
+		PE13_PF_UART1_RXD,
+		PE14_PF_UART1_CTS,
+		PE15_PF_UART1_RTS,
+	};
+
+	/* initizalize gpios */
+	for (i = 0; i < ARRAY_SIZE(mode); i++)
+		imx_gpio_mode(mode[i]);
+
+	add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX21_CS0_BASE_ADDR,
+			32 * 1024 * 1024, 0);
+	imx21_add_nand(&nand_info);
+	add_generic_device("cs8900", DEVICE_ID_DYNAMIC, NULL,
+			MX21_CS1_BASE_ADDR, 0x1000,
+			IORESOURCE_MEM, NULL);
+	imx21_add_fb(&imx_fb_data);
+
+	armlinux_set_architecture(MACH_TYPE_MX21ADS);
+
+	return 0;
+}
+
+device_initcall(mx21ads_devices_init);
+
+static int mx21ads_enable_display(void)
+{
+	u16 tmp;
+
+	tmp = readw(MX21ADS_IO_REG);
+	tmp |= MX21ADS_IO_LCDON;
+	writew(tmp, MX21ADS_IO_REG);
+	return 0;
+}
+
+late_initcall(mx21ads_enable_display);
+
+static int mx21ads_console_init(void)
+{
+	barebox_set_model("Freescale i.MX21 ADS");
+	barebox_set_hostname("mx21ads");
+
+	imx21_add_uart0();
+	return 0;
+}
+
+console_initcall(mx21ads_console_init);
diff --git a/arch/arm/boards/freescale-mx21-ads/imx21ads.dox b/arch/arm/boards/freescale-mx21-ads/imx21ads.dox
new file mode 100644
index 0000000000..9f11ffaa6e
--- /dev/null
+++ b/arch/arm/boards/freescale-mx21-ads/imx21ads.dox
@@ -0,0 +1,5 @@
+/** @page imx21ads Freescale i.MX21ads
+
+This is the Freescale evaluation board for the i.MX21 Processor
+
+*/
diff --git a/arch/arm/boards/freescale-mx21-ads/lowlevel_init.S b/arch/arm/boards/freescale-mx21-ads/lowlevel_init.S
new file mode 100644
index 0000000000..471390f328
--- /dev/null
+++ b/arch/arm/boards/freescale-mx21-ads/lowlevel_init.S
@@ -0,0 +1,143 @@
+/*
+ * Copyright (C) 2010 Jaccon Bastiaansen <jaccon.bastiaansen@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <config.h>
+#include <sizes.h>
+#include <asm-generic/memory_layout.h>
+#include <mach/imx21-regs.h>
+#include <asm/barebox-arm-head.h>
+
+	.section ".text_bare_init","ax"
+
+.globl barebox_arm_reset_vector
+barebox_arm_reset_vector:
+
+	bl	arm_cpu_lowlevel_init
+
+/*
+ * Initialize the AHB-Lite IP Interface (AIPI) module (to enable access to
+ * on chip peripherals) as described in section 7.2 of rev3 of the i.MX21
+ * reference manual.
+ */
+	ldr	r0, =MX21_AIPI_BASE_ADDR + MX21_AIPI1_PSR0
+	ldr	r1, =0x00040304
+	str	r1, [r0]
+	ldr	r0, =MX21_AIPI_BASE_ADDR + MX21_AIPI1_PSR1
+	ldr     r1, =0xfffbfcfb
+	str	r1, [r0]
+
+	ldr	r0, =MX21_AIPI_BASE_ADDR + MX21_AIPI2_PSR0
+	ldr	r1, =0x3ffc0000
+	str	r1, [r0]
+	ldr	r0, =MX21_AIPI_BASE_ADDR + MX21_AIPI2_PSR1
+	ldr     r1, =0xffffffff
+	str	r1, [r0]
+
+/*
+ * Configure CPU core clock (266MHz), peripheral clock (133MHz) and enable
+ * the clock to peripherals.
+ */
+	ldr	r0, =MX21_CCM_BASE_ADDR + MX21_CSCR
+	ldr	r1, =0x17180607
+	str	r1, [r0]
+
+	ldr	r0, =MX21_CCM_BASE_ADDR + MX21_PCCR1
+	ldr	r1, =0x0e000000
+	str	r1, [r0]
+
+
+/*
+ * SDRAM and SDRAM controller configuration
+ */
+
+	/*
+	 * CSD1 not required, because the MX21ADS board only contains 64Mbyte.
+	 * CS3 can therefore be made available.
+	 */
+	ldr	r0, =MX21_SYSCTRL_BASE_ADDR + MX21_FMCR
+	ldr	r1, =0xffffffc9
+	str	r1, [r0]
+
+	/* Skip SDRAM initialization if we run from RAM */
+	cmp	pc, #0xc0000000
+	bls	1f
+	cmp	pc, #0xc8000000
+	bhi	1f
+
+	b	ret
+1:
+
+	/* Precharge */
+	ldr	r0, =MX21_X_MEMC_BASE_ADDR + MX21_SDCTL0
+	ldr	r1, =0x92120300
+	str	r1, [r0]
+	ldr	r2, =0xc0200000
+	ldr	r1, [r2]
+
+	bl	mem_delay
+
+	/* Auto refresh */
+	ldr	r1, =0xa2120300
+	str	r1, [r0]
+	ldr	r2, =0xc0000000
+	ldr	r1, [r2]
+	ldr	r1, [r2]
+	ldr	r1, [r2]
+	ldr	r1, [r2]
+	ldr	r1, [r2]
+	ldr	r1, [r2]
+	ldr	r1, [r2]
+	ldr	r1, [r2]
+
+	/* Set mode register */
+	ldr	r1, =0xB2120300
+	str	r1, [r0]
+	ldr	r1, =0xC0119800
+	ldr	r2, [r1]
+
+	bl	mem_delay
+
+	/* Back to Normal Mode */
+	ldr	r1, =0x8212F339
+	str	r1, [r0]
+
+	/* Set NFC_CLK to 24MHz */
+	ldr	r0, =MX21_CCM_BASE_ADDR + MX21_PCDR0
+	ldr	r1, =0x6419a007
+	str	r1, [r0]
+
+#ifdef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND {
+
+	/* Setup a temporary stack in SRAM */
+	ldr	sp, =MX21_IRAM_BASE_ADDR + MX21_IRAM_SIZE - 4
+
+	b	imx21_barebox_boot_nand_external
+#endif /* CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND */
+
+ret:
+	mov	r0, #0xc0000000
+	mov	r1, #SZ_64M
+	mov	r2, #0
+	b	barebox_arm_entry
+
+/*
+ *  spin for a while.  we need to wait at least 200 usecs.
+ */
+mem_delay:
+	mov	r4, #0x4000
+spin:	subs	r4, r4, #1
+	bne	spin
+	mov	pc, lr
+