diff options
| author | Sascha Hauer <s.hauer@pengutronix.de> | 2012-10-10 22:10:36 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2012-10-17 20:22:02 +0200 |
| commit | 6a9d37e579b7922b427d02aa02a9f104b378a628 (patch) | |
| tree | a95ce6c274170c673de122c90de392c8c3cb917f /arch/arm/boards/guf-neso/pll_init.S | |
| parent | 11b175793714f7461e91bc00120c7f6e8b2fdc5a (diff) | |
| download | barebox-6a9d37e579b7922b427d02aa02a9f104b378a628.tar.gz barebox-6a9d37e579b7922b427d02aa02a9f104b378a628.tar.xz | |
ARM i.MX27: Cleanup remaining unprefixed registers
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/boards/guf-neso/pll_init.S')
| -rw-r--r-- | arch/arm/boards/guf-neso/pll_init.S | 37 |
1 files changed, 20 insertions, 17 deletions
diff --git a/arch/arm/boards/guf-neso/pll_init.S b/arch/arm/boards/guf-neso/pll_init.S index 87e5312fb4..13df4a33ff 100644 --- a/arch/arm/boards/guf-neso/pll_init.S +++ b/arch/arm/boards/guf-neso/pll_init.S @@ -8,34 +8,37 @@ ldr r1, =val; \ str r1, [r0]; -#define CSCR_VAL CSCR_USB_DIV(3) | \ - CSCR_SD_CNT(3) | \ - CSCR_MSHC_SEL | \ - CSCR_H264_SEL | \ - CSCR_SSI1_SEL | \ - CSCR_SSI2_SEL | \ - CSCR_MCU_SEL | \ - CSCR_ARM_SRC_MPLL | \ - CSCR_SP_SEL | \ - CSCR_ARM_DIV(0) | \ - CSCR_FPM_EN | \ - CSCR_SPEN | \ - CSCR_MPEN | \ - CSCR_AHB_DIV(1) +#define CSCR_VAL MX27_CSCR_USB_DIV(3) | \ + MX27_CSCR_SD_CNT(3) | \ + MX27_CSCR_MSHC_SEL | \ + MX27_CSCR_H264_SEL | \ + MX27_CSCR_SSI1_SEL | \ + MX27_CSCR_SSI2_SEL | \ + MX27_CSCR_MCU_SEL | \ + MX27_CSCR_ARM_SRC_MPLL | \ + MX27_CSCR_SP_SEL | \ + MX27_CSCR_ARM_DIV(0) | \ + MX27_CSCR_FPM_EN | \ + MX27_CSCR_SPEN | \ + MX27_CSCR_MPEN | \ + MX27_CSCR_AHB_DIV(1) ENTRY(neso_pll_init) + /* 399 MHz */ writel(IMX_PLL_PD(0) | IMX_PLL_MFD(51) | IMX_PLL_MFI(7) | - IMX_PLL_MFN(35), MPCTL0) /* 399 MHz */ + IMX_PLL_MFN(35), MX27_CCM_BASE_ADDR + MX27_MPCTL0) + /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */ writel(IMX_PLL_PD(1) | IMX_PLL_MFD(12) | IMX_PLL_MFI(9) | - IMX_PLL_MFN(3), SPCTL0) /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */ + IMX_PLL_MFN(3), MX27_CCM_BASE_ADDR + MX27_SPCTL0) - writel(CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART, CSCR) + writel(CSCR_VAL | MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART, + MX27_CCM_BASE_ADDR + MX27_CSCR) ldr r2, =16000 1: |