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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2012-10-09 21:11:54 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2012-10-17 20:22:01 +0200 |
| commit | 7a334ccdece70ed769af6c1604e488b942685a03 (patch) | |
| tree | a4351432ecba41fc67dc967349b80aaf6e2d81a9 /arch/arm/boards/guf-neso | |
| parent | aaad5cbad757b21457874a6b7adbeaaad36a0ce3 (diff) | |
| download | barebox-7a334ccdece70ed769af6c1604e488b942685a03.tar.gz barebox-7a334ccdece70ed769af6c1604e488b942685a03.tar.xz | |
ARM i.MX: Use SoC specific base to access sdram controller registers
This redefines the sdram controller registers as offsets to the base
rather than as absolute addresses. All users are fixed to use the
SoC specific base address.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/boards/guf-neso')
| -rw-r--r-- | arch/arm/boards/guf-neso/lowlevel.c | 21 |
1 files changed, 14 insertions, 7 deletions
diff --git a/arch/arm/boards/guf-neso/lowlevel.c b/arch/arm/boards/guf-neso/lowlevel.c index e2e3c78f80..eff1f8d5c8 100644 --- a/arch/arm/boards/guf-neso/lowlevel.c +++ b/arch/arm/boards/guf-neso/lowlevel.c @@ -71,7 +71,8 @@ void __bare_init __naked reset(void) /* * DDR on CSD0 */ - writel(0x00000008, ESDMISC); /* Enable DDR SDRAM operation */ + /* Enable DDR SDRAM operation */ + writel(0x00000008, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC); DSCR(3) = 0x55555555; /* Set the driving strength */ DSCR(5) = 0x55555555; @@ -79,22 +80,28 @@ void __bare_init __naked reset(void) DSCR(7) = 0x00005005; DSCR(8) = 0x15555555; - writel(0x00000004, ESDMISC); /* Initial reset */ - writel(0x006ac73a, ESDCFG0); + /* Initial reset */ + writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC); + writel(0x006ac73a, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0); - writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, ESDCTL0); /* precharge CSD0 all banks */ + /* precharge CSD0 all banks */ + writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writel(0x00000000, 0xA0000F00); /* CSD0 precharge address (A10 = 1) */ - writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, ESDCTL0); + writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); for (i = 0; i < 8; i++) writel(0, 0xa0000f00); - writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, ESDCTL0); + writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writeb(0xda, 0xa0000033); writeb(0xff, 0xa1000000); writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 | - ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, ESDCTL0); + ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); #ifdef CONFIG_NAND_IMX_BOOT /* skip NAND boot if not running from NFC space */ |