summaryrefslogtreecommitdiffstats
path: root/arch/arm/boards/kontron-samx6i/mem.c
diff options
context:
space:
mode:
authorSascha Hauer <s.hauer@pengutronix.de>2021-02-22 10:39:39 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2021-02-22 10:39:39 +0100
commit9eff9ce48c2e2398a52f0d9d572c0a15f1a50de9 (patch)
treeae184b43cc7a88c9853bf1591edc95734e8b5ad2 /arch/arm/boards/kontron-samx6i/mem.c
parentc7b6bbe70b2decd3bde1fca0d740760975e71bf5 (diff)
parentfd6b10c4cebc6dfa44c9d6bccc3e8018e7150425 (diff)
downloadbarebox-9eff9ce48c2e2398a52f0d9d572c0a15f1a50de9.tar.gz
barebox-9eff9ce48c2e2398a52f0d9d572c0a15f1a50de9.tar.xz
Merge branch 'for-next/imx'
Diffstat (limited to 'arch/arm/boards/kontron-samx6i/mem.c')
-rw-r--r--arch/arm/boards/kontron-samx6i/mem.c54
1 files changed, 19 insertions, 35 deletions
diff --git a/arch/arm/boards/kontron-samx6i/mem.c b/arch/arm/boards/kontron-samx6i/mem.c
index 3b9fbd464a..08dceb55c0 100644
--- a/arch/arm/boards/kontron-samx6i/mem.c
+++ b/arch/arm/boards/kontron-samx6i/mem.c
@@ -17,7 +17,6 @@
#include "mem.h"
-#define PCBVERSION_PIN IMX_GPIO_NR(2, 2)
#define PCBID0_PIN IMX_GPIO_NR(6, 7)
#define PCBID1_PIN IMX_GPIO_NR(6, 9)
@@ -25,62 +24,47 @@
IOMUX_PAD(0x0658, 0x0270, 5, 0x0000, 0, 0)
#define MX6S_PAD_NANDF_WP_B__GPIO_6_9 \
IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0)
-#define MX6S_PAD_NANDF_D2__GPIO_2_2 \
- IOMUX_PAD(0x028c, 0x0674, 5, 0x0000, 0, 0)
resource_size_t samx6i_get_size(void)
{
resource_size_t size = 0;
- int ver, id0, id1;
+ int id0, id1;
int cpu_type = __imx6_cpu_type();
void __iomem *iomuxbase = IOMEM(MX6_IOMUXC_BASE_ADDR);
void __iomem *gpio6 = IOMEM(MX6_GPIO6_BASE_ADDR);
- void __iomem *gpio2 = IOMEM(MX6_GPIO2_BASE_ADDR);
if (cpu_type == IMX6_CPUTYPE_IMX6D ||
- cpu_type == IMX6_CPUTYPE_IMX6Q) {
+ cpu_type == IMX6_CPUTYPE_IMX6Q) {
imx_setup_pad(iomuxbase, MX6Q_PAD_NANDF_CLE__GPIO_6_7);
imx_setup_pad(iomuxbase, MX6Q_PAD_NANDF_WP_B__GPIO_6_9);
- imx_setup_pad(iomuxbase, MX6Q_PAD_NANDF_D2__GPIO_2_2);
} else if (cpu_type == IMX6_CPUTYPE_IMX6S ||
- cpu_type == IMX6_CPUTYPE_IMX6DL) {
+ cpu_type == IMX6_CPUTYPE_IMX6DL) {
imx_setup_pad(iomuxbase, MX6S_PAD_NANDF_CLE__GPIO_6_7);
imx_setup_pad(iomuxbase, MX6S_PAD_NANDF_WP_B__GPIO_6_9);
- imx_setup_pad(iomuxbase, MX6S_PAD_NANDF_D2__GPIO_2_2);
};
- imx6_gpio_direction_input(gpio6, 6);
+ imx6_gpio_direction_input(gpio6, 7);
imx6_gpio_direction_input(gpio6, 9);
- imx6_gpio_direction_input(gpio2, 2);
- ver = imx6_gpio_val(gpio2, 2);
id0 = imx6_gpio_val(gpio6, 7);
id1 = imx6_gpio_val(gpio6, 9);
- if (cpu_type == IMX6_CPUTYPE_IMX6D ||
- cpu_type == IMX6_CPUTYPE_IMX6Q) {
- if (ver)
- size = SZ_1G;
- else if (id0 && id1)
- size = SZ_2G;
- else if (id0)
- size = SZ_2G;
- else if (id1)
- size = SZ_1G;
- else
- size = SZ_512M;
- } else if (cpu_type == IMX6_CPUTYPE_IMX6S ||
- cpu_type == IMX6_CPUTYPE_IMX6DL) {
- if (ver)
- size = SZ_512M;
- if (id0 && id1)
- size = SZ_2G;
- else if (id0)
- size = SZ_1G;
- else if (id1)
- size = SZ_512M;
+ /* Solo/DualLite module sizes */
+ if (id0 && id1)
+ size = SZ_2G;
+ else if (id0)
+ size = SZ_1G;
+ else if (id1)
+ size = SZ_512M;
+ else
+ size = SZ_256M;
+
+ /* Dual/Quad modules always have twice the size */
+ if (cpu_type == IMX6_CPUTYPE_IMX6D || cpu_type == IMX6_CPUTYPE_IMX6Q) {
+ if (size == SZ_2G)
+ size = 0xf0000000; /* 4G on a 32bit system */
else
- size = SZ_128M;
+ size *= 2;
}
return size;