ARM: imx: phyCORE i.MX7 on phyBOARD-Zeta support

This adds preliminary support for the phyCORE i.MX7 module on a
phyBOARD-Zeta baseboard. The DTs will likely change in the future
when PHYTEC finalizes their BSP.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

4 files changed, 168 insertions, 0 deletions

diff --git a/arch/arm/boards/phytec-phycore-imx7/Makefile b/arch/arm/boards/phytec-phycore-imx7/Makefile
new file mode 100644
index 0000000000..01c7a259e9
--- /dev/null
+++ b/arch/arm/boards/phytec-phycore-imx7/Makefile
@@ -0,0 +1,2 @@
+obj-y += board.o
+lwl-y += lowlevel.o
diff --git a/arch/arm/boards/phytec-phycore-imx7/board.c b/arch/arm/boards/phytec-phycore-imx7/board.c
new file mode 100644
index 0000000000..c3ebd1fadf
--- /dev/null
+++ b/arch/arm/boards/phytec-phycore-imx7/board.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2017 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <environment.h>
+#include <mach/bbu.h>
+#include <asm/armlinux.h>
+#include <generated/mach-types.h>
+#include <partition.h>
+#include <mach/generic.h>
+#include <linux/sizes.h>
+#include <asm/psci.h>
+#include <io.h>
+#include <mach/imx7-regs.h>
+#include <serial/imx-uart.h>
+#include <asm/secure.h>
+
+static int phycore_mx7_devices_init(void)
+{
+	if (!of_machine_is_compatible("phytec,imx7d-phycore-som"))
+		return 0;
+
+	imx6_bbu_internal_mmc_register_handler("mmc", "/dev/mmc2.boot0.barebox",
+					       BBU_HANDLER_FLAG_DEFAULT);
+
+	psci_set_putc(imx_uart_putc, IOMEM(MX7_UART5_BASE_ADDR));
+
+	return 0;
+}
+device_initcall(phycore_mx7_devices_init);
diff --git a/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg b/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg
new file mode 100644
index 0000000000..b1608dd9c7
--- /dev/null
+++ b/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2016 NXP Semiconductors
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+soc imx7
+loadaddr 0x80000000
+dcdofs 0x400
+
+wm 32 0x30340004 0x4F400005
+/* Clear then set bit30 to ensure exit from DDR retention */
+wm 32 0x30360388 0x40000000
+wm 32 0x30360384 0x40000000
+
+wm 32 0x30391000 0x00000002
+wm 32 0x307a0000 0x01040001
+wm 32 0x307a01a0 0x80400003
+wm 32 0x307a01a4 0x00100020
+wm 32 0x307a01a8 0x80100004
+wm 32 0x307a0064 0x00400046
+wm 32 0x307a0490 0x00000001
+wm 32 0x307a00d0 0x00020083
+wm 32 0x307a00d4 0x00690000
+wm 32 0x307a00dc 0x09300004
+wm 32 0x307a00e0 0x04080000
+wm 32 0x307a00e4 0x00100004
+wm 32 0x307a00f4 0x0000033f
+wm 32 0x307a0100 0x09081109
+wm 32 0x307a0104 0x0007020d
+wm 32 0x307a0108 0x03040407
+wm 32 0x307a010c 0x00002006
+wm 32 0x307a0110 0x04020205
+wm 32 0x307a0114 0x03030202
+wm 32 0x307a0120 0x00000803
+wm 32 0x307a0180 0x00800020
+wm 32 0x307a0184 0x02000100
+wm 32 0x307a0190 0x02098204
+wm 32 0x307a0194 0x00030303
+wm 32 0x307a0200 0x00000016
+wm 32 0x307a0204 0x00171717
+wm 32 0x307a0214 0x04040404
+wm 32 0x307a0218 0x0f040404
+wm 32 0x307a0240 0x06000604
+wm 32 0x307a0244 0x00000001
+wm 32 0x30391000 0x00000000
+wm 32 0x30790000 0x17420f40
+wm 32 0x30790004 0x10210100
+wm 32 0x30790010 0x00060807
+wm 32 0x307900b0 0x1010007e
+wm 32 0x3079009c 0x00000d6e
+wm 32 0x30790020 0x08080808
+wm 32 0x30790030 0x08080808
+wm 32 0x30790050 0x01000010
+wm 32 0x30790050 0x00000010
+
+wm 32 0x307900c0 0x0e407304
+wm 32 0x307900c0 0x0e447304
+wm 32 0x307900c0 0x0e447306
+
+check 32 while_any_bit_clear 0x307900c4 0x1
+
+wm 32 0x307900c0 0x0e447304
+wm 32 0x307900c0 0x0e407304
+
+wm 32 0x30384130 0x00000000
+wm 32 0x30340020 0x00000178
+wm 32 0x30384130 0x00000002
+wm 32 0x30790018 0x0000000f
+
+check 32 while_any_bit_clear 0x307a0004 0x1
diff --git a/arch/arm/boards/phytec-phycore-imx7/lowlevel.c b/arch/arm/boards/phytec-phycore-imx7/lowlevel.c
new file mode 100644
index 0000000000..ee2d7ae553
--- /dev/null
+++ b/arch/arm/boards/phytec-phycore-imx7/lowlevel.c
@@ -0,0 +1,48 @@
+#define DEBUG
+#include <io.h>
+#include <common.h>
+#include <linux/sizes.h>
+#include <mach/generic.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+#include <mach/debug_ll.h>
+#include <asm/cache.h>
+
+extern char __dtb_imx7d_phyboard_zeta_start[];
+
+static noinline void phytec_phycore_imx7_start(void)
+{
+	void __iomem *iomuxbase = IOMEM(0x302c0000);
+	void __iomem *uart = IOMEM(MX7_UART5_BASE_ADDR);
+	void __iomem *ccmbase = IOMEM(MX7_CCM_BASE_ADDR);
+	void *fdt;
+
+	writel(0x3, ccmbase + 0x4000 + 16 * 152 + 0x8);
+	writel(0x10000000, ccmbase + 0x8000 + 128 * 99);
+	writel(0x3, ccmbase + 0x4000 + 16 * 152 + 0x4);
+	writel(0x3, iomuxbase + 0x18);
+	writel(0x3, iomuxbase + 0x1c);
+
+	imx7_uart_setup(uart);
+
+	pbl_set_putc(imx_uart_putc, uart);
+
+	pr_debug("Phytec phyCORE i.MX7\n");
+
+	fdt = __dtb_imx7d_phyboard_zeta_start - get_runtime_offset();
+
+	barebox_arm_entry(0x80000000, SZ_512M, fdt);
+}
+
+ENTRY_FUNCTION(start_phytec_phycore_imx7, r0, r1, r2)
+{
+	imx7_cpu_lowlevel_init();
+
+	arm_early_mmu_cache_invalidate();
+
+	relocate_to_current_adr();
+	setup_c();
+	barrier();
+
+	phytec_phycore_imx7_start();
+}
\ No newline at end of file