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| author | Juergen Borleis <jbe@pengutronix.de> | 2018-03-23 09:43:51 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-03-26 09:23:21 +0200 |
| commit | f04deb4018a2df204e16fc13c74028120cdb60a6 (patch) | |
| tree | 1f97528de964704199937c87d956003095cad0c6 /arch/arm/boards/phytec-phycore-imx7 | |
| parent | 971366078893a669246a52e6058d47de9993e77e (diff) | |
| download | barebox-f04deb4018a2df204e16fc13c74028120cdb60a6.tar.gz barebox-f04deb4018a2df204e16fc13c74028120cdb60a6.tar.xz | |
i.MX/DCD compiler and interpreter: logic is different
Reading the manual more carefully discovers a different logic for the
DCD 'check' command. They use the term "until". In order to get the
manual and the software in sync, this change switches to the term
"until" as well. Changing must happen at compiler and interpreter level
to make it work.
Signed-off-by: Juergen Borleis <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/boards/phytec-phycore-imx7')
| -rw-r--r-- | arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg b/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg index 6c256e8fc5..6e08b6c1b1 100644 --- a/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg +++ b/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg @@ -65,7 +65,7 @@ wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e407304 wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447304 wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447306 -check 32 while_any_bit_clear MX7_DDR_PHY_ZQ_CON1 0x1 +check 32 until_any_bit_set MX7_DDR_PHY_ZQ_CON1 0x1 wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447304 wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e407304 @@ -75,4 +75,4 @@ wm 32 0x30340020 0x00000178 wm 32 0x30384130 0x00000002 wm 32 MX7_DDR_PHY_LP_CON0 0x0000000f -check 32 while_any_bit_clear MX7_DDRC_STAT 0x1 +check 32 until_any_bit_set MX7_DDRC_STAT 0x1 |