ARM: rename boards to more consistent naming

This renames the Freescale and Phytec board directories and defconfig
files to a common naming scheme. The board directories are named
<vendor>-<board> and the defconfig files are named
<vendor>-<board>_defconfig. Also the DataModul realq7 is renamed to its
Marketing Name eDM-QMX6.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

7 files changed, 809 insertions, 0 deletions

diff --git a/arch/arm/boards/phytec-phycore-omap4460/Makefile b/arch/arm/boards/phytec-phycore-omap4460/Makefile
new file mode 100644
index 0000000000..5d4eb10b9b
--- /dev/null
+++ b/arch/arm/boards/phytec-phycore-omap4460/Makefile
@@ -0,0 +1,2 @@
+obj-y += board.o
+lwl-y += lowlevel.o mux.o
diff --git a/arch/arm/boards/phytec-phycore-omap4460/board.c b/arch/arm/boards/phytec-phycore-omap4460/board.c
new file mode 100644
index 0000000000..baf88a380c
--- /dev/null
+++ b/arch/arm/boards/phytec-phycore-omap4460/board.c
@@ -0,0 +1,313 @@
+/*
+ * Copyright (C) 2011 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *
+ */
+
+#include <common.h>
+#include <console.h>
+#include <init.h>
+#include <driver.h>
+#include <gpio.h>
+#include <io.h>
+#include <ns16550.h>
+#include <asm/armlinux.h>
+#include <generated/mach-types.h>
+#include <mach/omap4-silicon.h>
+#include <mach/omap4-devices.h>
+#include <mach/omap4-clock.h>
+#include <mach/omap-fb.h>
+#include <mach/sdrc.h>
+#include <mach/sys_info.h>
+#include <mach/syslib.h>
+#include <mach/control.h>
+#include <linux/err.h>
+#include <sizes.h>
+#include <partition.h>
+#include <nand.h>
+#include <asm/mmu.h>
+#include <mach/gpmc.h>
+#include <mach/gpmc_nand.h>
+#include <i2c/i2c.h>
+
+static int pcm049_console_init(void)
+{
+	barebox_set_model("Phytec phyCORE-OMAP4460");
+	barebox_set_hostname("phycore-omap4460");
+
+	omap44xx_add_uart3();
+
+	return 0;
+}
+console_initcall(pcm049_console_init);
+
+static int pcm049_mem_init(void)
+{
+#ifdef CONFIG_1024MB_DDR2RAM
+	omap_add_ram0(SZ_1G);
+#else
+	omap_add_ram0(SZ_512M);
+#endif
+
+	omap44xx_add_sram0();
+	return 0;
+}
+mem_initcall(pcm049_mem_init);
+
+static struct gpmc_config net_cfg = {
+	.cfg = {
+		0xc1001000,	/* CONF1 */
+		0x00070700,	/* CONF2 */
+		0x00000000,	/* CONF3 */
+		0x07000700,	/* CONF4 */
+		0x09060909,	/* CONF5 */
+		0x000003c2,	/* CONF6 */
+	},
+	.base = 0x2C000000,
+	.size = GPMC_SIZE_16M,
+};
+
+static void pcm049_network_init(void)
+{
+	gpmc_cs_config(5, &net_cfg);
+
+	add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, 0x2C000000, 0x4000,
+			   IORESOURCE_MEM, NULL);
+}
+
+static struct i2c_board_info i2c_devices[] = {
+	{
+		I2C_BOARD_INFO("twl6030", 0x48),
+	},
+};
+
+static struct gpmc_nand_platform_data nand_plat = {
+	.wait_mon_pin = 1,
+	.ecc_mode = OMAP_ECC_BCH8_CODE_HW,
+	.nand_cfg = &omap4_nand_cfg,
+};
+
+static struct omapfb_display const pcm049_displays[] = {
+	{
+		.mode	= {
+			.name		= "pd050vl1",
+			.refresh	= 60,
+			.xres		= 640,
+			.yres		= 480,
+			.pixclock	= 25000,
+			.left_margin	= 46,
+			.right_margin	= 18,
+			.hsync_len	= 96,
+			.upper_margin	= 33,
+			.lower_margin	= 10,
+			.vsync_len	= 2,
+		},
+
+		.config = (OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
+				OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC |
+				OMAP_DSS_LCD_DATALINES_24),
+	},
+	/* Prime-View PM070WL4 */
+	{
+		.mode	= {
+			.name		= "pm070wl4",
+			.refresh	= 60,
+			.xres		= 800,
+			.yres		= 480,
+			.pixclock	= 32000,
+			.left_margin	= 86,
+			.right_margin	= 42,
+			.hsync_len	= 128,
+			.lower_margin	= 10,
+			.upper_margin	= 33,
+			.vsync_len	= 2,
+		},
+
+		.config = (OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
+				OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC |
+				OMAP_DSS_LCD_DATALINES_24),
+	},
+	/* Prime-View PD104SLF */
+	{
+		.mode	= {
+			.name		= "pd104slf",
+			.refresh	= 60,
+			.xres		= 800,
+			.yres		= 600,
+			.pixclock	= 40000,
+			.left_margin	= 86,
+			.right_margin	= 42,
+			.hsync_len	= 128,
+			.lower_margin	= 1,
+			.upper_margin	= 23,
+			.vsync_len	= 4,
+		},
+
+		.config = (OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
+				OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC |
+				OMAP_DSS_LCD_DATALINES_24),
+	},
+	/* EDT ETM0350G0DH6 */
+	{
+		.mode	= {
+			.name		= "edt_etm0350G0dh6",
+			.refresh	= 60,
+			.xres		= 320,
+			.yres		= 240,
+			.pixclock	= 15720,
+			.left_margin	= 68,
+			.right_margin	= 20,
+			.hsync_len	= 88,
+			.lower_margin	= 4,
+			.upper_margin	= 18,
+			.vsync_len	= 22,
+		},
+
+		.config = (OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
+				OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC |
+				OMAP_DSS_LCD_DATALINES_24),
+	},
+	/* EDT ETM0430G0DH6 */
+	{
+		.mode	= {
+			.name		= "edt_etm0430G0dh6",
+			.refresh	= 60,
+			.xres		= 480,
+			.yres		= 272,
+			.pixclock	= 9000,
+			.left_margin	= 2,
+			.right_margin	= 2,
+			.hsync_len	= 41,
+			.lower_margin	= 2,
+			.upper_margin	= 2,
+			.vsync_len	= 10,
+		},
+
+		.config = (OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
+				OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC |
+				OMAP_DSS_LCD_DATALINES_24),
+	},
+	/* EDT ETMV570G2DHU */
+	{
+		.mode	= {
+			.name		= "edt_etmv570G2dhu",
+			.refresh	= 60,
+			.xres		= 640,
+			.yres		= 480,
+			.pixclock	= 25175,
+			.left_margin	= 114,
+			.right_margin	= 16,
+			.hsync_len	= 30,
+			.lower_margin	= 10,
+			.upper_margin	= 35,
+			.vsync_len	= 3,
+		},
+
+		.config = (OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
+				OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC |
+				OMAP_DSS_LCD_DATALINES_24),
+	},
+	/* ETD ETM0700G0DH6 */
+	{
+		.mode	= {
+			.name		= "edt_etm0700G0dh6",
+			.refresh	= 60,
+			.xres		= 800,
+			.yres		= 480,
+			.pixclock	= 33260,
+			.left_margin	= 216,
+			.right_margin	= 40,
+			.hsync_len	= 128,
+			.lower_margin	= 10,
+			.upper_margin	= 35,
+			.vsync_len	= 2,
+		},
+
+		.config = (OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
+				OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC |
+				OMAP_DSS_LCD_DATALINES_24),
+	},
+
+	/* CHIMEI G104X1-L03 */
+	{
+		.mode = {
+			.name		= "g104x1",
+			.refresh	= 60,
+			.xres		= 1024,
+			.yres		= 768,
+			.pixclock	= 64000,
+			.left_margin	= 320,
+			.right_margin	= 1,
+			.hsync_len	= 320,
+			.upper_margin	= 38,
+			.lower_margin	= 38,
+			.vsync_len	= 2,
+		},
+		.config = (OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
+				OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC |
+				OMAP_DSS_LCD_DATALINES_24),
+
+		.power_on_delay		= 50,
+		.power_off_delay	= 100,
+	},
+};
+
+#define GPIO_DISPENABLE			  118
+#define GPIO_BACKLIGHT			  122
+
+static void pcm049_fb_enable(int e)
+{
+	gpio_direction_output(GPIO_DISPENABLE, e);
+	gpio_direction_output(GPIO_BACKLIGHT, e);
+}
+
+static struct omapfb_platform_data pcm049_fb_data = {
+	.displays	= pcm049_displays,
+	.num_displays	= ARRAY_SIZE(pcm049_displays),
+
+	.dss_clk_hz	= 19200000,
+
+	.bpp		= 32,
+	.enable		= pcm049_fb_enable,
+};
+
+static int pcm049_devices_init(void)
+{
+	i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
+	omap44xx_add_i2c1(NULL);
+	omap44xx_add_mmc1(NULL);
+
+	gpmc_generic_init(0x10);
+
+	if (IS_ENABLED(CONFIG_DRIVER_NET_SMC911X))
+		pcm049_network_init();
+
+	omap_add_gpmc_nand_device(&nand_plat);
+
+#ifdef CONFIG_PARTITION
+	devfs_add_partition("nand0", 0x00000, SZ_128K, DEVFS_PARTITION_FIXED, "xload_raw");
+	dev_add_bb_dev("xload_raw", "xload");
+	devfs_add_partition("nand0", SZ_128K, SZ_512K, DEVFS_PARTITION_FIXED, "self_raw");
+	dev_add_bb_dev("self_raw", "self0");
+	devfs_add_partition("nand0", SZ_128K + SZ_512K, SZ_128K, DEVFS_PARTITION_FIXED, "env_raw");
+	dev_add_bb_dev("env_raw", "env0");
+#endif
+
+	armlinux_set_architecture(MACH_TYPE_PCM049);
+
+	if (IS_ENABLED(CONFIG_DRIVER_VIDEO_OMAP))
+		omap_add_display(&pcm049_fb_data);
+
+	return 0;
+}
+device_initcall(pcm049_devices_init);
diff --git a/arch/arm/boards/phytec-phycore-omap4460/env/bin/init_board b/arch/arm/boards/phytec-phycore-omap4460/env/bin/init_board
new file mode 100644
index 0000000000..d5142ee8d0
--- /dev/null
+++ b/arch/arm/boards/phytec-phycore-omap4460/env/bin/init_board
@@ -0,0 +1,23 @@
+#!/bin/sh
+global displayargs
+. /env/config
+
+if [ -z $display ]; then
+	echo "no display configured"
+	exit 0
+fi
+
+if [ $display = dvi ]; then
+	global.displayargs="omapdss.def_disp=dvi omapfb.mode=dvi:$dvi_resolution"
+	exit 0
+fi
+
+# Display a splash screen
+
+if [ -e /dev/fb0 ]; then
+	fb0.mode_name=$display
+	splash /dev/nand0.splash.bb
+	fb0.enable=1
+fi
+
+global.displayargs="panel_generic_dpi.name=$display"
diff --git a/arch/arm/boards/phytec-phycore-omap4460/env/bin/nand_bootstrap b/arch/arm/boards/phytec-phycore-omap4460/env/bin/nand_bootstrap
new file mode 100644
index 0000000000..49e38dc4f0
--- /dev/null
+++ b/arch/arm/boards/phytec-phycore-omap4460/env/bin/nand_bootstrap
@@ -0,0 +1,31 @@
+#!/bin/sh
+echo "copying barebox to nand..."
+
+mci0.probe=1
+mkdir mnt
+
+mount /dev/disk0.0 /mnt
+if [ $? != 0 ]; then
+	echo "failed to mount mmc card"
+	exit 1
+fi
+
+if [ ! -f /mnt/mlo-nand.bin ]; then
+	echo "mlo-nand.bin not found on mmc card"
+	exit 1
+fi
+
+if [ ! -f /mnt/barebox.bin ]; then
+	echo "barebox.bin not found on mmc card"
+fi
+
+gpmc_nand0.eccmode=bch8_hw_romcode
+erase /dev/nand0.xload.bb
+cp /mnt/mlo-nand.bin /dev/nand0.xload.bb
+
+gpmc_nand0.eccmode=bch8_hw
+erase /dev/nand0.barebox.bb
+cp /mnt/barebox.bin /dev/nand0.barebox.bb
+
+echo "success"
+
diff --git a/arch/arm/boards/phytec-phycore-omap4460/env/config b/arch/arm/boards/phytec-phycore-omap4460/env/config
new file mode 100644
index 0000000000..1a252dd9c5
--- /dev/null
+++ b/arch/arm/boards/phytec-phycore-omap4460/env/config
@@ -0,0 +1,61 @@
+#!/bin/sh
+
+eth0.serverip=
+user=
+
+# use 'dhcp' to do dhcp in barebox and in kernel
+# use 'none' if you want to skip kernel ip autoconfiguration
+ip=dhcp
+
+# or set your networking parameters here
+#eth0.ipaddr=a.b.c.d
+#eth0.netmask=a.b.c.d
+#eth0.gateway=a.b.c.d
+#eth0.serverip=a.b.c.d
+
+# can be either 'nfs', 'tftp', 'nor' or 'nand'
+kernel_loc=tftp
+# can be either 'net', 'nor', 'nand' or 'initrd'
+rootfs_loc=net
+
+# can be either 'jffs2' or 'ubifs'
+rootfs_type=ubifs
+rootfsimage=root-${global.hostname}.$rootfs_type
+
+kernelimage=zImage-${global.hostname}
+#kernelimage=uImage-${global.hostname}
+#kernelimage=Image-${global.hostname}
+#kernelimage=Image-${global.hostname}.lzo
+
+if [ -n $user ]; then
+	kernelimage="$user"-"$kernelimage"
+	nfsroot="$eth0.serverip:/home/$user/nfsroot/${global.hostname}"
+	rootfsimage="$user"-"$rootfsimage"
+else
+	nfsroot="$eth0.serverip:/path/to/nfs/root"
+fi
+
+autoboot_timeout=3
+
+bootargs="console=ttyO2,115200"
+
+nand_parts="128k(xload)ro,512k(barebox),128k(bareboxenv),4M(kernel),4M(splash),-(root)"
+nand_device="omap2-nand.0"
+rootfs_mtdblock_nand=5
+
+#Displays
+# Splashscreen-Display can be either '', 'pd050vl1', 'pm070wl4', 'pd104slf', 'g104x1'
+# 'edt_etm0350G0dh6', 'edt_etm0430G0dh6', 'edt_etmv570G2dhu' or 'edt_etm0700G0dh6'
+# to use dvi output in kernel set 'display=dvi' and
+# dvi_resolution to '640x480-60' '800x600-60' or '1024x768-60'
+
+display=edt_etm0700G0dh6
+#dvi_resolution=1024x768-60
+
+if [ -n ${global.displayargs} ]; then
+	bootargs="$bootargs ${global.displayargs}"
+fi
+
+# set a fancy prompt (if support is compiled in)
+PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "
+
diff --git a/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c b/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c
new file mode 100644
index 0000000000..4f39600436
--- /dev/null
+++ b/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c
@@ -0,0 +1,126 @@
+/*
+ * (C) Copyright 2004-2009
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <common.h>
+#include <init.h>
+#include <io.h>
+#include <sizes.h>
+#include <mach/generic.h>
+#include <mach/omap4-mux.h>
+#include <mach/omap4-silicon.h>
+#include <mach/omap4-generic.h>
+#include <mach/omap4-clock.h>
+#include <mach/syslib.h>
+#include <asm/barebox-arm.h>
+#include <asm/barebox-arm-head.h>
+
+#define TPS62361_VSEL0_GPIO    182
+
+void set_muxconf_regs(void);
+
+/* 512MB */
+static const struct ddr_regs ddr_regs_mt42L64M64_25_400_mhz = {
+	.tim1		= 0x0EEB0662,
+	.tim2		= 0x20370DD2,
+	.tim3		= 0x00BFC33F,
+	.phy_ctrl_1	= 0x849FF408,
+	.ref_ctrl	= 0x00000618,
+	.config_init	= 0x80001AB1,
+	.config_final	= 0x80001AB1,
+	.zq_config	= 0xd0093215,
+	.mr1		= 0x83,
+	.mr2		= 0x4
+};
+
+/* 1GB */
+static const struct ddr_regs ddr_regs_mt42L128M64_25_400_mhz = {
+	.tim1		= 0x0EEB0663,
+	.tim2		= 0x205715D2,
+	.tim3		= 0x00BFC53F,
+	.phy_ctrl_1	= 0x849FF408,
+	.ref_ctrl	= 0x00000618,
+	.config_init	= 0x80001AB9,
+	.config_final	= 0x80001AB9,
+	.zq_config	= 0x50093215,
+	.mr1		= 0x83,
+	.mr2		= 0x4
+};
+
+static void noinline pcm049_init_lowlevel(void)
+{
+	struct dpll_param core = OMAP4_CORE_DPLL_PARAM_19M2_DDR400;
+	struct dpll_param mpu44xx = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000;
+	struct dpll_param mpu4460 = OMAP4_MPU_DPLL_PARAM_19M2_MPU920;
+	struct dpll_param iva = OMAP4_IVA_DPLL_PARAM_19M2;
+	struct dpll_param per = OMAP4_PER_DPLL_PARAM_19M2;
+	struct dpll_param abe = OMAP4_ABE_DPLL_PARAM_19M2;
+	struct dpll_param usb = OMAP4_USB_DPLL_PARAM_19M2;
+	unsigned int rev = omap4_revision();
+
+	set_muxconf_regs();
+
+#ifdef CONFIG_1024MB_DDR2RAM
+		omap4_ddr_init(&ddr_regs_mt42L128M64_25_400_mhz, &core);
+#else
+		omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core);
+#endif
+
+	/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
+	if (rev < OMAP4460_ES1_0)
+		omap4430_scale_vcores();
+	else
+		omap4460_scale_vcores(TPS62361_VSEL0_GPIO, 1320);
+
+	writel(CM_SYS_CLKSEL_19M2, CM_SYS_CLKSEL);
+
+	/* Configure all DPLL's at 100% OPP */
+	if (rev < OMAP4460_ES1_0)
+		omap4_configure_mpu_dpll(&mpu44xx);
+	else
+		omap4_configure_mpu_dpll(&mpu4460);
+
+	omap4_configure_iva_dpll(&iva);
+	omap4_configure_per_dpll(&per);
+	omap4_configure_abe_dpll(&abe);
+	omap4_configure_usb_dpll(&usb);
+
+	/* Enable all clocks */
+	omap4_enable_all_clocks();
+
+	sr32(OMAP44XX_SCRM_AUXCLK3, 8, 1, 0x1);  /* enable software ioreq */
+	sr32(OMAP44XX_SCRM_AUXCLK3, 1, 2, 0x0);  /* set for sys_clk (19.2MHz) */
+	sr32(OMAP44XX_SCRM_AUXCLK3, 16, 4, 0x0); /* set divisor to 1 */
+	sr32(OMAP44XX_SCRM_ALTCLKSRC, 0, 1, 0x1);  /* activate clock source */
+	sr32(OMAP44XX_SCRM_ALTCLKSRC, 2, 2, 0x3);  /* enable clocks */
+}
+
+void __bare_init __naked barebox_arm_reset_vector(uint32_t *data)
+{
+	omap4_save_bootinfo(data);
+
+	arm_cpu_lowlevel_init();
+
+	if (get_pc() > 0x80000000)
+		goto out;
+
+	arm_setup_stack(0x4030d000);
+
+	pcm049_init_lowlevel();
+out:
+	barebox_arm_entry(0x80000000, SZ_512M, 0);
+}
diff --git a/arch/arm/boards/phytec-phycore-omap4460/mux.c b/arch/arm/boards/phytec-phycore-omap4460/mux.c
new file mode 100644
index 0000000000..fda4c519b8
--- /dev/null
+++ b/arch/arm/boards/phytec-phycore-omap4460/mux.c
@@ -0,0 +1,253 @@
+#include <common.h>
+#include <init.h>
+#include <io.h>
+#include <mach/omap4-silicon.h>
+#include <mach/omap4-mux.h>
+#include <mach/omap4-clock.h>
+
+static const struct pad_conf_entry core_padconf_array[] = {
+	{GPMC_AD0, (IEN | PTD | DIS | M0)},				/* gpmc_ad0 */
+	{GPMC_AD1, (IEN | PTD | DIS | M0)},			 	/* gpmc_ad1 */
+	{GPMC_AD2, (IEN | PTD | DIS | M0)},				/* gpmc_ad2 */
+	{GPMC_AD3, (IEN | PTD | DIS | M0)},				/* gpmc_ad3 */
+	{GPMC_AD4, (IEN | PTD | DIS | M0)},				/* gpmc_ad4 */
+	{GPMC_AD5, (IEN | PTD | DIS | M0)},				/* gpmc_ad5 */
+	{GPMC_AD6, (IEN | PTD | DIS | M0)},				/* gpmc_ad6 */
+	{GPMC_AD7, (IEN | PTD | DIS | M0)},				/* gpmc_ad7 */
+	{GPMC_AD8, (IEN | PTD | DIS | M0)},				/* gpmc_ad8 */
+	{GPMC_AD9, (IEN | PTD | DIS | M0)},				/* gpmc_ad9 */
+	{GPMC_AD10, (IEN | PTD | DIS | M0)},				/* gpmc_ad10 */
+	{GPMC_AD11, (IEN | PTD | DIS | M0)},				/* gpmc_ad11 */
+	{GPMC_AD12, (IEN | PTD | DIS | M0)},				/* gpmc_ad12 */
+	{GPMC_AD13, (IEN | PTD | DIS | M0)},				/* gpmc_ad13 */
+	{GPMC_AD14, (IEN | PTD | DIS | M0)},				/* gpmc_ad14 */
+	{GPMC_AD15, (IEN | PTD | DIS | M0)},				/* gpmc_ad15 */
+	{GPMC_A16, (IEN | PTD | DIS | M0)},				/* gpmc_a16 */
+	{GPMC_A17, (IEN | PTD | DIS | M0)},				/* gpmc_a17 */
+	{GPMC_A18, (IEN | PTD | DIS | M0)},				/* gpmc_a18 */
+	{GPMC_A19, (IEN | PTD | DIS | M0)},				/* gpmc_a19 */
+	{GPMC_A20, (IEN | PTD | DIS | M0)},				/* gpmc_a20 */
+	{GPMC_A21, (IEN | PTD | DIS | M0)},				/* gpmc_a21 */
+	{GPMC_A22, (IEN | PTD | DIS | M0)},				/* gpmc_a22 */
+	{GPMC_A23, (IEN | PTD | DIS | M0)},				/* gpmc_a23 */
+	{GPMC_A24, (IEN | PTD | DIS | M0)},				/* gpmc_a24 */
+	{GPMC_A25, (IEN | PTD | DIS | M0)},				/* gpmc_a25 */
+	{GPMC_NCS0, (IDIS | PTU | EN | M0)},				/* gpmc_nsc0 */
+	{GPMC_NCS1, (IDIS | PTU | EN | M0)},				/* gpmc_nsc1 */
+	{GPMC_NCS2, (SAFE_MODE)},					/* nc */
+	{GPMC_NCS3, (SAFE_MODE)},					/* nc */
+	{GPMC_NWP, (IEN | PTD | DIS | M0)},				/* gpmc_nwp */
+	{GPMC_CLK, (SAFE_MODE)},					/* nc */
+	{GPMC_NADV_ALE, (IDIS | PTD | DIS | M0)},			/* gpmc_ndav_ale */
+	{GPMC_NOE, (IDIS | PTD | DIS | M0)},				/* gpmc_noe */
+	{GPMC_NWE, (IDIS | PTD | DIS | M0)},				/* gpmc_nwe */
+	{GPMC_NBE0_CLE, (IDIS | PTD | DIS | M0)},			/* gpmc_nbe0_cle */
+	{GPMC_NBE1, (SAFE_MODE)},					/* nc */
+	{GPMC_WAIT0, (IEN | PTU | EN | M0)},				/* gpmc_wait0 */
+	{GPMC_WAIT1, (SAFE_MODE)},					/* nc */
+	{C2C_DATA11, (SAFE_MODE)},					/* nc */
+	{C2C_DATA12, (SAFE_MODE)},					/* nc */
+	{C2C_DATA13, (IDIS | PTU | EN | M0)},				/* gpmc_nsc5 */
+	{C2C_DATA14, (SAFE_MODE)},					/* nc */
+	{C2C_DATA15, (SAFE_MODE)},					/* nc */
+	{HDMI_HPD, (SAFE_MODE)},					/* unused */
+	{HDMI_CEC, (SAFE_MODE)},					/* unused */
+	{HDMI_DDC_SCL, (SAFE_MODE)},					/* unused */
+	{HDMI_DDC_SDA, (SAFE_MODE)},					/* unused */
+	{CSI21_DX0, (SAFE_MODE)},					/* unused */
+	{CSI21_DY0, (SAFE_MODE)},					/* unused */
+	{CSI21_DX1, (SAFE_MODE)},					/* unused */
+	{CSI21_DY1, (SAFE_MODE)},					/* unused */
+	{CSI21_DX2, (SAFE_MODE)},					/* unused */
+	{CSI21_DY2, (SAFE_MODE)},					/* unused */
+	{CSI21_DX3, (SAFE_MODE)},					/* unused */
+	{CSI21_DY3, (SAFE_MODE)},					/* unused */
+	{CSI21_DX4, (SAFE_MODE)},					/* unused */
+	{CSI21_DY4, (SAFE_MODE)},					/* unused */
+	{CSI22_DX0, (SAFE_MODE)},					/* unused */
+	{CSI22_DY0, (SAFE_MODE)},					/* unused */
+	{CSI22_DX1, (SAFE_MODE)},					/* unused */
+	{CSI22_DY1, (SAFE_MODE)},					/* unused */
+	{CAM_SHUTTER, (SAFE_MODE)},					/* unused */
+	{CAM_STROBE, (SAFE_MODE)},					/* unused */
+	{CAM_GLOBALRESET, (SAFE_MODE)},					/* unused */
+	{USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
+	{USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)},		/* usbb1_ulpiphy_stp */
+	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dir */
+	{USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_nxt */
+	{USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat0 */
+	{USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat1 */
+	{USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat2 */
+	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat3 */
+	{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat4 */
+	{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat5 */
+	{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat6 */
+	{USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat7 */
+	{USBB1_HSIC_DATA, (SAFE_MODE)},					/* nc */
+	{USBB1_HSIC_STROBE, (SAFE_MODE)},				/* nc */
+	{USBC1_ICUSB_DP, (SAFE_MODE)},					/* unused */
+	{USBC1_ICUSB_DM, (SAFE_MODE)},					/* unused */
+	{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc1_clk */
+	{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_cmd */
+	{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat0 */
+	{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat1 */
+	{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat2 */
+	{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc1_dat3 */
+	{SDMMC1_DAT4, (SAFE_MODE)},					/* unused */
+	{SDMMC1_DAT5, (SAFE_MODE)},					/* unused */
+	{SDMMC1_DAT6, (SAFE_MODE)},					/* unused */
+	{SDMMC1_DAT7, (SAFE_MODE)},					/* unused */
+	{ABE_MCBSP2_CLKX, (SAFE_MODE)},					/* unused */
+	{ABE_MCBSP2_DR, (SAFE_MODE)},					/* unused */
+	{ABE_MCBSP2_DX, (SAFE_MODE)},					/* unused */
+	{ABE_MCBSP2_FSX, (SAFE_MODE)},					/* unused */
+	{ABE_MCBSP1_CLKX, (SAFE_MODE)},					/* unused */
+	{ABE_MCBSP1_DR, (SAFE_MODE)},					/* unused */
+	{ABE_MCBSP1_DX, (SAFE_MODE)},					/* unused */
+	{ABE_MCBSP1_FSX, (SAFE_MODE)},					/* unused */
+	{ABE_PDM_UL_DATA, (SAFE_MODE)},					/* unused */
+	{ABE_PDM_DL_DATA, (SAFE_MODE)},					/* unused */
+	{ABE_PDM_FRAME, (SAFE_MODE)},					/* unused */
+	{ABE_PDM_LB_CLK, (SAFE_MODE)},					/* unused */
+	{ABE_CLKS, (M3)},						/* gpio_118 */
+	{ABE_DMIC_CLK1, (SAFE_MODE)},					/* nc */
+	{ABE_DMIC_DIN1, (SAFE_MODE)},					/* unused */
+	{ABE_DMIC_DIN2, (DIS | IEN | M3)},				/* gpio_121 */
+	{ABE_DMIC_DIN3, (M3)},						/* gpio_122 */
+	{UART2_CTS, (SAFE_MODE)},					/* unused */
+	{UART2_RTS, (SAFE_MODE)},					/* unused */
+	{UART2_RX, (SAFE_MODE)},					/* unused */
+	{UART2_TX, (SAFE_MODE)},					/* unused */
+	{HDQ_SIO, (SAFE_MODE)},						/* unused */
+	{I2C1_SCL, (PTU | IEN | M0)},					/* i2c1_scl */
+	{I2C1_SDA, (PTU | IEN | M0)},					/* i2c1_sda */
+	{I2C2_SCL, (SAFE_MODE)},					/* unused */
+	{I2C2_SDA, (SAFE_MODE)},					/* unused */
+	{I2C3_SCL, (PTU | IEN | M0)},					/* i2c3_scl */
+	{I2C3_SDA, (PTU | IEN | M0)},					/* i2c3_sda */
+	{I2C4_SCL, (PTU | IEN | M0)},					/* i2c4_scl */
+	{I2C4_SDA, (PTU | IEN | M0)},					/* i2c4_sda */
+	{MCSPI1_CLK, (SAFE_MODE)},					/* unused */
+	{MCSPI1_SOMI, (SAFE_MODE)},					/* unused */
+	{MCSPI1_SIMO, (SAFE_MODE)},					/* unused */
+	{MCSPI1_CS0, (SAFE_MODE)},					/* unused */
+	{MCSPI1_CS1, (SAFE_MODE)},					/* unused */
+	{MCSPI1_CS2, (SAFE_MODE)},					/* unused */
+	{MCSPI1_CS3, (SAFE_MODE)},					/* unused */
+	{UART3_CTS_RCTX, (PTU | IEN | M0)},				/* uart3_tx */
+	{UART3_RTS_SD, (M0)},						/* uart3_rts_sd */
+	{UART3_RX_IRRX, (IEN | M0)},					/* uart3_rx */
+	{UART3_TX_IRTX, (M0)},						/* uart3_tx */
+	{SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc5_clk */
+	{SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_cmd */
+	{SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat0 */
+	{SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat1 */
+	{SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat2 */
+	{SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat3 */
+	{MCSPI4_CLK, (SAFE_MODE)},					/* nc */
+	{MCSPI4_SIMO, (PTU | IEN | M3)},				/* gpio_152 */
+	{MCSPI4_SOMI, (PTU | IEN | M3)},				/* gpio_153 */
+	{MCSPI4_CS0, (SAFE_MODE)},					/* nc */
+	{UART4_RX, (SAFE_MODE)},					/* unused */
+	{UART4_TX, (SAFE_MODE)},					/* unused */
+	{USBB2_ULPITLL_CLK, (SAFE_MODE)},				/* nc */
+	{USBB2_ULPITLL_STP, (M5)},					/* dispc2_data23 */
+	{USBB2_ULPITLL_DIR, (M5)},					/* dispc2_data22 */
+	{USBB2_ULPITLL_NXT, (M5)},					/* dispc2_data21 */
+	{USBB2_ULPITLL_DAT0, (M5)},					/* dispc2_data20 */
+	{USBB2_ULPITLL_DAT1, (M5)},					/* dispc2_data19 */
+	{USBB2_ULPITLL_DAT2, (M5)},					/* dispc2_data18 */
+	{USBB2_ULPITLL_DAT3, (M5)},					/* dispc2_data15 */
+	{USBB2_ULPITLL_DAT4, (M5)},					/* dispc2_data14 */
+	{USBB2_ULPITLL_DAT5, (M5)},					/* dispc2_data13 */
+	{USBB2_ULPITLL_DAT6, (M5)},					/* dispc2_data12 */
+	{USBB2_ULPITLL_DAT7, (M5)},					/* dispc2_data11 */
+	{USBB2_HSIC_DATA, (SAFE_MODE)},					/* nc */
+	{USBB2_HSIC_STROBE, (SAFE_MODE)},				/* nc */
+	{UNIPRO_TX0, (SAFE_MODE)},					/* unused */
+	{UNIPRO_TY0, (SAFE_MODE)},					/* unused */
+	{UNIPRO_TX1, (SAFE_MODE)},					/* unused */
+	{UNIPRO_TY1, (SAFE_MODE)},					/* unused */
+	{UNIPRO_TX2, (SAFE_MODE)},					/* unused */
+	{UNIPRO_TY2, (SAFE_MODE)},					/* unused */
+	{UNIPRO_RX0, (SAFE_MODE)},					/* unused */
+	{UNIPRO_RY0, (SAFE_MODE)},					/* unused */
+	{UNIPRO_RX1, (SAFE_MODE)},					/* unused */
+	{UNIPRO_RY1, (SAFE_MODE)},					/* unused */
+	{UNIPRO_RX2, (SAFE_MODE)},					/* unused */
+	{UNIPRO_RY2, (SAFE_MODE)},					/* unused */
+	{USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},	/* usba0_otg_ce */
+	{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dp */
+	{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dm */
+	{FREF_CLK1_OUT, (SAFE_MODE)},					/* nc */
+	{FREF_CLK2_OUT, (SAFE_MODE)},					/* nc */
+	{SYS_NIRQ1, (PTU | IEN | M0)},					/* sys_nirq1 */
+	{SYS_NIRQ2, (M0)},						/* sys_boot0 */
+	{SYS_BOOT0, (M0)},						/* sys_boot */
+	{SYS_BOOT1, (M0)},						/* sys_boot */
+	{SYS_BOOT2, (M0)},						/* sys_boot */
+	{SYS_BOOT3, (M0)},						/* sys_boot */
+	{SYS_BOOT4, (M0)},						/* sys_boot */
+	{SYS_BOOT5, (M0)},						/* sys_boot */
+	{DPM_EMU0, (IEN | M0)},						/* dpm_emu0 */
+	{DPM_EMU1, (IEN | M0)},						/* dpm_emu1 */
+	{DPM_EMU2, (SAFE_MODE)},					/* unused */
+	{DPM_EMU3, (M5)},						/* dispc2_data10 */
+	{DPM_EMU4, (M5)},						/* dispc2_data9 */
+	{DPM_EMU5, (M5)},						/* dispc2_data16 */
+	{DPM_EMU6, (M5)},						/* dispc2_data17 */
+	{DPM_EMU7, (M5)},						/* dispc2_hsync */
+	{DPM_EMU8, (M5)},						/* dispc2_pclk */
+	{DPM_EMU9, (M5)},						/* dispc2_vsync */
+	{DPM_EMU10, (M5)},						/* dispc2_de */
+	{DPM_EMU11, (M5)},						/* dispc2_data8 */
+	{DPM_EMU12, (M5)},						/* dispc2_data7 */
+	{DPM_EMU13, (M5)},						/* dispc2_data6 */
+	{DPM_EMU14, (M5)},						/* dispc2_data5 */
+	{DPM_EMU15, (M5)},						/* dispc2_data4 */
+	{DPM_EMU16, (M5)},						/* dispc2_data3 */
+	{DPM_EMU17, (M5)},						/* dispc2_data2 */
+	{DPM_EMU18, (M5)},						/* dispc2_data1 */
+	{DPM_EMU19, (M5)},						/* dispc2_data0 */
+};
+
+static const struct pad_conf_entry wkup_padconf_array[] = {
+	{GPIO_WK0, (SAFE_MODE)},		/* nc */
+	{GPIO_WK1, (SAFE_MODE)},		/* nc */
+	{GPIO_WK2, (SAFE_MODE)},		/* nc */
+	{GPIO_WK3, (SAFE_MODE)},		/* nc */
+	{GPIO_WK4, (SAFE_MODE)},		/* nc */
+	{SR_SCL, (PTU | IEN | M0)},		/* sr_scl */
+	{SR_SDA, (PTU | IEN | M0)},		/* sr_sda */
+	{FREF_XTAL_IN, (M0)},			/* # */
+	{FREF_SLICER_IN, (SAFE_MODE)},		/* nc */
+	{FREF_CLK_IOREQ, (SAFE_MODE)},		/* nc */
+	{FREF_CLK0_OUT, (M2)},			/* sys_drm_msecure */
+	{FREF_CLK3_REQ, (IEN | M3)},		/* gpio_wk30 */
+	{FREF_CLK3_OUT, (M0)},			/* fref_clk3_out */
+	{FREF_CLK4_REQ, (M0)},			/* fref_clk4_req */
+	{FREF_CLK4_OUT, (M0)},			/* fref_clk4_out */
+	{SYS_32K, (IEN | M0)},			/* sys_32k */
+	{SYS_NRESPWRON, (M0)},			/* sys_nrespwron */
+	{SYS_NRESWARM, (M0)},			/* sys_nreswarm */
+	{SYS_PWR_REQ, (PTU | M0)},		/* sys_pwr_req */
+	{SYS_PWRON_RESET_OUT, (M0)},		/* sys_pwron_reset_out */
+	{SYS_BOOT6, (M0)},			/* sys_boot6 */
+	{SYS_BOOT7, (M0)},			/* sys_boot7 */
+};
+
+void set_muxconf_regs(void)
+{
+	omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_CORE, core_padconf_array,
+			ARRAY_SIZE(core_padconf_array));
+
+	omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_WKUP, wkup_padconf_array,
+			ARRAY_SIZE(wkup_padconf_array));
+
+	/* gpio_182 is used for controlling TPS on 4460 */
+	if (omap4_revision() >= OMAP4460_ES1_0) {
+		writew(M3, OMAP44XX_CONTROL_PADCONF_CORE + FREF_CLK2_OUT);
+		/* Enable GPIO-1 clocks before TPS initialization */
+		omap4_enable_gpio_clocks();
+	}
+}