diff options
| author | Stefan Riedmueller <s.riedmueller@phytec.de> | 2018-12-05 16:40:37 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-12-06 09:09:40 +0100 |
| commit | 247ad6509db69b26b3513bec7d1481530938bb15 (patch) | |
| tree | 6918badcb246eb33b175be711a888f535b0eb84e /arch/arm/boards/phytec-som-imx6 | |
| parent | ca343ec8a2d09ab0708cb007ac0382960a31b218 (diff) | |
| download | barebox-247ad6509db69b26b3513bec7d1481530938bb15.tar.gz barebox-247ad6509db69b26b3513bec7d1481530938bb15.tar.xz | |
ARM: phytec-som-imx6: Add full featured phyCORE-i.MX 6ULL
The phyCORE-i.MX 6ULL now comes in a full featured (Y2 variant) and a
low cost (Y0 variant) version. The main difference for the barebox is
the missing second USB OTG port on the Y0 variant and the RAM configuration.
So to account for these differences the existing low cost version is
renamed and the full featured version added.
The results are following phyCORE-i.MX 6ULL modules:
phyCORE-i.MX 6ULL low cost:
- i.MX 6ULL Y0
- 256 MB RAM
- NAND
- Ethernet 10/100 MBits
- USB OTG
phyCORE-i.MX 6ULL full featured:
- i.MX 6ULL Y2
- 512 MB RAM
- NAND
- Ethernet 10/100 MBits
- USB OTG
- USB Host
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/boards/phytec-som-imx6')
| -rw-r--r-- | arch/arm/boards/phytec-som-imx6/lowlevel.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/boards/phytec-som-imx6/lowlevel.c b/arch/arm/boards/phytec-som-imx6/lowlevel.c index 05f918f6c9..9d81c278ca 100644 --- a/arch/arm/boards/phytec-som-imx6/lowlevel.c +++ b/arch/arm/boards/phytec-som-imx6/lowlevel.c @@ -116,4 +116,5 @@ PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_1gib, imx6q_phytec_phycore_som_ PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_2gib, imx6q_phytec_phycore_som_emmc, SZ_2G, true); PHYTEC_ENTRY(start_phytec_phycore_imx6ul_som_512mb, imx6ul_phytec_phycore_som, SZ_512M, false); -PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_256mb, imx6ull_phytec_phycore_som, SZ_256M, false); +PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_lc_256mb, imx6ull_phytec_phycore_som_lc, SZ_256M, false); +PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_512mb, imx6ull_phytec_phycore_som, SZ_512M, false); |