ARM: phyCORE-i.MX8M SOM support

The phyCORE-i.MX8M aka PCL-066 is a SoM containing a i.MX8M SoC.

phyCORE-i.MX8M:
 - 1GB LPDDR4 RAM
 - eMMC
 - microSD
 - Ethernet

Signed-off-by: Christian Hemp <christian.hemp@posteo.de>
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

1 files changed, 26 insertions, 0 deletions

diff --git a/arch/arm/boards/phytec-som-imx8mq/ddr.h b/arch/arm/boards/phytec-som-imx8mq/ddr.h
new file mode 100644
index 0000000000..18ae6e9022
--- /dev/null
+++ b/arch/arm/boards/phytec-som-imx8mq/ddr.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2018 Christian Hemp
+ *
+ * Varios wrappers and macros needed to intgrate code generated by
+ * i.MX8M DDR Tool into rest of Barebox
+ */
+#include <common.h>
+#include <io.h>
+#include <mach/imx8-ddrc.h>
+
+/*
+ * Code generated by i.MX8 M DDR Tool doesn't have any prefixes in the
+ * global identifiers below, so in order to avoid symbol name
+ * collisions with other boards we re-name them via a #define
+ */
+#define ddr_init	phytec_imx8mq_phycore_ddr_init
+#define ddr_cfg_phy	phytec_imx8mq_phycore_ddr_cfg_phy
+
+void phytec_imx8mq_phycore_ddr_init(void);
+void phytec_imx8mq_phycore_ddr_cfg_phy(void);
+
+#define FW_1D_IMAGE	lpddr4_pmu_train_1d_imem_bin, \
+			lpddr4_pmu_train_1d_dmem_bin
+#define FW_2D_IMAGE	lpddr4_pmu_train_2d_imem_bin, \
+			lpddr4_pmu_train_2d_dmem_bin