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author | Sascha Hauer <s.hauer@pengutronix.de> | 2019-07-16 12:42:09 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-07-16 15:19:26 +0200 |
commit | 468c4ecbfb015567eed627993558c4b0c631aad8 (patch) | |
tree | bbe9fbebec58532dca00f0f0251b2ffba0d25bff /arch/arm/boards/phytec-som-imx8mq/lowlevel.c | |
parent | ea8981915e1d3dffe651e8ce3049cd1f707c96a1 (diff) | |
download | barebox-468c4ecbfb015567eed627993558c4b0c631aad8.tar.gz barebox-468c4ecbfb015567eed627993558c4b0c631aad8.tar.xz |
ARM: phyCORE-i.MX8M SOM: Do setup_c() before accessing global variables
The lowlevel board code accesses global variables, so call
relocate_to_current_adr() / setup_c() to make sure we have a valid C
environment.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/boards/phytec-som-imx8mq/lowlevel.c')
-rw-r--r-- | arch/arm/boards/phytec-som-imx8mq/lowlevel.c | 53 |
1 files changed, 30 insertions, 23 deletions
diff --git a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c index e42e7a6fcc..4e52b92ad3 100644 --- a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c +++ b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c @@ -61,30 +61,8 @@ static void phytec_imx8mq_som_sram_setup(void) BUG_ON(ret); } -/* - * Power-on execution flow of start_phytec_phycore_imx8mq() might not be - * obvious for a very first read, so here's, hopefully helpful, - * summary: - * - * 1. MaskROM uploads PBL into OCRAM and that's where this function is - * executed for the first time - * - * 2. DDR is initialized and full i.MX image is loaded to the - * beginning of RAM - * - * 3. start_phytec_phycore_imx8mq, now in RAM, is executed again - * - * 4. BL31 blob is uploaded to OCRAM and the control is transfer to it - * - * 5. BL31 exits EL3 into EL2 at address MX8MQ_ATF_BL33_BASE_ADDR, - * executing start_phytec_phycore_imx8mq() the third time - * - * 6. Standard barebox boot flow continues - */ -ENTRY_FUNCTION(start_phytec_phycore_imx8mq, r0, r1, r2) +static __noreturn noinline void phytec_phycore_imx8mq_start(void) { - imx8mq_cpu_lowlevel_init(); - if (IS_ENABLED(CONFIG_DEBUG_LL)) setup_uart(); @@ -118,3 +96,32 @@ ENTRY_FUNCTION(start_phytec_phycore_imx8mq, r0, r1, r2) */ imx8mq_barebox_entry(__dtb_imx8mq_phytec_phycore_som_start); } + +/* + * Power-on execution flow of start_phytec_phycore_imx8mq() might not be + * obvious for a very first read, so here's, hopefully helpful, + * summary: + * + * 1. MaskROM uploads PBL into OCRAM and that's where this function is + * executed for the first time + * + * 2. DDR is initialized and full i.MX image is loaded to the + * beginning of RAM + * + * 3. start_phytec_phycore_imx8mq, now in RAM, is executed again + * + * 4. BL31 blob is uploaded to OCRAM and the control is transfer to it + * + * 5. BL31 exits EL3 into EL2 at address MX8MQ_ATF_BL33_BASE_ADDR, + * executing start_phytec_phycore_imx8mq() the third time + * + * 6. Standard barebox boot flow continues + */ +ENTRY_FUNCTION(start_phytec_phycore_imx8mq, r0, r1, r2) +{ + imx8mq_cpu_lowlevel_init(); + relocate_to_current_adr(); + setup_c(); + + phytec_phycore_imx8mq_start(); +} |