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author | Sascha Hauer <s.hauer@pengutronix.de> | 2020-02-14 11:53:38 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2020-02-19 08:30:32 +0100 |
commit | 0266042714b2e0a17e397fe5d8a29a4487785df4 (patch) | |
tree | 3ec6d49a15181e40d14ef2349afdbd84438acd2d /arch/arm/boards/phytec-som-imx8mq | |
parent | 5973ed7e2196aac7df53f81033cd46b51acba09c (diff) | |
download | barebox-0266042714b2e0a17e397fe5d8a29a4487785df4.tar.gz barebox-0266042714b2e0a17e397fe5d8a29a4487785df4.tar.xz |
ARM: i.MX8M: Add DDR controller support
This adds the DDR driver for the i.MX8MQ/i.MX8MM. It's taken from
U-Boot v2020.04-rc1 with slight modifications for barebox
The i.MX8MQ boards in the tree currently use the output of an earlier
version of the NXP i.MX8M DDR Tool which doesn't use a controller driver
but instead does most stuff in board code. It seems this can coexist
with the new driver, only a few helper functions that previously lived
in arch/arm/mach-imx/imx8-ddrc.c are now provided by the new driver.
Tested on an i.MX8MM EVK
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/boards/phytec-som-imx8mq')
-rw-r--r-- | arch/arm/boards/phytec-som-imx8mq/ddr.h | 7 | ||||
-rw-r--r-- | arch/arm/boards/phytec-som-imx8mq/ddrphy_train.c | 1 | ||||
-rw-r--r-- | arch/arm/boards/phytec-som-imx8mq/lowlevel.c | 2 |
3 files changed, 2 insertions, 8 deletions
diff --git a/arch/arm/boards/phytec-som-imx8mq/ddr.h b/arch/arm/boards/phytec-som-imx8mq/ddr.h index 18ae6e9022..e125feaaf0 100644 --- a/arch/arm/boards/phytec-som-imx8mq/ddr.h +++ b/arch/arm/boards/phytec-som-imx8mq/ddr.h @@ -7,7 +7,7 @@ */ #include <common.h> #include <io.h> -#include <mach/imx8-ddrc.h> +#include <soc/imx8m/ddr.h> /* * Code generated by i.MX8 M DDR Tool doesn't have any prefixes in the @@ -19,8 +19,3 @@ void phytec_imx8mq_phycore_ddr_init(void); void phytec_imx8mq_phycore_ddr_cfg_phy(void); - -#define FW_1D_IMAGE lpddr4_pmu_train_1d_imem_bin, \ - lpddr4_pmu_train_1d_dmem_bin -#define FW_2D_IMAGE lpddr4_pmu_train_2d_imem_bin, \ - lpddr4_pmu_train_2d_dmem_bin diff --git a/arch/arm/boards/phytec-som-imx8mq/ddrphy_train.c b/arch/arm/boards/phytec-som-imx8mq/ddrphy_train.c index 56af647821..cc00527649 100644 --- a/arch/arm/boards/phytec-som-imx8mq/ddrphy_train.c +++ b/arch/arm/boards/phytec-som-imx8mq/ddrphy_train.c @@ -9,7 +9,6 @@ #include "ddr.h" -extern void wait_ddrphy_training_complete(void); void ddr_cfg_phy(void) { unsigned int tmp, tmp_t; diff --git a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c index f460901a2c..f5b9b6c008 100644 --- a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c +++ b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c @@ -11,7 +11,7 @@ #include <asm/barebox-arm.h> #include <mach/imx8m-ccm-regs.h> #include <mach/iomux-mx8mq.h> -#include <mach/imx8-ddrc.h> +#include <soc/imx8m/ddr.h> #include <mach/xload.h> #include <io.h> #include <debug_ll.h> |