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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2019-09-09 14:18:09 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-10-01 22:34:08 +0200 |
| commit | c123df1fc8b57b52d81cc462c084eb0fb09a0d8a (patch) | |
| tree | 2a2be8e515b84d1036d4e8d8963e063c00a2189f /arch/arm/boards | |
| parent | 9d7a00bd45a0d7a4fc2110251916abb3dc555fd4 (diff) | |
| download | barebox-c123df1fc8b57b52d81cc462c084eb0fb09a0d8a.tar.gz barebox-c123df1fc8b57b52d81cc462c084eb0fb09a0d8a.tar.xz | |
ARM: drop bultin DTB
We can build multiple DTBs into the binary and board code can select
which one to use. Drop the single builtin DTB and let the boards using
it pass the correct one.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/boards')
| -rw-r--r-- | arch/arm/boards/canon-a1100/lowlevel.c | 9 | ||||
| -rw-r--r-- | arch/arm/boards/module-mb7707/lowlevel.c | 8 | ||||
| -rw-r--r-- | arch/arm/boards/versatile/lowlevel.c | 9 | ||||
| -rw-r--r-- | arch/arm/boards/virt2real/lowlevel.c | 8 |
4 files changed, 30 insertions, 4 deletions
diff --git a/arch/arm/boards/canon-a1100/lowlevel.c b/arch/arm/boards/canon-a1100/lowlevel.c index 744ce59eaa..b75a1bfa60 100644 --- a/arch/arm/boards/canon-a1100/lowlevel.c +++ b/arch/arm/boards/canon-a1100/lowlevel.c @@ -3,10 +3,16 @@ #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> +extern char __dtb_canon_a1100_start[]; + void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { + void *fdt; + arm_cpu_lowlevel_init(); + fdt = __dtb_canon_a1100_start + get_runtime_offset(); + /* FIXME: can we determine RAM size using CP15 register? * * see http://chdk.setepontos.com/index.php?topic=5980.90 @@ -19,5 +25,6 @@ void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) * The Control Register value (mrc p15, 0, %0, c0, c1, 4) * is 0x00051078. */ - barebox_arm_entry(0x0, SZ_64M, 0); + + barebox_arm_entry(0x0, SZ_64M, fdt); } diff --git a/arch/arm/boards/module-mb7707/lowlevel.c b/arch/arm/boards/module-mb7707/lowlevel.c index 055e432c1c..fc102e26e1 100644 --- a/arch/arm/boards/module-mb7707/lowlevel.c +++ b/arch/arm/boards/module-mb7707/lowlevel.c @@ -26,9 +26,15 @@ #define MB7707_SRAM_BASE 0x40000000 #define MB7707_SRAM_SIZE SZ_128M +extern char __dtb_module_mb7707_start[]; + void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { + void *fdt; + arm_cpu_lowlevel_init(); - barebox_arm_entry(MB7707_SRAM_BASE, MB7707_SRAM_SIZE, 0); + fdt = __dtb_module_mb7707_start + get_runtime_offset(); + + barebox_arm_entry(MB7707_SRAM_BASE, MB7707_SRAM_SIZE, fdt); } diff --git a/arch/arm/boards/versatile/lowlevel.c b/arch/arm/boards/versatile/lowlevel.c index a9ccf1fff5..beab04d234 100644 --- a/arch/arm/boards/versatile/lowlevel.c +++ b/arch/arm/boards/versatile/lowlevel.c @@ -3,8 +3,15 @@ #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> +extern char __dtb_versatile_pb_start[]; + void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { + void *fdt; + arm_cpu_lowlevel_init(); - barebox_arm_entry(0x0, SZ_64M, NULL); + + fdt = __dtb_versatile_pb_start + get_runtime_offset(); + + barebox_arm_entry(0x0, SZ_64M, fdt); } diff --git a/arch/arm/boards/virt2real/lowlevel.c b/arch/arm/boards/virt2real/lowlevel.c index 264ebee893..a72334bb0e 100644 --- a/arch/arm/boards/virt2real/lowlevel.c +++ b/arch/arm/boards/virt2real/lowlevel.c @@ -26,9 +26,15 @@ #define VIRT2REAL_SRAM_BASE 0x82000000 #define VIRT2REAL_SRAM_SIZE SZ_16M +extern char __dtb_virt2real_start[]; + void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { + void *fdt; + arm_cpu_lowlevel_init(); - barebox_arm_entry(VIRT2REAL_SRAM_BASE, VIRT2REAL_SRAM_SIZE, NULL); + fdt = __dtb_virt2real_start + get_runtime_offset(); + + barebox_arm_entry(VIRT2REAL_SRAM_BASE, VIRT2REAL_SRAM_SIZE, fdt); } |