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| author | Teresa Gámez <t.gamez@phytec.de> | 2014-09-04 08:50:39 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2014-09-09 09:52:53 +0200 |
| commit | d31480132cd94950a2f4e7d8f0fe162751f6acef (patch) | |
| tree | 383808755a8f8a83fbc23aab64f26913cb27c398 /arch/arm/boards | |
| parent | af6aa727672f475cdba713c0041fbc3f47c1bead (diff) | |
| download | barebox-d31480132cd94950a2f4e7d8f0fe162751f6acef.tar.gz barebox-d31480132cd94950a2f4e7d8f0fe162751f6acef.tar.xz | |
ARM: phyCORE-AM335x: Add support for 2x512MB RAM
Added settings for 1GB RAM option.
Signed-off-by: Teresa Gámez <t.gamez@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/boards')
| -rw-r--r-- | arch/arm/boards/phytec-phycore-am335x/lowlevel.c | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/arm/boards/phytec-phycore-am335x/lowlevel.c b/arch/arm/boards/phytec-phycore-am335x/lowlevel.c index a15e151b05..66bae806c4 100644 --- a/arch/arm/boards/phytec-phycore-am335x/lowlevel.c +++ b/arch/arm/boards/phytec-phycore-am335x/lowlevel.c @@ -36,6 +36,7 @@ enum { MT41J128M16125IT_256MB, MT41J64M1615IT_128MB, MT41J256M16HA15EIT_512MB, + MT41J512M8125IT_2x512MB, }; struct pcm051_sdram_timings timings[] = { @@ -95,6 +96,25 @@ struct pcm051_sdram_timings timings[] = { .wr_slave_ratio0 = 0x7b, }, }, + + /* 1024MB */ + [MT41J512M8125IT_2x512MB] = { + .regs = { + .emif_read_latency = 0x7, + .emif_tim1 = 0x0AAAE4DB, + .emif_tim2 = 0x266B7FDA, + .emif_tim3 = 0x501F867F, + .sdram_config = 0x61C053B2, + .zq_config = 0x50074BE4, + .sdram_ref_ctrl = 0x00000C30 + }, + .data = { + .rd_slave_ratio0 = 0x32, + .wr_dqs_slave_ratio0 = 0x48, + .fifo_we_slave_ratio0 = 0x99, + .wr_slave_ratio0 = 0x80, + }, + }, }; extern char __dtb_am335x_phytec_phycore_start[]; @@ -169,6 +189,11 @@ ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_512mb, bootinfo, r1, r2) pcm051_board_entry(bootinfo, MT41J256M16HA15EIT_512MB); } +ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_2x512mb, bootinfo, r1, r2) +{ + pcm051_board_entry(bootinfo, MT41J512M8125IT_2x512MB); +} + ENTRY_FUNCTION(start_am33xx_phytec_phycore_sdram, r0, r1, r2) { void *fdt; |