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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2012-09-28 00:14:14 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2012-10-13 11:19:13 +0200 |
| commit | 1dbfd5ed82fd2b6b0ba6df98e2e23aaf3cd1a197 (patch) | |
| tree | 3214217a66047c49aaa48ea3e860dec9ac7899bb /arch/arm/cpu/cache-armv4.S | |
| parent | 3d76ff9aeada3607e913e4627237c6fd7b5acc05 (diff) | |
| download | barebox-1dbfd5ed82fd2b6b0ba6df98e2e23aaf3cd1a197.tar.gz barebox-1dbfd5ed82fd2b6b0ba6df98e2e23aaf3cd1a197.tar.xz | |
ARM: Support multiple ARM architectures
The different ARM architectures need different cache functions. This
patch makes them selectable during runtime.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/cpu/cache-armv4.S')
| -rw-r--r-- | arch/arm/cpu/cache-armv4.S | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/arch/arm/cpu/cache-armv4.S b/arch/arm/cpu/cache-armv4.S index 22fab1455c..1d1a1e32bf 100644 --- a/arch/arm/cpu/cache-armv4.S +++ b/arch/arm/cpu/cache-armv4.S @@ -4,7 +4,7 @@ #define CACHE_DLINESIZE 32 .section .text.__mmu_cache_on -ENTRY(__mmu_cache_on) +ENTRY(v4_mmu_cache_on) mov r12, lr #ifdef CONFIG_MMU mov r0, #0 @@ -21,7 +21,7 @@ ENTRY(__mmu_cache_on) mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs #endif mov pc, r12 -ENDPROC(__mmu_cache_on) +ENDPROC(v4_mmu_cache_on) __common_mmu_cache_on: orr r0, r0, #0x000d @ Write buffer, mmu @@ -31,8 +31,8 @@ __common_mmu_cache_on: mrc p15, 0, r0, c1, c0, 0 @ and read it back to sub pc, lr, r0, lsr #32 @ properly flush pipeline -.section .text.__mmu_cache_off -ENTRY(__mmu_cache_off) +.section .text.v4_mmu_cache_off +ENTRY(v4_mmu_cache_off) #ifdef CONFIG_MMU mrc p15, 0, r0, c1, c0 bic r0, r0, #0x000d @@ -42,10 +42,10 @@ ENTRY(__mmu_cache_off) mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4 #endif mov pc, lr -ENDPROC(__mmu_cache_off) +ENDPROC(v4_mmu_cache_off) -.section .text.__mmu_cache_flush -ENTRY(__mmu_cache_flush) +.section .text.v4_mmu_cache_flush +ENTRY(v4_mmu_cache_flush) stmfd sp!, {r6, r11, lr} mrc p15, 0, r6, c0, c0 @ get processor ID mov r2, #64*1024 @ default: 32K dcache size (*2) @@ -76,7 +76,7 @@ no_cache_id: mcr p15, 0, r1, c7, c6, 0 @ flush D cache mcr p15, 0, r1, c7, c10, 4 @ drain WB ldmfd sp!, {r6, r11, pc} -ENDPROC(__mmu_cache_flush) +ENDPROC(v4_mmu_cache_flush) /* * dma_inv_range(start, end) @@ -91,8 +91,8 @@ ENDPROC(__mmu_cache_flush) * * (same as v4wb) */ -.section .text.__dma_inv_range -ENTRY(__dma_inv_range) +.section .text.v4_dma_inv_range +ENTRY(v4_dma_inv_range) tst r0, #CACHE_DLINESIZE - 1 bic r0, r0, #CACHE_DLINESIZE - 1 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry @@ -115,8 +115,8 @@ ENTRY(__dma_inv_range) * * (same as v4wb) */ -.section .text.__dma_clean_range -ENTRY(__dma_clean_range) +.section .text.v4_dma_clean_range +ENTRY(v4_dma_clean_range) bic r0, r0, #CACHE_DLINESIZE - 1 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry add r0, r0, #CACHE_DLINESIZE @@ -133,8 +133,8 @@ ENTRY(__dma_clean_range) * - start - virtual start address * - end - virtual end address */ -.section .text.__dma_flush_range -ENTRY(__dma_flush_range) +.section .text.v4_dma_flush_range +ENTRY(v4_dma_flush_range) bic r0, r0, #CACHE_DLINESIZE - 1 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry add r0, r0, #CACHE_DLINESIZE |