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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2012-07-09 09:05:37 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2012-07-23 23:57:44 +0200 |
| commit | 7c3e50c83db91e2a8679c8e7fc3e77c091c20697 (patch) | |
| tree | 43f4ae5cd1e1b0a0e246405fadf47f9f276b9ba6 /arch/arm/cpu/cache-armv4.S | |
| parent | 244198ea8bdf592799ebfd430fe9ab165284e480 (diff) | |
| download | barebox-7c3e50c83db91e2a8679c8e7fc3e77c091c20697.tar.gz barebox-7c3e50c83db91e2a8679c8e7fc3e77c091c20697.tar.xz | |
ARM: Separate assembler functions into their own section
To let the linker remove unused functions.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/cpu/cache-armv4.S')
| -rw-r--r-- | arch/arm/cpu/cache-armv4.S | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/arm/cpu/cache-armv4.S b/arch/arm/cpu/cache-armv4.S index 6d03565c58..2231eee06b 100644 --- a/arch/arm/cpu/cache-armv4.S +++ b/arch/arm/cpu/cache-armv4.S @@ -3,6 +3,7 @@ #define CACHE_DLINESIZE 32 +.section .text.__mmu_cache_on ENTRY(__mmu_cache_on) mov r12, lr #ifdef CONFIG_MMU @@ -30,6 +31,7 @@ __common_mmu_cache_on: mrc p15, 0, r0, c1, c0, 0 @ and read it back to sub pc, lr, r0, lsr #32 @ properly flush pipeline +.section .text.__mmu_cache_off ENTRY(__mmu_cache_off) #ifdef CONFIG_MMU mrc p15, 0, r0, c1, c0 @@ -42,6 +44,7 @@ ENTRY(__mmu_cache_off) mov pc, lr ENDPROC(__mmu_cache_off) +.section .text.__mmu_cache_flush ENTRY(__mmu_cache_flush) mrc p15, 0, r6, c0, c0 @ get processor ID mov r2, #64*1024 @ default: 32K dcache size (*2) @@ -74,7 +77,6 @@ no_cache_id: mov pc, lr ENDPROC(__mmu_cache_flush) -.section ".text.text" /* * dma_inv_range(start, end) * @@ -88,6 +90,7 @@ ENDPROC(__mmu_cache_flush) * * (same as v4wb) */ +.section .text.__dma_inv_range ENTRY(__dma_inv_range) tst r0, #CACHE_DLINESIZE - 1 bic r0, r0, #CACHE_DLINESIZE - 1 @@ -111,6 +114,7 @@ ENTRY(__dma_inv_range) * * (same as v4wb) */ +.section .text.__dma_clean_range ENTRY(__dma_clean_range) bic r0, r0, #CACHE_DLINESIZE - 1 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry @@ -128,6 +132,7 @@ ENTRY(__dma_clean_range) * - start - virtual start address * - end - virtual end address */ +.section .text.__dma_flush_range ENTRY(__dma_flush_range) bic r0, r0, #CACHE_DLINESIZE - 1 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry |