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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2010-03-30 10:57:38 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2010-03-30 14:15:04 +0200 |
| commit | bcaabae0f622ed80c9dc34ad671d4f75e6596d9d (patch) | |
| tree | fe8e9cb2e09e6bf45d025fb9776d598d21af367f /arch/arm/cpu/cache-armv4.S | |
| parent | 6f5a6b591a0cf20caf8fc9c15b271ed59984dbbb (diff) | |
| download | barebox-bcaabae0f622ed80c9dc34ad671d4f75e6596d9d.tar.gz barebox-bcaabae0f622ed80c9dc34ad671d4f75e6596d9d.tar.xz | |
ARM: Add a wrapper around dma_* functions
This is a preparation to add second level cache support.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/cpu/cache-armv4.S')
| -rw-r--r-- | arch/arm/cpu/cache-armv4.S | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/cpu/cache-armv4.S b/arch/arm/cpu/cache-armv4.S index a0ab256017..a79cc27789 100644 --- a/arch/arm/cpu/cache-armv4.S +++ b/arch/arm/cpu/cache-armv4.S @@ -86,7 +86,7 @@ ENDPROC(__mmu_cache_flush) * * (same as v4wb) */ -ENTRY(dma_inv_range) +ENTRY(__dma_inv_range) tst r0, #CACHE_DLINESIZE - 1 bic r0, r0, #CACHE_DLINESIZE - 1 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry @@ -109,7 +109,7 @@ ENTRY(dma_inv_range) * * (same as v4wb) */ -ENTRY(dma_clean_range) +ENTRY(__dma_clean_range) bic r0, r0, #CACHE_DLINESIZE - 1 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry add r0, r0, #CACHE_DLINESIZE @@ -126,7 +126,7 @@ ENTRY(dma_clean_range) * - start - virtual start address * - end - virtual end address */ -ENTRY(dma_flush_range) +ENTRY(__dma_flush_range) bic r0, r0, #CACHE_DLINESIZE - 1 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry add r0, r0, #CACHE_DLINESIZE |