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authorJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2010-09-12 13:30:04 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2010-09-20 08:56:37 +0200
commite34c1d4fccda53fe7f83dba57d1102e4ba2baf91 (patch)
treebb8342665df55a147fcae0844143aa5500deddaf /arch/arm/cpu/cache-armv4.S
parent427c6085838cb52bf71c316a2c7b5630e94c65f8 (diff)
downloadbarebox-e34c1d4fccda53fe7f83dba57d1102e4ba2baf91.tar.gz
barebox-e34c1d4fccda53fe7f83dba57d1102e4ba2baf91.tar.xz
init: introduce __BARE_INIT for .section ".text_bare_init.text"
and make init.h availlable for assembly too Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/cpu/cache-armv4.S')
-rw-r--r--arch/arm/cpu/cache-armv4.S3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/cpu/cache-armv4.S b/arch/arm/cpu/cache-armv4.S
index 3cec4dd9af..fc53653c34 100644
--- a/arch/arm/cpu/cache-armv4.S
+++ b/arch/arm/cpu/cache-armv4.S
@@ -1,4 +1,5 @@
#include <linux/linkage.h>
+#include <init.h>
#define CACHE_DLINESIZE 32
@@ -41,7 +42,7 @@ ENTRY(__mmu_cache_off)
mov pc, lr
ENDPROC(__mmu_cache_off)
-.section ".text_bare_init.text"
+__BARE_INIT
ENTRY(__mmu_cache_flush)
mrc p15, 0, r6, c0, c0 @ get processor ID
mov r2, #64*1024 @ default: 32K dcache size (*2)