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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2012-01-16 09:33:16 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2012-01-17 18:50:55 +0100 |
| commit | 0073723f154c0929e3f95293cb99e0c5cfa75aca (patch) | |
| tree | 30adcf3ae3cec9520a294a6c9ed777fcacb10436 /arch/arm/cpu/cache-armv7.S | |
| parent | 8b99fe89561489731895b71919a57e1ee933512a (diff) | |
| download | barebox-0073723f154c0929e3f95293cb99e0c5cfa75aca.tar.gz barebox-0073723f154c0929e3f95293cb99e0c5cfa75aca.tar.xz | |
ARM cache-armv7: Add additional ISB
At least OMAP3 needs this to properly work with MMU.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/cpu/cache-armv7.S')
| -rw-r--r-- | arch/arm/cpu/cache-armv7.S | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/cpu/cache-armv7.S b/arch/arm/cpu/cache-armv7.S index f25dcfaa57..416498d329 100644 --- a/arch/arm/cpu/cache-armv7.S +++ b/arch/arm/cpu/cache-armv7.S @@ -22,6 +22,7 @@ ENTRY(__mmu_cache_on) movne r1, #-1 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control #endif + mcr p15, 0, r0, c7, c5, 4 @ ISB mcr p15, 0, r0, c1, c0, 0 @ load control register mrc p15, 0, r0, c1, c0, 0 @ and read it back mov r0, #0 |