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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2015-08-07 14:24:54 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2015-08-07 15:34:02 +0200 |
| commit | 9a56bfa95d3ca167fba04eacc0421c39efbbdd8a (patch) | |
| tree | 13e9600c72f3de3f9aac7ca199b676975fb3d916 /arch/arm/cpu/mmu.c | |
| parent | 3086fd8bb43ae6350d057e8a1534cfcc2f7f7558 (diff) | |
| download | barebox-9a56bfa95d3ca167fba04eacc0421c39efbbdd8a.tar.gz barebox-9a56bfa95d3ca167fba04eacc0421c39efbbdd8a.tar.xz | |
ARM: MMU: Fix order when flushing inner/outer cache
When flushing the cache L1 has to be flushed before L2, not the
other way round.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/cpu/mmu.c')
| -rw-r--r-- | arch/arm/cpu/mmu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c index 37bfa058a5..1bd6080f5c 100644 --- a/arch/arm/cpu/mmu.c +++ b/arch/arm/cpu/mmu.c @@ -159,9 +159,9 @@ static u32 *find_pte(unsigned long adr) static void dma_flush_range(unsigned long start, unsigned long end) { + __dma_flush_range(start, end); if (outer_cache.flush_range) outer_cache.flush_range(start, end); - __dma_flush_range(start, end); } static void dma_inv_range(unsigned long start, unsigned long end) |