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| author | Ahmad Fatoum <a.fatoum@pengutronix.de> | 2019-10-08 16:46:28 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-10-14 15:26:46 +0200 |
| commit | 843b24bf6d569647f85f69942e3db1940a54f26c (patch) | |
| tree | 45c2d35b95bc388a279b3f1bb780537e487d6a6d /arch/arm/cpu | |
| parent | 0c7a656ab0febcce6d9d8d3a15a11d0ee9a38436 (diff) | |
| download | barebox-843b24bf6d569647f85f69942e3db1940a54f26c.tar.gz barebox-843b24bf6d569647f85f69942e3db1940a54f26c.tar.xz | |
ARM: cache-armv7: remove superfluous instruction
There are two tst r11, #0xf with nothing in between them that changes
r11. This a left over from the kernel code that checks for VMSA twice,
once to check if the page table should be setup and once to more to
flush the TLB. We do the setup in the caller already, so the tst serves
no useful purpose. Delete one.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/cache-armv7.S | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/arm/cpu/cache-armv7.S b/arch/arm/cpu/cache-armv7.S index 6a8aff8bb1..43ec902133 100644 --- a/arch/arm/cpu/cache-armv7.S +++ b/arch/arm/cpu/cache-armv7.S @@ -7,7 +7,6 @@ ENTRY(v7_mmu_cache_on) mov r12, lr #ifdef CONFIG_MMU mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0 - tst r11, #0xf @ VMSA mov r0, #0 dsb @ drain write buffer tst r11, #0xf @ VMSA |