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| author | Andrey Smirnov <andrew.smirnov@gmail.com> | 2019-04-23 23:32:48 -0700 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-04-26 07:40:05 +0200 |
| commit | cd6e1857a6a824d562bd27379d191602c074f6b7 (patch) | |
| tree | 64fc20de60367fa2b20ef8f0686eadfcf29913cd /arch/arm/cpu | |
| parent | ea569a0afd6a2e9a84418cd18ddeaeefaa5eae39 (diff) | |
| download | barebox-cd6e1857a6a824d562bd27379d191602c074f6b7.tar.gz barebox-cd6e1857a6a824d562bd27379d191602c074f6b7.tar.xz | |
ARM: aarch64: lowlevel: Reset SCTLR_EL3 in arm_cpu_lowlevel_init()
There's no guarantee that when arm_cpu_lowlevel_init() runs at EL3,
SCTLR will be in a state we expect it to be. Add code to reset it to a
known state, so we'd always start form clean slate. This is also
matches what we've been doing non 64-bit ARMs.
Real word motivation for this patch is i.MX8MQ whose rev 2.1 silicon
appear to have different mask ROM behaviour where it now leaves MMU
enabled if no valid boot source is found. Page table it sets up
doesn't include DDR range, so trying to bootstrap the device via
JTAG/OpenOCD results in an abort.
The value for SCTLR_ELx_FLAGS was taken from Linux kernel.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/lowlevel_64.S | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/cpu/lowlevel_64.S b/arch/arm/cpu/lowlevel_64.S index af1cd8b5bc..6a23132ed1 100644 --- a/arch/arm/cpu/lowlevel_64.S +++ b/arch/arm/cpu/lowlevel_64.S @@ -12,6 +12,13 @@ ENTRY(arm_cpu_lowlevel_init) orr x0, x0, #(1 << 10) /* 64-bit EL2 */ msr scr_el3, x0 msr cptr_el3, xzr + + mrs x0, sctlr_el3 + ldr x1, =SCTLR_ELx_FLAGS + bic x0, x0, x1 + msr sctlr_el3, x0 + isb + b done 2: |