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| author | Andrey Smirnov <andrew.smirnov@gmail.com> | 2018-08-25 14:03:15 -0700 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-09-04 08:33:51 +0200 |
| commit | ad37499caa8784f4c0432df9eb16ea413b22e85a (patch) | |
| tree | 5c8854d4bea4584c7dbeb7f1b89a89539338ff2b /arch/arm/dts/imx51-zii-rdu1.dts | |
| parent | 13ebcc4a77ccc9f2cccf162fa62810824402e031 (diff) | |
| download | barebox-ad37499caa8784f4c0432df9eb16ea413b22e85a.tar.gz barebox-ad37499caa8784f4c0432df9eb16ea413b22e85a.tar.xz | |
ARM: imx51-zii-rdu1: Add USBH1,2 iomux configuration
Add iomux configuration for USBH1,2 to match what U-Boot (as well as
Babbage board) would configure those pads to.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/dts/imx51-zii-rdu1.dts')
| -rw-r--r-- | arch/arm/dts/imx51-zii-rdu1.dts | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/arch/arm/dts/imx51-zii-rdu1.dts b/arch/arm/dts/imx51-zii-rdu1.dts index 979c4c9de6..bde565fe08 100644 --- a/arch/arm/dts/imx51-zii-rdu1.dts +++ b/arch/arm/dts/imx51-zii-rdu1.dts @@ -86,3 +86,45 @@ }; }; }; + +&iomuxc { + pinctrl_usbh1: usbh1grp { + + /* + * Overwrite upstream USBH1,2 iomux settings to match + * the setting U-Boot would set these to. Remove this + * once this is fixed upstream. + */ + fsl,pins = < + MX51_PAD_USBH1_STP__USBH1_STP 0x1e5 + MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5 + MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5 + MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5 + MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5 + MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5 + MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5 + MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5 + MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5 + MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5 + MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5 + MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5 + >; + }; + + pinctrl_usbh2: usbh2grp { + fsl,pins = < + MX51_PAD_EIM_A26__USBH2_STP 0x1e5 + MX51_PAD_EIM_A24__USBH2_CLK 0x1e5 + MX51_PAD_EIM_A25__USBH2_DIR 0x1e5 + MX51_PAD_EIM_A27__USBH2_NXT 0x1e5 + MX51_PAD_EIM_D16__USBH2_DATA0 0x1e5 + MX51_PAD_EIM_D17__USBH2_DATA1 0x1e5 + MX51_PAD_EIM_D18__USBH2_DATA2 0x1e5 + MX51_PAD_EIM_D19__USBH2_DATA3 0x1e5 + MX51_PAD_EIM_D20__USBH2_DATA4 0x1e5 + MX51_PAD_EIM_D21__USBH2_DATA5 0x1e5 + MX51_PAD_EIM_D22__USBH2_DATA6 0x1e5 + MX51_PAD_EIM_D23__USBH2_DATA7 0x1e5 + >; + }; +}; |