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| author | Andrey Smirnov <andrew.smirnov@gmail.com> | 2019-01-30 11:47:48 -0800 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-02-11 10:37:34 +0100 |
| commit | ecff6c2110d6b247200a46567edafdff10c87ee1 (patch) | |
| tree | fd503023a29bd489c13b7bfd6bb3c6c0d2709be4 /arch/arm/dts/imx8mq-zii-ultra-rmb3.dts | |
| parent | bcb1e5420cc176cef5c1e2154e0a29894342a28d (diff) | |
| download | barebox-ecff6c2110d6b247200a46567edafdff10c87ee1.tar.gz barebox-ecff6c2110d6b247200a46567edafdff10c87ee1.tar.xz | |
ARM: i.MX: Add support for ZII i.MX8MQ based devices
Add support for the following ZII i.MX8MQ based boards:
- ZII i.MX8MQ RMB3
- ZII i.MX8MQ Zest
Most of the basic peripherals are supported by this patch. More
advanced features such as PCIe, display support, etc, are planned to
be added later.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/dts/imx8mq-zii-ultra-rmb3.dts')
| -rw-r--r-- | arch/arm/dts/imx8mq-zii-ultra-rmb3.dts | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/arch/arm/dts/imx8mq-zii-ultra-rmb3.dts b/arch/arm/dts/imx8mq-zii-ultra-rmb3.dts new file mode 100644 index 0000000000..b2b3a560b5 --- /dev/null +++ b/arch/arm/dts/imx8mq-zii-ultra-rmb3.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2019 Zodiac Inflight Innovations + */ + +/dts-v1/; + +#include "imx8mq-zii-ultra.dtsi" + +/ { + model = "ZII i.MX8MQ Ultra RMB3 Board"; + compatible = "zii,imx8mq-ultra-rmb3", "zii,imx8mq-ultra", "fsl,imx8mq"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + nor_flash: flash@0 { + compatible = "st,m25p128", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 + MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 + MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 + MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 + >; + }; +}; |