Merge branch 'for-next/socfpga'

1 files changed, 124 insertions, 0 deletions

diff --git a/arch/arm/dts/socfpga_arria10_achilles.dts b/arch/arm/dts/socfpga_arria10_achilles.dts
new file mode 100644
index 0000000000..dd991318e2
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_achilles.dts
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2015 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/dts-v1/;
+#include <arm/socfpga_arria10.dtsi>
+
+/ {
+	model = "Reflex SOCFPGA Arria 10 Achilles";
+	compatible = "reflex,achilles", "altr,socfpga-arria10", "altr,socfpga";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		linux,stdout-path = &uart0;
+
+		environment@0 {
+			compatible = "barebox,environment";
+			device-path = &mmc, "partname:1";
+			file-path = "barebox.env";
+		};
+	};
+
+	memory {
+		name = "memory";
+		device_type = "memory";
+		reg = <0x0 0xc0000000>;
+	};
+
+	soc {
+		clkmgr@ffd04000 {
+			clocks {
+				osc1 {
+					clock-frequency = <25000000>;
+				};
+
+				cb_intosc_hs_div2_clk {
+					clock-frequency = <0>;
+				};
+				cb_intosc_ls_clk {
+					clock-frequency = <60000000>;
+				};
+				f2s_free_clk {
+					clock-frequency = <200000000>;
+				};
+			};
+		};
+	};
+};
+
+&gmac1 {
+	phy-mode = "rgmii";
+	phy-addr = <0x00fffff0>; /* probe for phy addr */
+
+	/*
+	 * These skews assume the user's FPGA design is adding 600ps of delay
+	 * for TX_CLK on Arria 10.
+	 *
+	 * All skews are offset since hardware skew values for the ksz9031
+	 * range from a negative skew to a positive skew.
+	 * See the micrel-ksz90x1.txt Documentation file for details.
+	 */
+	txd0-skew-ps = <0>; /* -420ps */
+	txd1-skew-ps = <0>; /* -420ps */
+	txd2-skew-ps = <0>; /* -420ps */
+	txd3-skew-ps = <0>; /* -420ps */
+	rxd0-skew-ps = <420>; /* 0ps */
+	rxd1-skew-ps = <420>; /* 0ps */
+	rxd2-skew-ps = <420>; /* 0ps */
+	rxd3-skew-ps = <420>; /* 0ps */
+	txen-skew-ps = <0>; /* -420ps */
+	txc-skew-ps = <1860>; /* 960ps */
+	rxdv-skew-ps = <420>; /* 0ps */
+	rxc-skew-ps = <1680>; /* 780ps */
+	max-frame-size = <3800>;
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	tempsensor: ti,tmp102@0x48 {
+		compatible = "ti,tmp102";
+		reg = <0x48>;
+	};
+
+	rtc: nxp,pcf8563@0x51 {
+		compatible = "nxp,pcf8563";
+		reg = <0x51>;
+	};
+
+	eeprom: at24@0x54 {
+		compatible = "at24";
+		reg = <0x54>;
+		bytelen = <256>;
+		pagesize = <16>;
+	};
+};
+
+&mmc {
+	supports-highspeed;
+	broken-cd;
+	bus-width = <1>;
+	status = "okay";
+};
+
+&uart0 {
+	reg-io-width = <4>;
+	status = "okay";
+};