diff options
| author | Marco Felsch <m.felsch@pengutronix.de> | 2021-01-18 21:29:19 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2021-01-19 11:00:55 +0100 |
| commit | 9345f2baeec46cdec5fbd020cc5c6d739c7d7562 (patch) | |
| tree | 864418b9f01eb0eeb58e5ed1788e511e51c4509c /arch/arm/dts | |
| parent | 2636cd7e5be372ea7a72f06c7027356b269dcc66 (diff) | |
| download | barebox-9345f2baeec46cdec5fbd020cc5c6d739c7d7562.tar.gz barebox-9345f2baeec46cdec5fbd020cc5c6d739c7d7562.tar.xz | |
ARM: dts: imx6qdl-smarc-samx6i: remove iomuxc hog
Move the muxing into the gpioX nodes so we can get rid of the iomuxc
hog. While on it set the correct mux config and don't rely on the reset
value.
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/dts')
| -rw-r--r-- | arch/arm/dts/imx6qdl-smarc-samx6i.dtsi | 37 |
1 files changed, 25 insertions, 12 deletions
diff --git a/arch/arm/dts/imx6qdl-smarc-samx6i.dtsi b/arch/arm/dts/imx6qdl-smarc-samx6i.dtsi index 363da66ec7..1381a551d0 100644 --- a/arch/arm/dts/imx6qdl-smarc-samx6i.dtsi +++ b/arch/arm/dts/imx6qdl-smarc-samx6i.dtsi @@ -129,6 +129,16 @@ status = "okay"; }; +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio2_hog>; +}; + +&gpio6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio6_hog>; +}; + &i2c_pfuze { pfuze100@08 { compatible = "fsl,pfuze100"; @@ -352,18 +362,6 @@ }; &iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_boot>; - - pinctrl_boot: boot { - fsl,pins = < - /* GPIOS for version and id detection */ - MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 - MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x80000000 - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 - >; - }; - pinctrl_flexcan1: flexcan1-smarc { fsl,pins = < MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000 @@ -378,6 +376,21 @@ >; }; + pinctrl_gpio2_hog: gpio2-hog { + fsl,pins = < + /* GPIO for version detection */ + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0xb0b0 + >; + }; + + pinctrl_gpio6_hog: gpio6-hog { + fsl,pins = < + /* GPIOs for ddr3 size detection */ + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0xb0b0 + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0xb0b0 + >; + }; + pinctrl_enet_smarc: fecgrp-smarc { fsl,pins = < MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 |