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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2018-03-08 12:29:31 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-03-23 07:43:27 +0100 |
| commit | 19e85c9fa75b1efc1374321729334ad93dbaa562 (patch) | |
| tree | 6375dae782d06ceb82820f8a8db46c5775c76c3b /arch/arm/include | |
| parent | 3d0fdf6c60cc4e52842cac8977a06a19b6fc5301 (diff) | |
| download | barebox-19e85c9fa75b1efc1374321729334ad93dbaa562.tar.gz barebox-19e85c9fa75b1efc1374321729334ad93dbaa562.tar.xz | |
ARM: aarch64: mmu: Fix mair register setting
The memory attributes register contains the memory attribute settings
for the corresponding to the possible AttrIndx values in the page
table entries. Passing UNCACHED_MEM makes no sense here, pass the
desired attributes instead.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/pgtable64.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/include/asm/pgtable64.h b/arch/arm/include/asm/pgtable64.h index 20bea5b28a..7f7efa10ca 100644 --- a/arch/arm/include/asm/pgtable64.h +++ b/arch/arm/include/asm/pgtable64.h @@ -109,6 +109,13 @@ #define MT_NORMAL 4 #define MT_NORMAL_WT 5 +#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_nGnRnE * 8)) | \ + (0x04 << (MT_DEVICE_nGnRE * 8)) | \ + (0x0c << (MT_DEVICE_GRE * 8)) | \ + (0x44 << (MT_NORMAL_NC * 8)) | \ + (UL(0xff) << (MT_NORMAL * 8)) | \ + (UL(0xbb) << (MT_NORMAL_WT * 8))) + /* * TCR flags. */ |