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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2017-09-27 09:51:22 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2017-10-17 08:39:36 +0200 |
| commit | fbcdca885d2f3597dafce640820ec2675a9f25b1 (patch) | |
| tree | 9b9c0a4d37e49298ed5bf770810573ba9baae834 /arch/arm/include | |
| parent | 857f60c1c6b588588508e52c4270007fe74fa6ec (diff) | |
| download | barebox-fbcdca885d2f3597dafce640820ec2675a9f25b1.tar.gz barebox-fbcdca885d2f3597dafce640820ec2675a9f25b1.tar.xz | |
ARM: i.MX6ul: Add SoC specific lowlevel_init function
On i.MX6ul(l) (Cortex A7) We have to set the SMP bit before
enabling the caches, otherwise they won't work. Add a SoC specific
lowlevel_init function to be called by the i.MX6ul(l) boards.
Since this is a quirk of the Cortex A7 core we put the functionality
into a separate function to be reused by other Cortex A7 cores.
Change existing i.MX6ul(l) boards to use the new initialisation
function. It seems this is only needed when booting from USB,
in other boot modes the ROM will already have done the initialisation.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/barebox-arm-head.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/barebox-arm-head.h b/arch/arm/include/asm/barebox-arm-head.h index 0a2eb6bdca..bd9c9b1c4f 100644 --- a/arch/arm/include/asm/barebox-arm-head.h +++ b/arch/arm/include/asm/barebox-arm-head.h @@ -6,6 +6,7 @@ #ifndef __ASSEMBLY__ void arm_cpu_lowlevel_init(void); +void cortex_a7_lowlevel_init(void); /* * 32 bytes at this offset is reserved in the barebox head for board/SoC |