ARM: at91: import lowlevel clock initialization from at91bootstrap

For use by future at91 first stage bootloaders, this commit imports
https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/driver/pmc.c

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

3 files changed, 100 insertions, 4 deletions

diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index bbbd497afa..4d60becefb 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -50,14 +50,19 @@
 #define		AT91_PMC_OSCBYPASS	(1    <<  1)		/* Oscillator Bypass */
 #define		AT91_PMC_MOSCRCEN	(1    <<  3)		/* Main On-Chip RC Oscillator Enable [some SAM9] */
 #define		AT91_PMC_OSCOUNT	(0xff <<  8)		/* Main Oscillator Start-up Time */
-#define		AT91_PMC_KEY		(0x37 << 16)		/* MOR Writing Key */
+#define			AT91_PMC_OSCOUNT_(x) ((x) << 8)
+#define		AT91_PMC_KEY_MASK	(0xff << 16)		/* MOR Writing Key */
+#define			AT91_PMC_KEY		(0x37 << 16)
 #define		AT91_PMC_MOSCSEL	(1    << 24)		/* Main Oscillator Selection [some SAM9] */
 #define		AT91_PMC_CFDEN		(1    << 25)		/* Clock Failure Detector Enable [some SAM9] */
 
 #define	AT91_CKGR_MCFR		0x24			/* Main Clock Frequency Register */
 #define		AT91_PMC_MAINF		(0xffff <<  0)		/* Main Clock Frequency */
-#define		AT91_PMC_MAINRDY	(1	<< 16)		/* Main Clock Ready */
-
+#define		AT91_PMC_MAINRDY        (1      << 16)          /* Main Clock Frequency Measure Ready */
+#define		AT91_PMC_RCMEAS         (1      << 20)          /* RC Oscillator Frequency Measure (write-only) */
+#define		AT91_PMC_CCSS           (1      << 24)          /* Counter Clock Source Selection */
+#define			AT91_PMC_CCSS_RC_OSC    (0      << 24)          /* MAINF counter clock is the RC oscillator. */
+#define			AT91_PMC_CCSS_XTAL_OSC  (1      << 24)          /* MAINF counter clock is the crystal oscillator. */
 #define	AT91_CKGR_PLLAR		0x28			/* PLL A Register */
 #define	AT91_CKGR_PLLBR		0x2c			/* PLL B Register */
 #define		AT91_PMC_DIV		(0xff  <<  0)		/* Divider */
@@ -133,6 +138,7 @@
 #define			AT91_PMC_CSSMCK_MCK		(1 << 8)
 
 #define	AT91_PMC_IER		0x60			/* Interrupt Enable Register */
+#define		AT91_PMC_MOSCXTS	(1 << 0)		/* Oscillator Startup Time */
 #define	AT91_PMC_IDR		0x64			/* Interrupt Disable Register */
 #define	AT91_PMC_SR		0x68			/* Status Register */
 #define		AT91_PMC_MOSCS		(1 <<  0)		/* MOSCS Flag */
@@ -148,6 +154,17 @@
 #define		AT91_PMC_MOSCRCS	(1 << 17)		/* Main On-Chip RC [some SAM9] */
 #define		AT91_PMC_CFDEV		(1 << 18)		/* Clock Failure Detector Event [some SAM9] */
 #define	AT91_PMC_IMR		0x6c			/* Interrupt Mask Register */
+#define	AT91_PMC_PLLICPR	0x80			/* PLL Charge Pump Current Register */
+#define		AT91_PMC_ICPPLLA	(0xf <<  0)
+#define			AT91_PMC_ICPPLLA_0		(0 <<  0)
+#define			AT91_PMC_ICPPLLA_1		(1 <<  0)
+#define		AT91_PMC_REALLOCK	(0x1 <<  7)
+#define		AT91_PMC_IPLLA		(0xf <<  8)
+#define			AT91_PMC_IPLLA_0		(0 <<  8)
+#define			AT91_PMC_IPLLA_1		(1 <<  8)
+#define			AT91_PMC_IPLLA_2		(2 <<  8)
+#define			AT91_PMC_IPLLA_3		(3 <<  8)
+
 
 #define AT91_PMC_PROT		0xe4			/* Write Protect Mode Register [some SAM9] */
 #define		AT91_PMC_WPEN		(0x1  <<  0)		/* Write Protect Enable */
@@ -163,6 +180,7 @@
 #define AT91_PMC_PCR		0x10c			/* Peripheral Control Register [some SAM9] */
 #define		AT91_PMC_PCR_PID	(0x3f  <<  0)		/* Peripheral ID */
 #define		AT91_PMC_PCR_CMD	(0x1  <<  12)		/* Command */
+#define		AT91_PMC_PCR_DIV_MASK	(0x3  <<  16)
 #define		AT91_PMC_PCR_DIV(n)	((n) <<  16)	/* Divisor value */
 #define			AT91_PMC_PCR_DIV0	0x0		/* Peripheral clock is MCK */
 #define			AT91_PMC_PCR_DIV2	0x1		/* Peripheral clock is MCK/2 */
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc_ll.h b/arch/arm/mach-at91/include/mach/at91_pmc_ll.h
new file mode 100644
index 0000000000..eda40e8e12
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_pmc_ll.h
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: BSD-1-Clause
+/*
+ * Copyright (c) 2006, Atmel Corporation
+ */
+
+#ifndef AT91_PMC_LL_H
+#define AT91_PMC_LL_H
+
+#include <errno.h>
+#include <asm/io.h>
+#include <mach/at91_pmc.h>
+
+#define AT91_PMC_LL_FLAG_SAM9X5_PMC	(1 << 0)
+#define AT91_PMC_LL_FLAG_MEASURE_XTAL	(1 << 1)
+#define AT91_PMC_LL_FLAG_DISABLE_RC	(1 << 2)
+
+#define AT91_PMC_LL_AT91RM9200	(0)
+#define AT91_PMC_LL_AT91SAM9260	(0)
+#define AT91_PMC_LL_AT91SAM9261	(0)
+#define AT91_PMC_LL_AT91SAM9263	(0)
+#define AT91_PMC_LL_AT91SAM9G45	(0)
+#define AT91_PMC_LL_AT91SAM9X5	(AT91_PMC_LL_FLAG_SAM9X5_PMC | \
+				 AT91_PMC_LL_FLAG_DISABLE_RC)
+#define AT91_PMC_LL_AT91SAM9N12	(AT91_PMC_LL_FLAG_SAM9X5_PMC | \
+				 AT91_PMC_LL_FLAG_DISABLE_RC)
+#define AT91_PMC_LL_SAMA5D2	(AT91_PMC_LL_FLAG_SAM9X5_PMC | \
+				 AT91_PMC_LL_FLAG_MEASURE_XTAL)
+#define AT91_PMC_LL_SAMA5D3	(AT91_PMC_LL_FLAG_SAM9X5_PMC | \
+				 AT91_PMC_LL_FLAG_DISABLE_RC)
+#define AT91_PMC_LL_SAMA5D4	(AT91_PMC_LL_FLAG_SAM9X5_PMC)
+
+void at91_pmc_init(void __iomem *pmc_base, unsigned int flags);
+void at91_pmc_cfg_mck(void __iomem *pmc_base, u32 pmc_mckr, unsigned int flags);
+void at91_pmc_cfg_plla(void __iomem *pmc_base, u32 pmc_pllar, unsigned int flags);
+
+static inline void at91_pmc_init_pll(void __iomem *pmc_base, u32 pmc_pllicpr)
+{
+	writel(pmc_pllicpr, pmc_base + AT91_PMC_PLLICPR);
+}
+
+static inline void at91_pmc_enable_system_clock(void __iomem *pmc_base,
+						unsigned clock_id)
+{
+	writel(clock_id, pmc_base +  AT91_PMC_SCER);
+}
+
+static inline int at91_pmc_enable_periph_clock(void __iomem *pmc_base,
+					       unsigned periph_id)
+{
+	u32 mask = 0x01 << (periph_id % 32);
+
+	if ((periph_id / 32) == 1)
+		writel(mask, pmc_base + AT91_PMC_PCER1);
+	else if ((periph_id / 32) == 0)
+		writel(mask, pmc_base + AT91_PMC_PCER);
+	else
+		return -EINVAL;
+
+	return 0;
+}
+
+static inline int at91_pmc_sam9x5_enable_periph_clock(void __iomem *pmc_base,
+						      unsigned periph_id)
+{
+       u32 pcr = periph_id;
+
+       if (periph_id >= 0x80) /* 7 bits only */
+               return -EINVAL;
+
+       writel(pcr, pmc_base + AT91_PMC_PCR);
+       pcr |= readl(pmc_base + AT91_PMC_PCR) & AT91_PMC_PCR_DIV_MASK;
+       pcr |= AT91_PMC_PCR_CMD | AT91_PMC_PCR_EN;
+       writel(pcr, pmc_base + AT91_PMC_PCR);
+
+       return 0;
+}
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h
index f0e53610c6..cd2102c20e 100644
--- a/arch/arm/mach-at91/include/mach/sama5d3.h
+++ b/arch/arm/mach-at91/include/mach/sama5d3.h
@@ -92,7 +92,7 @@
 #define SAMA5D3_BASE_RSTC	0xfffffe00
 #define SAMA5D3_BASE_PIT	0xfffffe30
 #define SAMA5D3_BASE_WDT	0xfffffe40
-
+#define SAMA5D3_BASE_PMC	0xfffffc00
 #define SAMA5D3_BASE_PMECC	0xffffc070
 #define SAMA5D3_BASE_PMERRLOC	0xffffc500