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author | Matteo Fortini <matteo.fortini@gmail.com> | 2014-07-21 18:13:26 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2014-07-31 14:40:11 +0200 |
commit | 322f0ef9efe300341f5d749e10e4a8ff206e4476 (patch) | |
tree | e103b024973b23ef34f8d5511580d65ee5602ebf /arch/arm/mach-at91/include | |
parent | 0dad2766f157dd0f05faa8416236e8c2a0ba6a2e (diff) | |
download | barebox-322f0ef9efe300341f5d749e10e4a8ff206e4476.tar.gz barebox-322f0ef9efe300341f5d749e10e4a8ff206e4476.tar.xz |
sama5d3x: fix HSMC MODE register offset and add TIMINGS register
As stated in section 29.19.35 of SAMA5D3 Series Datasheet,
MODE register has offset 0x10 and at offset 0x0C there is
a TIMINGS register.
Signed-off-by: Matteo Fortini <matteo.fortini@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-at91/include')
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91sam9_smc.h | 33 |
1 files changed, 32 insertions, 1 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_smc.h b/arch/arm/mach-at91/include/mach/at91sam9_smc.h index d5cf5f762d..d19cf82eca 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9_smc.h +++ b/arch/arm/mach-at91/include/mach/at91sam9_smc.h @@ -43,12 +43,24 @@ struct sam9_smc_config { /* Mode register */ u32 mode; u8 tdf_cycles:4; + + /* Timings register */ + u8 tclr; + u8 tadl; + u8 tar; + u8 ocms; + u8 trr; + u8 twb; + u8 rbnsel; + u8 nfsel; }; extern void sam9_smc_configure(int id, int cs, struct sam9_smc_config *config); extern void sam9_smc_read(int id, int cs, struct sam9_smc_config *config); extern void sam9_smc_read_mode(int id, int cs, struct sam9_smc_config *config); extern void sam9_smc_write_mode(int id, int cs, struct sam9_smc_config *config); + +extern void sama5_smc_configure(int id, int cs, struct sam9_smc_config *config); #endif #define AT91_SMC_SETUP 0x00 /* Setup Register for CS n */ @@ -77,7 +89,26 @@ extern void sam9_smc_write_mode(int id, int cs, struct sam9_smc_config *config); #define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */ #define AT91_SMC_NRDCYCLE_(x) ((x) << 16) -#define AT91_SMC_MODE 0x0c /* Mode Register for CS n */ +#define AT91_SAMA5_SMC_TIMINGS 0x0c /* Timings register for CS n */ +#define AT91_SMC_TCLR (0x0f << 0) /* CLE to REN Low Delay */ +#define AT91_SMC_TCLR_(x) ((x) << 0) +#define AT91_SMC_TADL (0x0f << 4) /* ALE to Data Start */ +#define AT91_SMC_TADL_(x) ((x) << 4) +#define AT91_SMC_TAR (0x0f << 8) /* ALE to REN Low Delay */ +#define AT91_SMC_TAR_(x) ((x) << 8) +#define AT91_SMC_OCMS (0x1 << 12) /* Off Chip Memory Scrambling Enable */ +#define AT91_SMC_OCMS_(x) ((x) << 12) +#define AT91_SMC_TRR (0x0f << 16) /* Ready to REN Low Delay */ +#define AT91_SMC_TRR_(x) ((x) << 16) +#define AT91_SMC_TWB (0x0f << 24) /* WEN High to REN to Busy */ +#define AT91_SMC_TWB_(x) ((x) << 24) +#define AT91_SMC_RBNSEL (0x07 << 28) /* Ready/Busy Line Selection */ +#define AT91_SMC_RBNSEL_(x) ((x) << 28) +#define AT91_SMC_NFSEL (0x01 << 31) /* Nand Flash Selection */ +#define AT91_SMC_NFSEL_(x) ((x) << 31) + +#define AT91_SAM9_SMC_MODE 0xc +#define AT91_SAMA5_SMC_MODE 0x10 #define AT91_SMC_READMODE (1 << 0) /* Read Mode */ #define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ #define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */ |