at91rm9200ek: move reset vector to board code

Include deletion of now unused at91rm9200_lowlevel_init.c
and related CONFIG symbols

Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Reviewed-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

3 files changed, 0 insertions, 137 deletions

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 1d2ac085df..74e1a862b9 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -47,8 +47,6 @@ config AT91SAM9260_LWL
 	bool
 config AT91SAM9263_LWL
 	bool
-config AT91RM9200_LWL
-	bool
 
 config AT91SAM9_SMC
 	bool
@@ -251,7 +249,6 @@ choice
 config MACH_AT91RM9200EK
 	bool "Atmel AT91RM9200-EK Evaluation Kit"
 	select HAVE_AT91_DATAFLASH_CARD
-	select AT91RM9200_LWL
 	help
 	  Select this if you are using Atmel's AT91RM9200-EK Evaluation Kit.
 	  <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3507>
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index c430498ffa..7193b8690c 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -10,7 +10,6 @@ obj-$(CONFIG_AT91_BOOTSTRAP)	+= bootstrap.o
 
 lwl-$(CONFIG_AT91SAM926X_LWL)	+= at91sam926x_lowlevel_init.o
 
-lwl-$(CONFIG_AT91RM9200_LWL)	+= at91rm9200_lowlevel_init.o
 lwl-$(CONFIG_AT91SAM9260_LWL)	+= at91sam9260_lowlevel_init.o
 lwl-$(CONFIG_AT91SAM9263_LWL)	+= at91sam9263_lowlevel_init.o
 
diff --git a/arch/arm/mach-at91/at91rm9200_lowlevel_init.c b/arch/arm/mach-at91/at91rm9200_lowlevel_init.c
deleted file mode 100644
index f78e368086..0000000000
--- a/arch/arm/mach-at91/at91rm9200_lowlevel_init.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * Under GPLv2
- */
-
-#define __LOWLEVEL_INIT__
-
-#include <common.h>
-#include <asm/system.h>
-#include <asm/barebox-arm.h>
-#include <asm/barebox-arm-head.h>
-#include <mach/hardware.h>
-#include <mach/at91rm9200.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_pio.h>
-#include <mach/at91_pmc.h>
-#include <mach/io.h>
-#include <init.h>
-
-void static inline access_sdram(void)
-{
-	writel(0x00000000, AT91_SDRAM_BASE);
-}
-
-void __naked __bare_init barebox_arm_reset_vector(void)
-{
-	u32 r;
-	int i;
-
-	arm_cpu_lowlevel_init();
-
-	/*
-	 * PMC Check if the PLL is already initialized
-	 */
-	r = at91_pmc_read(AT91_PMC_MCKR);
-	if (r & AT91_PMC_CSS)
-		goto end;
-
-	/*
-	 * Enable the Main Oscillator
-	 */
-	at91_pmc_write(AT91_CKGR_MOR, CONFIG_SYS_MOR_VAL);
-
-	do {
-		r = at91_pmc_read(AT91_PMC_SR);
-	} while (!(r & AT91_PMC_MOSCS));
-
-	/*
-	 * EBI_CFGR
-	 */
-	at91_sys_write(AT91_EBI_CFGR, CONFIG_SYS_EBI_CFGR_VAL);
-
-	/*
-	 * SMC2_CSR[0]: 16bit, 2 TDF, 4 WS
-	 */
-	at91_sys_write(AT91_SMC_CSR(0), CONFIG_SYS_SMC_CSR0_VAL);
-
-	/*
-	 * Init Clocks
-	 */
-
-	/*
-	 * PLLAR: x MHz for PCK
-	 */
-	at91_pmc_write(AT91_CKGR_PLLAR, CONFIG_SYS_PLLAR_VAL);
-
-	do {
-		r = at91_pmc_read(AT91_PMC_SR);
-	} while (!(r & AT91_PMC_LOCKA));
-
-	/*
-	 * PCK/x = MCK Master Clock from SLOW
-	 */
-	at91_pmc_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR2_VAL1);
-
-	/*
-	 * PCK/x = MCK Master Clock from PLLA
-	 */
-	at91_pmc_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR2_VAL2);
-
-	do {
-		r = at91_pmc_read(AT91_PMC_SR);
-	} while (!(r & AT91_PMC_MCKRDY));
-
-	/*
-	 * Init SDRAM
-	 */
-
-	/* PIOC_ASR: Configure PIOC as peripheral (D16/D31) */
-	__raw_writel(CONFIG_SYS_PIOC_ASR_VAL, AT91_BASE_PIOC + PIO_ASR);
-	/* PIOC_BSR */
-	__raw_writel(CONFIG_SYS_PIOC_BSR_VAL, AT91_BASE_PIOC + PIO_BSR);
-	/* PIOC_PDR */
-	__raw_writel(CONFIG_SYS_PIOC_PDR_VAL, AT91_BASE_PIOC + PIO_PDR);
-
-	/* EBI_CSA : CS1=SDRAM */
-	at91_sys_write(AT91_EBI_CSA, CONFIG_SYS_EBI_CSA_VAL);
-
-	/* SDRC_CR */
-	at91_sys_write(AT91_SDRAMC_CR, CONFIG_SYS_SDRC_CR_VAL);
-	/* SDRC_MR : Precharge All */
-	at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_PRECHARGE);
-	/* access SDRAM */
-	access_sdram();
-	/* SDRC_MR : refresh */
-	at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_REFRESH);
-
-	/* access SDRAM 8 times */
-	for (i = 0; i < 8; i++)
-		access_sdram();
-
-	/* SDRC_MR : Load Mode Register */
-	at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_LMR);
-	/* access SDRAM */
-	access_sdram();
-	/* SDRC_TR : Write refresh rate */
-	at91_sys_write(AT91_SDRAMC_TR, CONFIG_SYS_SDRC_TR_VAL);
-	/* access SDRAM */
-	access_sdram();
-	/* SDRC_MR : Normal Mode */
-	at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NORMAL);
-	/* access SDRAM */
-	access_sdram();
-
-	/* switch from FastBus to Asynchronous clock mode */
-	r = get_cr();
-	r |= 0xC0000000;	/* set bit 31 (iA) and 30 (nF) */
-	set_cr(r);
-
-end:
-	barebox_arm_entry(AT91_CHIPSELECT_1, at91rm9200_get_sdram_size(), NULL);
-}