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| author | Raphaël Poggi <poggi.raph@gmail.com> | 2014-09-08 15:37:37 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2014-09-10 08:19:04 +0200 |
| commit | 29ebbf33c2ec076b85dde362437239de32097c91 (patch) | |
| tree | e7a212fe72b0b9c507b3d48422dad56902986050 /arch/arm/mach-at91 | |
| parent | 5a5ba5ad30f22f0e3a4c0c56d180261136e3dfe4 (diff) | |
| download | barebox-29ebbf33c2ec076b85dde362437239de32097c91.tar.gz barebox-29ebbf33c2ec076b85dde362437239de32097c91.tar.xz | |
mach-at91: declare device tree clock
This commit use the clkdev_add_physbase function, to declare device tree and non device tree gpio clocks.
Signed-off-by: Raphaël Poggi <poggi.raph@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-at91')
| -rw-r--r-- | arch/arm/mach-at91/at91sam9g45.c | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c index 9a50debb16..ce6ce90db2 100644 --- a/arch/arm/mach-at91/at91sam9g45.c +++ b/arch/arm/mach-at91/at91sam9g45.c @@ -192,11 +192,6 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci1", &mmc1_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi0", &spi0_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi1", &spi1_clk), - CLKDEV_DEV_ID("at91rm9200-gpio0", &pioA_clk), - CLKDEV_DEV_ID("at91rm9200-gpio1", &pioB_clk), - CLKDEV_DEV_ID("at91rm9200-gpio2", &pioC_clk), - CLKDEV_DEV_ID("at91rm9200-gpio3", &pioDE_clk), - CLKDEV_DEV_ID("at91rm9200-gpio4", &pioDE_clk), CLKDEV_DEV_ID("at91-pit", &mck), CLKDEV_CON_DEV_ID("hck1", "atmel_lcdfb", &lcdc_clk), }; @@ -238,6 +233,14 @@ static void __init at91sam9g45_register_clocks(void) clkdev_add_table(usart_clocks_lookups, ARRAY_SIZE(usart_clocks_lookups)); + clkdev_add_physbase(&twi0_clk, AT91SAM9G45_BASE_TWI0, NULL); + clkdev_add_physbase(&twi1_clk, AT91SAM9G45_BASE_TWI1, NULL); + clkdev_add_physbase(&pioA_clk, AT91SAM9G45_BASE_PIOA, NULL); + clkdev_add_physbase(&pioB_clk, AT91SAM9G45_BASE_PIOB, NULL); + clkdev_add_physbase(&pioC_clk, AT91SAM9G45_BASE_PIOC, NULL); + clkdev_add_physbase(&pioDE_clk, AT91SAM9G45_BASE_PIOD, NULL); + clkdev_add_physbase(&pioDE_clk, AT91SAM9G45_BASE_PIOE, NULL); + if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11()) clk_register(&vdec_clk); |