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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2015-11-20 12:07:03 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2015-11-30 08:22:31 +0100 |
| commit | 7da99e58bdf6ccf421dacd83e5c9d1231c12507b (patch) | |
| tree | 496ac1c5231931e7ad391143c2a8a28b8e4569e9 /arch/arm/mach-imx/clk-imx5.c | |
| parent | e7a8519963fcb235a123dfe5e7dd59d6fb2eaf9e (diff) | |
| download | barebox-7da99e58bdf6ccf421dacd83e5c9d1231c12507b.tar.gz barebox-7da99e58bdf6ccf421dacd83e5c9d1231c12507b.tar.xz | |
video: i.MX IPUv3: Set ldb clocks correctly
The clocks for the LVDS display bridge have a fixed /3.5 and a
configurable /1,/2 divider in their path. The configurable divider has
to be explicitly configured for single/dual channel support, so we can't
rely on clock rate parent propagation here. Clear the
CLK_SET_RATE_PARENT flag for the configurable divider and configure the
clock explicitly in the ldb driver.
Tested on a custom i.MX6 board, currently untested on i.MX53.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-imx/clk-imx5.c')
| -rw-r--r-- | arch/arm/mach-imx/clk-imx5.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/clk-imx5.c b/arch/arm/mach-imx/clk-imx5.c index 6dc3c8008e..70db31c18e 100644 --- a/arch/arm/mach-imx/clk-imx5.c +++ b/arch/arm/mach-imx/clk-imx5.c @@ -332,7 +332,7 @@ static struct driver_d imx51_ccm_driver = { static void mx53_clocks_ipu_init(void __iomem *regs) { clks[IMX5_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); - clks[IMX5_CLK_LDB_DI1_DIV] = imx_clk_divider("ldb_di1_div", "ldb_di1_div_3_5", regs + CCM_CSCMR2, 11, 1); + clks[IMX5_CLK_LDB_DI1_DIV] = imx_clk_divider_np("ldb_di1_div", "ldb_di1_div_3_5", regs + CCM_CSCMR2, 11, 1); clks[IMX5_CLK_LDB_DI1_SEL] = imx_clk_mux_p("ldb_di1_sel", regs + CCM_CSCMR2, 9, 1, mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel)); clks[IMX5_CLK_DI_PLL4_PODF] = imx_clk_divider("di_pll4_podf", "pll4_sw", regs + CCM_CDCDR, 16, 3); |