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authorSascha Hauer <s.hauer@pengutronix.de>2012-10-12 15:21:13 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2012-10-17 20:22:58 +0200
commit4ad34853f13e6fa62cf2b234f60655f6ff517d81 (patch)
tree2c8507d75c8f2e648af2ae648fef71c229a871e9 /arch/arm/mach-imx/imx53.c
parentb1b76f60279aa53a9ba65acc2be028cb7c415d48 (diff)
downloadbarebox-4ad34853f13e6fa62cf2b234f60655f6ff517d81.tar.gz
barebox-4ad34853f13e6fa62cf2b234f60655f6ff517d81.tar.xz
ARM i.MX53: enable imx53_init_lowlevel for pbl
The KARO Tx53 board in the revision 8030 has an instable SDRAM setup. It works as long as the MMU is disabled, but the board crashes at arbitrary places once the MMU gets enabled. So we need the PLL setup early. Enable it for pbl. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-imx/imx53.c')
-rw-r--r--arch/arm/mach-imx/imx53.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/imx53.c b/arch/arm/mach-imx/imx53.c
index 38b94fcc80..cac7b74c17 100644
--- a/arch/arm/mach-imx/imx53.c
+++ b/arch/arm/mach-imx/imx53.c
@@ -191,6 +191,8 @@ void imx53_init_lowlevel(unsigned int cpufreq_mhz)
writel(0xffffffff, ccm + MX5_CCM_CCGR6);
writel(0xffffffff, ccm + MX53_CCM_CCGR7);
- clock_notifier_call_chain();
+ if (!IS_ENABLED(__PBL__))
+ clock_notifier_call_chain();
+
writel(0, ccm + MX5_CCM_CCDR);
}