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| author | Andrey Smirnov <andrew.smirnov@gmail.com> | 2018-06-12 11:48:00 -0700 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-06-13 09:56:21 +0200 |
| commit | 5adbb4b01249184d353d27a40cab9964907b246b (patch) | |
| tree | 6c7f341f8075bf45f6fa91ab3c942e87c623003d /arch/arm/mach-imx | |
| parent | 96b673d03d1321cc3896bfe4b4d0733647ea14f8 (diff) | |
| download | barebox-5adbb4b01249184d353d27a40cab9964907b246b.tar.gz barebox-5adbb4b01249184d353d27a40cab9964907b246b.tar.xz | |
VFxxx: DCD: Remove read leveling and gate training delays
Read leveling delays are being specified as zero, so they are as good
as disabled and can be safely dropped.
Gate training delay is specified as 4/128 tCK for both data
slices. This setting, when applied to Data Byte 1, makes that slice
unusable* during POR startup which is somehow is mitigated by
double-reset hack in DCD.
Dropping gate training delays allows both VF610 Tower board and ZII
VF610 Dev board to sucessfully PoR-boot without the need for double
resetting of the DDRMC.
* The board fails to boot. When examined via JTAG in such a state
only even bytes of DDR memory are functional.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-imx')
| -rw-r--r-- | arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-cr-default.imxcfg | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-cr-default.imxcfg b/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-cr-default.imxcfg index 956cc5c58b..8c411ddc7e 100644 --- a/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-cr-default.imxcfg +++ b/arch/arm/mach-imx/include/mach/flash-header/vf610-ddr-cr-default.imxcfg @@ -107,10 +107,6 @@ wm 32 DDRMC_CR88 0x00040000 wm 32 DDRMC_CR89 0x00000002 wm 32 DDRMC_CR91 0x00020000 wm 32 DDRMC_CR96 0x00002819 -wm 32 DDRMC_CR102 0x00010100 -wm 32 DDRMC_CR105 0x00000000 -wm 32 DDRMC_CR106 0x00000004 -wm 32 DDRMC_CR110 0x00040000 wm 32 DDRMC_CR117 0x00000000 wm 32 DDRMC_CR118 0x01010000 wm 32 DDRMC_CR120 0x02020000 |