mxs: get_fecclk is hclk, not a constant

The fec has multiple clock inputs:

- 50MHz clock for generating the (R)MII clock
- bus clock

The MDIO clock is derived from the bus clock, not the 50MHz clock,
so pass this into the driver so that it can correctly configure
the MDIO clock divider.
This fixes several wrong MDIO register read problems on i.MX28 boards.

Reported-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

1 files changed, 1 insertions, 2 deletions

diff --git a/arch/arm/mach-mxs/speed-imx28.c b/arch/arm/mach-mxs/speed-imx28.c
index df55f64c24..2cab42d8f5 100644
--- a/arch/arm/mach-mxs/speed-imx28.c
+++ b/arch/arm/mach-mxs/speed-imx28.c
@@ -121,8 +121,7 @@ unsigned imx_get_xtalclk(void)
 
 unsigned imx_get_fecclk(void)
 {
-	/* this PLL always runs at 50 MHz */
-	return 50000000;
+	return imx_get_hclk();
 }