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| author | Wolfram Sang <w.sang@pengutronix.de> | 2012-10-30 15:21:13 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2012-10-31 08:36:51 +0100 |
| commit | c2ae23e9dfdf4b2016b59f320f1222e5fd3daf9a (patch) | |
| tree | 60de4a4bf4aaecd0c7b1b42ded630831e6271f40 /arch/arm/mach-mxs | |
| parent | 2d1ceaff2f905f4a2bd7e6c539e7dd3d8d8e9bef (diff) | |
| download | barebox-c2ae23e9dfdf4b2016b59f320f1222e5fd3daf9a.tar.gz barebox-c2ae23e9dfdf4b2016b59f320f1222e5fd3daf9a.tar.xz | |
arm: mxs: use timeouts in block reset routines
These routines can fail, add support for that. Also, put in missing
copyright headers.
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-mxs')
| -rw-r--r-- | arch/arm/mach-mxs/common.c | 39 |
1 files changed, 35 insertions, 4 deletions
diff --git a/arch/arm/mach-mxs/common.c b/arch/arm/mach-mxs/common.c index 3730633c71..122d88362b 100644 --- a/arch/arm/mach-mxs/common.c +++ b/arch/arm/mach-mxs/common.c @@ -1,8 +1,26 @@ +/* + * Freescale i.MXS common code + * + * Copyright (C) 2012 Wolfram Sang <w.sang@pengutronix.de> + * + * Based on code from LTIB: + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + #include <common.h> #include <io.h> +#include <errno.h> +#include <clock.h> #include <mach/mxs.h> #include <mach/imx-regs.h> +#define MXS_IP_RESET_TIMEOUT (10 * MSECOND) + #define MXS_BLOCK_SFTRST (1 << 31) #define MXS_BLOCK_CLKGATE (1 << 30) @@ -10,7 +28,9 @@ int mxs_reset_block(void __iomem *reg, int just_enable) { /* Clear SFTRST */ writel(MXS_BLOCK_SFTRST, reg + BIT_CLR); - mdelay(1); + + if (wait_on_timeout(MXS_IP_RESET_TIMEOUT, !(readl(reg) & MXS_BLOCK_SFTRST))) + goto timeout; /* Clear CLKGATE */ writel(MXS_BLOCK_CLKGATE, reg + BIT_CLR); @@ -18,16 +38,27 @@ int mxs_reset_block(void __iomem *reg, int just_enable) if (!just_enable) { /* Set SFTRST */ writel(MXS_BLOCK_SFTRST, reg + BIT_SET); - mdelay(1); + + /* Wait for CLKGATE being set */ + if (wait_on_timeout(MXS_IP_RESET_TIMEOUT, readl(reg) & MXS_BLOCK_CLKGATE)) + goto timeout; } /* Clear SFTRST */ writel(MXS_BLOCK_SFTRST, reg + BIT_CLR); - mdelay(1); + + if (wait_on_timeout(MXS_IP_RESET_TIMEOUT, !(readl(reg) & MXS_BLOCK_SFTRST))) + goto timeout; /* Clear CLKGATE */ writel(MXS_BLOCK_CLKGATE, reg + BIT_CLR); - mdelay(1); + + if (wait_on_timeout(MXS_IP_RESET_TIMEOUT, !(readl(reg) & MXS_BLOCK_CLKGATE))) + goto timeout; return 0; + +timeout: + printf("MXS: Timeout resetting block via register 0x%p\n", reg); + return -ETIMEDOUT; } |