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author | Oleg Karfich <oleg.karfich@wago.com> | 2018-11-07 07:35:28 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-12-20 08:50:49 +0100 |
commit | 2621259c52bd5db5de9da120fe20bee8c60b276e (patch) | |
tree | 3e2e6837936b2fa3129bf721524529028d5dc41f /arch/arm/mach-omap | |
parent | e61b7432212ab5fcf61b7e1d33fcf6727ba84fdd (diff) | |
download | barebox-2621259c52bd5db5de9da120fe20bee8c60b276e.tar.gz barebox-2621259c52bd5db5de9da120fe20bee8c60b276e.tar.xz |
ARM: omap3: Add support for reset reason detection
Due to the Errata i520, the reset code in the linux kernel aswell in barebox
triggers a cpu reset by setting the bit RST_DPLL3 in the PRM_RSTCTRL register.
This induces a global cold reset on the chip. So we will always detect a POR as
reset source when a reboot of the chip is triggerd. Other states like WDG, JTAG
were tested successfully.
Signed-off-by: Oleg Karfich <oleg.karfich@wago.com>
Diffstat (limited to 'arch/arm/mach-omap')
-rw-r--r-- | arch/arm/mach-omap/omap3_generic.c | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/arch/arm/mach-omap/omap3_generic.c b/arch/arm/mach-omap/omap3_generic.c index 348a00cdff..cff4a4fb11 100644 --- a/arch/arm/mach-omap/omap3_generic.c +++ b/arch/arm/mach-omap/omap3_generic.c @@ -44,6 +44,7 @@ #include <mach/sys_info.h> #include <mach/syslib.h> #include <mach/omap3-generic.h> +#include <reset_source.h> /** * @brief Reset the CPU @@ -490,12 +491,60 @@ static int omap3_bootsource(void) return 0; } +#define OMAP3_PRM_RSTST_OFF 0x8 +#define OMAP3_REG_PRM_RSTST (OMAP3_PRM_REG(RSTCTRL) + OMAP3_PRM_RSTST_OFF) + +#define OMAP3_ICECRUSHER_RST BIT(10) +#define OMAP3_ICEPICK_RST BIT(9) +#define OMAP3_EXTERNAL_WARM_RST BIT(6) +#define OMAP3_SECURE_WD_RST BIT(5) +#define OMAP3_MPU_WD_RST BIT(4) +#define OMAP3_SECURITY_VIOL_RST BIT(3) +#define OMAP3_GLOBAL_SW_RST BIT(1) +#define OMAP3_GLOBAL_COLD_RST BIT(0) + +static void omap3_detect_reset_reason(void) +{ + uint32_t val = 0; + + val = readl(OMAP3_REG_PRM_RSTST); + /* clear OMAP3_PRM_RSTST - must be cleared by software */ + writel(val, OMAP3_REG_PRM_RSTST); + + switch (val) { + case OMAP3_ICECRUSHER_RST: + case OMAP3_ICEPICK_RST: + reset_source_set(RESET_JTAG); + break; + case OMAP3_EXTERNAL_WARM_RST: + reset_source_set(RESET_EXT); + break; + case OMAP3_SECURE_WD_RST: + case OMAP3_MPU_WD_RST: + case OMAP3_SECURITY_VIOL_RST: + reset_source_set(RESET_WDG); + break; + case OMAP3_GLOBAL_SW_RST: + reset_source_set(RESET_RST); + break; + case OMAP3_GLOBAL_COLD_RST: + reset_source_set(RESET_POR); + break; + default: + reset_source_set(RESET_UKWN); + break; + } +} + int omap3_init(void) { omap_gpmc_base = (void *)OMAP3_GPMC_BASE; restart_handler_register_fn(omap3_restart_soc); + if (IS_ENABLED(CONFIG_RESET_SOURCE)) + omap3_detect_reset_reason(); + return omap3_bootsource(); } |