ARM: am335x: Changed timer

The 32KHz from dmtimer0 is derived from a SoC internal RC oscillator
which is quite inaccurate. Switch to dmtimer2 which is driven from
the high frequency oscillator clock.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

4 files changed, 48 insertions, 17 deletions

diff --git a/arch/arm/mach-omap/Kconfig b/arch/arm/mach-omap/Kconfig
index af359756ba..87e8d44556 100644
--- a/arch/arm/mach-omap/Kconfig
+++ b/arch/arm/mach-omap/Kconfig
@@ -43,7 +43,7 @@ config ARCH_AM33XX
 	select CPU_V7
 	select GENERIC_GPIO
 	select OFTREE
-	select OMAP_CLOCK_SOURCE_DMTIMER0
+	select OMAP_CLOCK_SOURCE_DMTIMER
 	help
 	  Say Y here if you are using Texas Instrument's AM33xx based platform
 
@@ -51,7 +51,7 @@ config ARCH_AM33XX
 config OMAP_CLOCK_SOURCE_S32K
 	bool
 
-config OMAP_CLOCK_SOURCE_DMTIMER0
+config OMAP_CLOCK_SOURCE_DMTIMER
 	bool
 
 config OMAP_GPMC
diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile
index 65072b91e4..db2856dc5e 100644
--- a/arch/arm/mach-omap/Makefile
+++ b/arch/arm/mach-omap/Makefile
@@ -18,7 +18,7 @@
 obj-$(CONFIG_ARCH_OMAP) += syslib.o omap_devices.o omap_generic.o omap_fb.o
 pbl-$(CONFIG_ARCH_OMAP) += syslib.o
 obj-$(CONFIG_OMAP_CLOCK_SOURCE_S32K) += s32k_clksource.o
-obj-$(CONFIG_OMAP_CLOCK_SOURCE_DMTIMER0) += dmtimer0.o
+obj-$(CONFIG_OMAP_CLOCK_SOURCE_DMTIMER) += dmtimer.o
 obj-$(CONFIG_ARCH_OMAP3) += omap3_generic.o auxcr.o
 pbl-$(CONFIG_ARCH_OMAP3) += omap3_generic.o auxcr.o
 obj-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o
diff --git a/arch/arm/mach-omap/dmtimer0.c b/arch/arm/mach-omap/dmtimer.c
index e536f8d222..56adda080a 100644
--- a/arch/arm/mach-omap/dmtimer0.c
+++ b/arch/arm/mach-omap/dmtimer.c
@@ -1,8 +1,8 @@
 /**
  * @file
- * @brief Support DMTimer0 counter
+ * @brief Support DMTimer counter
  *
- * FileName: arch/arm/mach-omap/dmtimer0.c
+ * FileName: arch/arm/mach-omap/dmtimer.c
  */
 /*
  * This File is based on arch/arm/mach-omap/s32k_clksource.c
@@ -10,7 +10,10 @@
  * Texas Instruments, <www.ti.com>
  * Nishanth Menon <x0nishan@ti.com>
  *
- * (C) Copyright 2012 Teresa Gámez, Phytec Messtechnik GmbH
+ * (C) Copyright 2012 Phytec Messtechnik GmbH
+ * Author: Teresa Gámez <t.gamez@phytec.de>
+ * (C) Copyright 2015 Phytec Messtechnik GmbH
+ * Author: Daniel Schultz <d.schultz@phytec.de>
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -29,6 +32,8 @@
 #include <io.h>
 #include <mach/am33xx-silicon.h>
 
+#include <stdio.h>
+
 #define CLK_RC32K	32768
 
 #define TIDR			0x0
@@ -49,18 +54,20 @@
 #define TSICR			0x54
 #define TCAR2			0x58
 
+static void *base = (void *)AM33XX_DMTIMER2_BASE;
+
 /**
  * @brief Provide a simple counter read
  *
- * @return DMTimer0 counter
+ * @return DMTimer counter
  */
-static uint64_t dmtimer0_read(void)
+static uint64_t dmtimer_read(void)
 {
-	return readl(AM33XX_DMTIMER0_BASE + TCRR);
+	return readl(base + TCRR);
 }
 
-static struct clocksource dmtimer0_cs = {
-	.read	= dmtimer0_read,
+static struct clocksource dmtimer_cs = {
+	.read	= dmtimer_read,
 	.mask	= CLOCKSOURCE_MASK(32),
 	.shift	= 10,
 };
@@ -68,18 +75,38 @@ static struct clocksource dmtimer0_cs = {
 /**
  * @brief Initialize the Clock
  *
- * Enable dmtimer0.
+ * Enable dmtimer.
  *
  * @return result of @ref init_clock
  */
-static int dmtimer0_init(void)
+static int dmtimer_init(void)
 {
-	dmtimer0_cs.mult = clocksource_hz2mult(CLK_RC32K, dmtimer0_cs.shift);
+	u64 clk_speed;
+	int sysboot;
+
+	sysboot = (readl(AM33XX_CTRL_STATUS) >> 22) & 3;
+	switch (sysboot) {
+	case 0:
+		clk_speed = 19200000;
+		break;
+	case 1:
+		clk_speed = 24000000;
+		break;
+	case 2:
+		clk_speed = 25000000;
+		break;
+	case 3:
+		clk_speed = 26000000;
+		break;
+	}
+
+	dmtimer_cs.mult = clocksource_hz2mult(clk_speed, dmtimer_cs.shift);
+
 	/* Enable counter */
-	writel(0x3, AM33XX_DMTIMER0_BASE + TCLR);
+	writel(0x3, base + TCLR);
 
-	return init_clock(&dmtimer0_cs);
+	return init_clock(&dmtimer_cs);
 }
 
 /* Run me at boot time */
-core_initcall(dmtimer0_init);
+core_initcall(dmtimer_init);
diff --git a/arch/arm/mach-omap/include/mach/am33xx-silicon.h b/arch/arm/mach-omap/include/mach/am33xx-silicon.h
index 7c209ec5d8..e17e609879 100644
--- a/arch/arm/mach-omap/include/mach/am33xx-silicon.h
+++ b/arch/arm/mach-omap/include/mach/am33xx-silicon.h
@@ -62,6 +62,9 @@
 
 /* DTMTimer0 */
 #define AM33XX_DMTIMER0_BASE		(AM33XX_L4_WKUP_BASE + 0x205000)
+/* DMTIimer2 */
+#define AM33XX_DMTIMER2_BASE		(AM33XX_L4_PER_BASE + 0x40000)
+#define AM33XX_CM_DPLL			(AM33XX_L4_WKUP_BASE + 0x200500)
 
 /* PRM */
 #define AM33XX_PRM_BASE			(AM33XX_L4_WKUP_BASE + 0x200000)
@@ -73,6 +76,7 @@
 /* CTRL */
 #define AM33XX_CTRL_BASE		(AM33XX_L4_WKUP_BASE + 0x210000)
 #define AM33XX_IDCODE_REG		(AM33XX_CTRL_BASE + 0x600)
+#define AM33XX_CTRL_STATUS		(AM33XX_CTRL_BASE + 0x40)
 
 /* Watchdog Timer */
 #define AM33XX_WDT_BASE			0x44E35000